JP3230294B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device represented by an active matrix type liquid crystal display. More specifically, the present invention relates to a multi-layer wiring technology for a TFT substrate on which a pixel electrode and a switching thin film transistor (TFT) are formed in an integrated manner.

[0002]

2. Description of the Related Art On a TFT substrate used for driving an active matrix type liquid crystal device, a plurality of gate lines and signal lines orthogonal to each other are stacked and arranged.
At each intersection of the two lines, a pixel electrode and a thin film transistor for switching drive are integrated and formed in a matrix. The thin film transistor has a gate electrode connected to a gate line, a source electrode connected to a signal line, and a drain electrode connected to a corresponding pixel electrode. When a gate pulse is applied to a gate line in a line-sequential manner, a corresponding thin film transistor is selected for each row. On the other hand, the image signal supplied via the signal line is written to the corresponding pixel electrode by the selected thin film transistor, and the display driving is performed.

[0003]

FIG. 8 shows an insulating substrate 101.
Gate line 102 and signal line 103 formed above
It is a typical perspective view which shows the intersection of. The gate line 102 is made of a polysilicon thin film linearly patterned in one direction, and the signal line 103 is made of a metal thin film of aluminum or the like linearly patterned in an orthogonal direction. Both lines intersect each other, and the step 104
Occurs. Although not shown, an interlayer insulating film is interposed between the gate line 102 and the signal line 103 to achieve electrical insulation between the two.

[0004] There are countless steps 104, and the substrate 1
On the surface of No. 01, a set of fine irregularities is formed. The substrate surface is covered with a liquid crystal alignment film, and the liquid crystal molecules are aligned by performing a predetermined rubbing treatment or the like. However, there is a problem that uniform rubbing treatment cannot be performed due to minute unevenness due to the step 104, and the orientation of liquid crystal molecules is deteriorated.

FIG. 9 shows a sectional shape of the step portion 104. A signal line 103 crosses over the gate line 102 via an interlayer insulating film 105. The pattern of the gate lines 102 and the signal lines 103 is becoming finer and finer in the device in order to increase the definition of the display device. For this reason, there is a problem that a step break 106 occurs in the aluminum metal pattern forming the signal line 103 in the step portion 104, and disconnection failure frequently occurs.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention eliminates or reduces the steps that occur at the intersections of gate lines and signal lines, and planarizes the substrate surface to achieve a liquid crystal display. It is an object of the present invention to prevent orientation deterioration, prevent a disconnection failure of a wiring, and suppress an increase in wiring resistance. The following measures were taken to achieve this purpose. That is, a plurality of gate lines formed on an insulating substrate, a signal line intersecting the gate line, and a thin film transistor and a pixel electrode are arranged near an intersection of the gate line and the signal line. In a display device having a TFT substrate, the gate line comprises a gate wiring layer formed in a groove or a trench provided in the insulating substrate, and the signal line is formed in another groove or a trench provided in the insulating substrate. the signal wirings from the layer Rutotomoni, the gate wiring layer is the
The polycrystalline semiconductor layer formed along the inner wall of the groove
A metal layer in which the signal wiring layer is embedded in the another groove.
It is characterized by consisting of Preferably, the gate wiring layer and the signal wiring layer are insulated from each other via an intermediate insulating layer at the intersection of the groove and the other groove. For example,
The gate wiring layer is made of a polycrystalline semiconductor layer such as polysilicon formed along the inner wall of the groove, and the signal wiring layer is made of aluminum or a metal layer mainly containing aluminum embedded in the other groove. It is configured.

[0007]

According to the present invention, a so-called trench wiring structure is employed. The polycrystalline semiconductor layer forming the gate line is formed along the inner wall of the trench provided in the main surface of the insulating substrate, and the surface of the substrate is planarized. In order to further planarize, a metal layer forming a signal line is also buried along the trench. In this case, the gate line trench and the signal line trench cross each other. At the intersection, an intermediate insulating layer is interposed to electrically insulate the gate wiring layer and the signal wiring layer from each other. With this configuration, the intersection is completely buried in the main surface of the insulating substrate, and flattening can be realized. Therefore, it is possible to effectively suppress the deterioration of the liquid crystal alignment, to prevent a wiring disconnection failure, and to prevent an increase in wiring resistance.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1A and 1B are schematic diagrams showing a basic configuration of an active matrix type liquid crystal display device according to the present invention. FIG. 1A shows the entire structure, and FIG. This is schematically shown. As shown in (A), this display device has a lower insulating substrate or TFT substrate 1 and an upper glass substrate or counter substrate 2.
Have a flat panel structure in which a liquid crystal layer 3 is sealed and filled in the gap. The liquid crystal layer 3 is, for example, twisted nematic, and the inner surfaces of both substrates are subjected to a predetermined alignment treatment. A pair of polarizing plates 4 and 5 are attached to both sides of the flat panel structure, and a change in molecular orientation of the liquid crystal layer 3 is detected as a change in transmittance.

On the inner principal surface of the TFT substrate 1, pixel electrodes 6 arranged in a matrix are formed. Switching drive thin film transistors or TFTs 7 are integrally formed corresponding to the individual pixel electrodes 6. A plurality of gate lines 8 and signal lines 9 which are orthogonal to each other are also formed by patterning. The gate electrode of the TFT 7 is connected to the corresponding gate line 8, the source electrode is connected to the corresponding signal line 9, and the drain electrode is connected to the corresponding pixel electrode 6.

On the other hand, a common electrode 1 is
0 and a color filter 11 are laminated. Each of the RGB segments of the color filter 11 is a pixel electrode 6
It is aligned to match.

As shown in FIG. 1B, a first groove or trench 12 extending in one direction is formed on the inner surface of the TFT substrate 1. A polycrystalline semiconductor layer 13 made of, for example, polysilicon or the like is deposited along the inner wall of the first trench 12, and constitutes the gate line 8 described above. PSG is formed inside the first trench 12.
A first insulating layer 14 made of (glass to which phosphorus is added) is embedded. As is clear from the figure, the gate line 8
Is buried in the inner surface of the TFT substrate 1 to achieve flattening.

On the other hand, a second trench 15 extends in a direction orthogonal to the first trench 12. Aluminum or a metal layer 17 containing aluminum as a main component is buried inside the second trench 15 via a second insulating layer 16 also made of PSG or the like, and constitutes the signal line 9 described above. The metal layer 17 and the semiconductor layer 13 are electrically separated from each other at intersections by the second insulating layer 16 (intermediate insulating layer). In this example, in addition to the gate line 8, the signal wiring layer constituting the signal line 9 is also provided in the trench, and the surface of the substrate is more effectively flattened. In particular, there is no step at the intersection of the gate line 8 and the signal line 9.

A third insulating layer 18 made of PSG or the like is further coated on the second insulating layer 16 and the metal layer 17 buried in the second trench 15. On top of that, P-Si
An N film 19 is formed to protect the entire wiring layer. In some cases, the P-SiN film 19 is used as a hydrogen diffusion source, and hydrogen is introduced into the semiconductor layer 13 made of polysilicon to reduce the resistance.

FIG. 2 shows the cross-sectional shape of the intersection along the cross section S shown in FIG. As is apparent from the figure, the metal layer 17 constituting the signal line is completely electrically separated from the semiconductor layer 13 constituting the gate line by the second insulating layer 16, and there is a possibility that a wiring short-circuit failure may occur. Absent.

FIG. 3 shows an application example of the trench wiring according to the present invention. A first trench 12 is formed on the inner surface of the TFT substrate 1 along one direction. A semiconductor layer 13 made of polysilicon or the like is formed on the inner wall of the trench 12.
Are deposited, and constitute a gate line. This first
Are filled with a first insulating layer 14 made of PSG.

Along the buried first insulating layer 14, the second
Trench 15 is provided. Therefore, the second trench 15 is provided in parallel with the first trench 12. A metal layer 17 made of aluminum or the like is embedded in the second trench 15. This metal layer 17 forms a part of a signal line in some cases. Alternatively, another wiring portion of the TFT may be formed. In this application example, the semiconductor layer 13 and the metal layer 17 are stacked on each other with the first insulating layer 14 interposed therebetween, and extend along the same trench 12. Therefore, TF
The surface area of the T substrate 1 can be effectively used, and contributes to miniaturization. The stacked structure of the semiconductor layer 13 and the metal layer 17 is further covered by a second insulating layer 16, a third insulating layer 18, and a P-SiN film 19 in order, so that the surface of the substrate 1 is flattened.

FIG. 4 is a graph showing the relationship between the wiring resistance value of the aluminum metal layer formed in the trench and the trench depth. Set the wiring length to 1000 μm and set the wiring width to 2 μm
Is set to As is clear from the graph, the wiring resistance value decreases as the depth of the trench increases. As described above, the trench wiring structure according to the present invention has a remarkable effect in lowering the wiring resistance.

Finally, the steps of forming the trench wiring according to the present invention shown in FIGS. 1 and 2 will be described in detail with reference to a series of process diagrams shown in FIGS. First, in step A of FIG. 5, a quartz substrate 51 is prepared. Quartz glass is excellent in heat resistance, and can make full use of film forming technology and semiconductor manufacturing technology.
Suitable for manufacturing FT substrates. In step B, the substrate 51
A first trench 52 is formed along one direction in the main surface of the first trench 52. The first trench 52 is formed by, for example, wet etching, and preferably has a depth of about 1 to 4 μm. Next, in step C, a polysilicon film 53 is deposited on the entire main surface of the quartz substrate 51. The film thickness is, for example, 400
nm, so that the inner wall of the trench 52 can be completely covered. The polysilicon film 53 is used, for example, as a gate electrode material of a thin film transistor (not shown). Subsequently, in step D, the polysilicon film is patterned into a predetermined shape by dry etching or the like, and a gate wiring layer 54 is formed. This patterning is performed simultaneously with the formation of the gate electrode. The gate wiring layer 54 is formed along the inner wall of the first trench 52 and can contribute to flattening of the substrate 51. In order to reduce the wiring resistance of the gate wiring layer 54, the trench 52 may be provided deeper. In step E, a first insulating layer 55 made of PSG is deposited on the entire surface of the substrate 51. The first trench 5 is formed by forming a film with a thickness of 400 nm using the LPCVD method.
2 can be completely embedded.

In the step F of FIG. 6, the first insulating layer is entirely removed from the surface of the substrate 51, and the first insulating layer 55 is left only in the first trench 52. This processing is performed, for example, by using CF ₄ /
Dry etching is performed using a mixed gas of O ₂ = 95/5. In step G, the main surface of the substrate 51 is again wet-etched to form a second trench 56 orthogonal to the first trench 52. At this time, at the intersection of the first trench 52 and the second trench 56, the end face 57 of the gate wiring layer 54 is exposed on the inner wall of the second trench 56. Subsequently, in step H, the substrate 51
A second insulating layer 58 made of PSG is formed on the entire surface of the
It is deposited by the D method. By this process, the end face of the gate wiring layer 54 exposed on the inner wall of the second trench 56 is completely covered with the second insulating layer 58, and electrical insulation is achieved. In step I, a metal aluminum film 59 is deposited on the entire main surface of the substrate 51 by a sputtering method. The film thickness is set to, for example, 600 nm, and the inside of the second trench 56 can be completely buried.

In step J of FIG. 7, the metal aluminum film is entirely removed from the surface of the substrate 51 by dry etching or wet etching to achieve flattening. As a result, the signal wiring layer 60 is formed of the metal aluminum embedded in the second trench 56. As is clear from the figure, the signal wiring layer 60 is electrically insulated from the gate wiring layer 54 via the second insulating layer 58. Process K
Then, a third insulating layer 61 made of PSG is deposited over the entire main surface of the substrate 51 by LPCVD. The film thickness is set to, for example, 600 nm. Finally, in step L, a P-SiN film 62 is deposited on the third insulating layer 61 to form a protective film or a passivation film. The film thickness is, for example, 500 nm.

[0021]

As described above, according to the present invention, in an active matrix type liquid crystal display device or the like in which gate lines and signal lines are arranged orthogonal to each other, a multi-layer wiring is formed using a so-called trench wiring technique. I do. The gate wiring layer and the signal wiring layer are embedded in the trench,
There is no superficial step at the intersection of the two. Because of this,
There is an effect that the substrate surface can be flattened and the orientation of the liquid crystal layer is improved. In addition, since there is no step due to the interlayer insulating film at the intersection of the gate wiring and the signal wiring, there is an effect that the wiring disconnection failure can be effectively prevented.
Further, since an increase in resistance caused by the step cover at the stepped portion can be prevented, there is an effect that the wiring resistance can be suppressed to be lower than in the related art even in the case of miniaturization.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a basic configuration of a display device according to the present invention.

FIG. 2 is a schematic cross-sectional view showing a crossing structure of a trench wiring.

FIG. 3 is a schematic cross-sectional view showing another example of the trench wiring according to the present invention.

FIG. 4 is a graph showing a relationship between a trench depth and a wiring resistance.

FIG. 5 is a process chart showing a step of forming a trench wiring.

FIG. 6 is a process drawing showing a step of forming a trench wiring.

FIG. 7 is a process view showing a step of forming a trench wiring.

FIG. 8 is a schematic diagram showing a conventional multilayer wiring structure.

FIG. 9 is a sectional view showing a conventional multilayer wiring structure.

[Explanation of symbols]

 Reference Signs List 1 TFT substrate 2 Counter substrate 3 Liquid crystal layer 6 Pixel electrode 7 TFT 8 Gate line 9 Signal line 10 Common electrode 12 First trench 13 Semiconductor layer 14 First insulating layer 15 Second trench 16 Second insulating layer 17 Metal layer 18 Third insulating layer

Claims (4)

(57) [Claims] 1. A plurality of gate lines formed on an insulating substrate, a signal line intersecting the gate line, and a thin film transistor and a pixel electrode arranged near an intersection of the gate line and the signal line. TFT
In a display device having a substrate, the gate line includes a gate wiring layer formed in a groove provided in the insulating substrate, and the signal line is formed in another groove provided in the insulating substrate. Ri Do from the wiring layer, the gate wiring layer is formed along the inner wall of the groove
The signal wiring layer is formed of a polycrystalline semiconductor layer,
A display device comprising a metal layer embedded in a part . 2. The display device according to claim 1, wherein the gate wiring layer and the signal wiring layer are insulated from each other at an intersection of the groove and another groove via an intermediate insulating layer. Wherein the metal layer is, the display device according to claim 1, characterized in that comprising an aluminum or aluminum metal composed mainly. 4. The display device according to claim 1, wherein at least a part of the signal line is stacked in parallel with the gate wiring layer via an insulating layer along a groove of the gate line.