JP3228927B2 - Processor element, processing unit, processor, and arithmetic processing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a digital signal processor (hereinafter referred to as a digital signal processor (hereinafter, referred to as a digital signal processor) which carries out arithmetic processing of digitized sequential data such as audio data and image data according to a program and outputs the arithmetic result. , DSP, etc.), a processor element (hereinafter, referred to as PE) as an arithmetic processing element constituting the processor, a processing unit (hereinafter, referred to as PU) configured using a plurality of the PEs, and a plurality of the PUs. The present invention relates to a processor capable of parallel processing for performing parallel processing by providing a plurality of processors and an arithmetic processing method thereof.

(Prior Art) Conventionally, as a technique in such a field, there is a technique described in the following literature.

Reference 1: Proceedings of the 1990 IEICE Spring National Convention,
SA-4-2, Sakiyama et al., "200 MIPS Image Processing Multiprocessor", P.1-415 to 1-416 Reference 2; Proceedings of the 1990 IEICE Spring Conference,
SA-4-4, Ota et al., "Design of Vector Processor for Parallel Signal Processing System", P.1-419 ~ 1-420 Reference 3-1; IEICE Transactions on Integrated Circuits ICD90-15 (199
0) Yamaguchi et al., “High-Speed Video Processor KZ5000”, P.59-66 Reference 3-2; NIKKEI ELECTRONICS [482] (1989-9-
18) “Communication workstation for videophone processing of image compression by software” P.100-101 Reference 3-3; NIKKEI ELECTRONICS [481] (1989-9-)
4) "Development of 320MIPS DSP used for motion assurance processing of videophone" P.75 Reference 4; IEICE Integrated Circuits Research Society ICD89-6 (1989) Kano et al. "16b, 25ns, video / image signal processor" P .
37-44 Conventionally, as described in Reference 4, the processor for signal processing in which the product-sum operation is dominant mainly includes:
For processing of one-dimensional signals such as voice, high speed has been measured by pipeline processing with a single PE configuration provided with a dedicated multiplier in addition to the arithmetic and logic unit. Further, as described in the above-mentioned documents 1, 2, 3-1 to 3-3, in recent years, processing of a signal having a two-dimensional or three-dimensional spread such as an image or higher-speed arithmetic processing has been performed. For the purpose of targeting, speeding up has been attempted by a parallel processing configuration provided with a plurality of PEs. An example of such a configuration is shown in FIGS. 2 (a), (b) and (c).

2 (a) to 2 (c) are explanatory diagrams of the prior art described in the above-mentioned references 3-1 and 3-2, and FIG. 2 (a) is a diagram illustrating the conventional art described in the above-mentioned reference 3-1. FIG. 2B is a block diagram showing the configuration of the PE in FIG. 2A, and FIG. 2C is a conventional three-stage pipeline described in Document 3-2. FIG. 7 is a processing configuration diagram for performing four parallel processings.

The image signal processor shown in FIG. 2 (a) is an array processing processor capable of executing high-speed signal processing in parallel.
A unit (hereinafter referred to as APU) 10, a central processing unit (hereinafter referred to as CPU) 20 for executing a program, a cache memory 22 controlled by a memory controller 21, an address / generation unit 23, an input / output port 24, and a bus A0, A1, D0, D1,
It is composed of DA, DD, PA, PD, etc.

The APU 10 has an input formatter 11 and PEs 12-0 to 12-3, 12-10 to 12-13, 12-20 to 12-23, 12 each having 4 rows × 4 columns.
-30 to 12-33, the parallel adders 13-0 to 13-3, the output formatter 14, the control formatter 15 for PE control, and the data of the parallel adders 13-0 to 13-3 are temporarily stored. Accumulator (hereinafter referred to as ACC) 16
And it is comprised.

As shown in FIG. 2 (b), the internal configuration of each of the PEs 12-0 to 12-33 includes selectors 31, 32, a multiplying circuit 33, and an adding circuit 3
4 and an input / output multiplexer 35.
In FIG. 2B, A and B are buses, A _si , D _si , B _si , and D _si are input data, and A _so , B _so , and D _so are output data.

In the image signal processing processor configured as described above, the image signal processing is executed by the 4 rows × 4 columns of PEs 12-0 to 12-33 constituting the APU 10. 4 rows x 4 columns PE12−
For 0 to 12-33, two connection modes, parallel and pipeline, can be realized. The parallel connection is used to execute a butterfly operation for two-dimensional discrete cosine transform (hereinafter referred to as DCT) or the like with two PEs as one set. On the other hand, in the pipeline connection, PE12-0 to 12-33
Takes a pipeline configuration in the row direction, and performs advanced processing that cannot be executed within one clock by a single PE alone.
Run on clock.

The input formatter 11 and the output formatter 14 having a function as an interface execute signal conversion between the PEs 12-0 to 12-33 and the cache memory 22, and the parallel adders 13-0 to 13-3 add via the ACC 16. Bus results P
Can be output on D. As a result, various kinds of signal processing such as a two-dimensional adaptive filter of an arbitrary block size having complicated conditions, a block matching method for motion compensation, and a gradient method can be executed at high speed.

For example, when processing image compression of a videophone, the second
The motion compensation of the videophone can be performed with one chip of the image processing processor shown in FIG. That is, as shown in FIG. 2 (c-1), the blocks used for videophone motion compensation
In the matching method, a three-stage pipeline is configured by combining operations as shown in FIG. 2 (c-2), and four of these pipelines are operated in parallel.

In the case of the international standard system, the motion is corrected for each block of 16 × 16 pixels. The absolute value of the difference between the pixel value A of the current frame and the value B of the previous frame is calculated for each pixel, and the sum is calculated for 16 × 16 pixels. Thus, the difference between the blocks is obtained.
One pipeline is assigned to this operation. The comparison unit 25 compares the blocks while shifting the blocks within a range of ± 7 pixels in the vertical, horizontal, and vertical directions, and calculates and corrects the motion vector. If you shift the position of the block, use a different pipeline.

(Problems to be Solved by the Invention) However, the PE having the above configuration, a processor using the same, and an arithmetic processing method thereof have the following problems.

In the conventional PE, as shown in FIGS. 2 (a) and (b),
16 PEs 12-0 to 12-3,..., 12-30 to 12-33 each having a dedicated multiplication circuit 33 and an addition circuit 34 are mounted. In the product-sum operation processing, 16 parallel processing can be performed. . However, for example, as shown in FIG. 2 (c), the accumulation processing of the absolute difference value used when detecting a motion vector is performed by a pipeline configuration combining four PEs. Since the processing is performed in parallel, the parallelism is impaired, and the dedicated multiplication circuit 33 is not used. Therefore, an unused arithmetic unit is generated, so that hardware is wasted and the circuit scale is increased. And it was difficult to solve them.

The present invention has a problem that the conventional technology has problems in that parallel processing is impaired in accumulating the difference absolute value and high-speed processing is difficult, and an unused arithmetic unit is generated and wasted. It is an object of the present invention to provide a PE, a PU, a processor, and an arithmetic processing method thereof that solve the problem of increasing the scale.

(Means for Solving the Problems) In order to solve the above problems, a first aspect of the present invention is a PE that outputs a cumulative value of a difference absolute value between first input data and second input data which are digital data. In the first, the positive or negative addition result is stored based on the fourth control signal.
Storage means, a second storage means for storing the cumulative addition result based on the fifth control signal, and the first input data and the first storage means which are stored in the first storage means based on the first control signal. A first selector for selectively inputting the positive or negative addition result and a second control signal based on a second control signal.
A second selector for selectively inputting the input data of the second and the cumulative addition result stored in the second storage means, and the second selector input from the first selector based on a third control signal. Bit inversion means for inverting and outputting the input data of 1 and the negative addition result, respectively, and outputting the positive addition result as it is, and inputting the third control signal as a carry signal, Means for adding the output of the second selector to the output of the second selector, outputting the positive or negative addition result and storing the result in the first storage means, and outputting the cumulative addition result in the second storage section. Adding means for storing in the storage means.

When the negative addition result is bit-inverted by the bit inversion means, the adding means adds logic "1" to the sum of the output and the content of the second storage means, and the positive addition result is When output from the bit inversion means as it is,
The sum of the output and the content of the second storage means is stored in the second storage means as the cumulative value of the absolute difference value.

According to a second aspect of the present invention, in the PE of the first aspect, a shifter for shifting the first input data by a predetermined bit based on a control signal is provided on an input side of the first selector, and an output of the shifter is provided to the second selector. One selector is input.

The third invention is the PE according to the first or second invention,
The first and second selectors are configured to switch the selector output based on the first and second control signals at a timing that is 1/2 of an input timing of input data to the selector.

A fourth invention provides a PU comprising (n + 1) PEs according to the first, second or third invention, wherein the PU comprises the first PE to the n-th PE.
Each input side of the PE is connected to an input bus group, each output side is connected to an output bus group, and the input and output sides of the (n + 1) th PE are connected to the output bus group. Then, according to the Booth (Booth) algorithm, each power term of 2 is calculated by each of the first to n-th PEs, and the (n + 1) -th PE is calculated.
, Multiplication or multiplication accumulation processing is performed by shift addition, and n parallel arithmetic logic accumulation processing is performed.

A fifth invention is a processor capable of processing parallel signals, comprising m PUs according to the fourth invention, wherein each input side of the first PU to the m-th PU is connected to an input data bus group, and each output side is provided. Are connected to an output data bus group, respectively, and are configured to perform addition / subtraction, multiplication, logical operation, and accumulation processing of an m × m matrix.

According to a sixth aspect of the present invention, in the arithmetic processing method using the PE, a shifter for shifting the first input data by a predetermined bit, a first selector for selectively outputting the output of the shifter or the output of the first register, And a second selector for selecting and outputting the input data of the second register or the output of the second register for data output, and inputting the outputs of the first and second selectors to perform an arithmetic processing, and calculating the arithmetic result by the first processor. And the arithmetic means for outputting to the second register, the following processing is performed.

That is, in the first operation processing mode set by the mode signal, in the first stage, the first selector selects and outputs the shifter output, and the second selector selects the second input data. Outputting the first and second
Is operated by the operation means, and the operation result is stored in the first register. In a second stage, the first and second selectors respectively
And the second register output is selectively output, the output is accumulated by the arithmetic means, the processing result is stored in the second register, and the first and second stages are repeated one or more times. Execute. Further, in the second arithmetic processing mode set by the mode signal,
Is fixed to selectively output the shifter output, the second selector is fixed to select and output the second register output, and the arithmetic means accumulates the shifter output. The stage stored in the second register is repeatedly executed one or more times.

At this time, the first operation mode in the first operation processing mode
The first and second stages from the second stage to the second stage
Of the selectors is performed at half the input timing of the first and second input data.

(Operation) According to the first and second aspects, one of the first input data and the addition result stored in the first storage means is transmitted to the bit inversion means via the first selector. The bit is inverted by the bit inversion means and sent to the addition means. One of the second input data and the cumulative addition result stored in the second storage means is selected by the second selector and sent to the addition means. The addition means performs an addition process on the output of the bit inversion means and the output of the second selector, and outputs the addition result to the first and second storage means. As a result, the same bit inversion means and the same addition means are repeatedly used to perform the accumulation operation processing, whereby the independence (parallel processing performance) and simplification of PE can be achieved.

According to the third aspect, based on the first and second control signals, the output of the first and second selectors is switched at a half of the input timing of the input data. The processing of the cumulative calculation can be performed at the timing of 2, thereby increasing the processing speed.

According to the fourth and fifth aspects of the present invention, when performing multiplication, each
Since PE performs arithmetic processing according to the Booth algorithm,
The independence (parallel processing property) and simplification of each PE can be achieved, thereby achieving high parallelism and performing parallel processing without waste for the PE.

According to the sixth aspect, in the first and second arithmetic processing modes set by the mode signal, the same arithmetic means is repeatedly used, thereby simplifying arithmetic processing and increasing the processing speed. At that time, the first and second selectors are switched at half the input timing of the first and second input data, so that the arithmetic processing can be performed at half the timing of the input data. Higher speed of arithmetic processing can be achieved.

Embodiment (First Embodiment) FIG. 1 is a configuration block diagram of a PE showing a first embodiment of the present invention.

The PE 100 has a control circuit 110 for controlling the entire PE. The control circuit 110 controls the third input data X (= X ^{2k + 1} , X ^2k , X ^2k-1) provided via the bus, the mode signal md and the clock ck supplied from the outside, the carry output co And outputs a control signal s0 for controlling an internal circuit of the PE and first to fifth control signals s1 to s5 at predetermined timings, respectively. , ROM, etc. The control circuit 110 includes a shifter 120 and first and second input means,
1, second selectors 130 and 140, arithmetic means 150, and first and second
The first and second registers 160 and 170, which are storage means, are connected.

The shifter 120 inputs the first input data Y, and shifts by 0 bit, shifts by 1 bit to the left, and shifts by 0 by the control signal s0.
The output side is connected to one input side of the arithmetic means 150 via the selector 130.
The selector 130 is connected to the output of the shifter 120 and the first register 160
And a function of selecting one of them by the control signal s1 and providing the selected signal to one input side of the arithmetic means 150. The second selector 140 receives the second input data M and the output of the second register 170, selects one of them according to the control signal s2, and outputs it to the other input side of the arithmetic means 150. Has a function.

The operation means 150 includes a bit inversion circuit 151 connected to the output side of the selector 130, the bit inversion circuit 151 and the selector
And an adder 152 connected to the output side of 140. The bit inversion circuit 151 is a circuit that receives the output of the first selector 130, inverts all the input bits by the control signal s3, and provides the inversion result to the adder 152. The adder 152 is connected to the output of the bit inversion circuit 151 and the second selector.
140, and a control signal s3 representing the positive or negative of the Booth encode value is input as a carry input ci, an addition process is performed on the output of the bit inversion circuit 151 and the output of the second selector 140, and the addition result is calculated. First and second registers
It has a function of giving the carry output co to the control circuit 110 as well as giving it to 160 and 170.

The first register 160 controls the adder 1 based on the control signal s4.
52 output is temporarily stored, and the stored content is stored in the first selector.
It is a circuit that outputs to 130. The second register 170 has a function of temporarily storing the output of the adder 152 based on the control signal s5, supplying the stored content to the second selector 140, and outputting the content as output data O to the bus.

FIG. 3 is a timing chart of the difference absolute value accumulating process using the PE 100 of FIG. 1. Referring to FIG.
The 100 calculation processing methods will be described.

The cumulative operation of the absolute difference value for the first and second input data Y, M is Is represented by Assuming that i = 1 to 3 for simplicity of description, the equation (1) becomes the following equation (2).

O _i = | M ₁ −Y ₁ | + | M ₂ −Y ₂ | + | M ₃ −Y ₃ | (2) FIG. 3 shows the operation of the equation (2).

The first input data Y _{1 to} Y ₃ are transmitted through the shifter 120 to the first input data Y _{1 to} Y ₃ .
, And the second input data M _{1 to} M ₃ are supplied to the second selector 140 by one of the machine cycles MC 1 to MC 7.
It is sequentially input every other time. In the first machine cycle MC1, input data Y ₁ and M ₁ are controlled by control signals s ₁ and s ₂ .
1, selected by the second selectors 130 and 140, and the bit inversion circuit 1
M ₁ −Y ₁ is executed by 51 and the adder 152. The execution of the subtraction M ₁ −Y _{1 in} the bit inversion circuit 151 and the adder 152 is performed by performing the bit inversion in the bit inversion circuit 151 by the control signal s3 and the carry input ci to the adder 152, that is, M ₁ + Y ₁ +1. Will be

In the second machine cycle MC2, the subtraction result of M ₁ −Y ₁ is input to the first register 160. At the same time, the first and second register outputs are selected in the first and second selectors 130 and 140, respectively, and the bit inverting circuit 151 and the adder 152 execute the cumulative addition of absolute values. The absolute value cumulative addition is performed by monitoring the carry output co of the adder 152 in the control circuit 110 and, when the subtraction result M ₁ −Y ₁ is negative, performing the subtraction by the above-described method.

In the third machine cycle MC3, accumulated result of the is input to the second register 170, a first similarly subtracting the machine cycle MC1 M ₂ -Y ₂ is executed. As described above, by repeating the above processing operation, the output data O obtained as the result of Expression (2) in the seventh machine cycle MC7 is obtained.
_i is obtained. In the first embodiment, the independence (parallel processing) of the PE 100 is improved by repeatedly using the same calculation means 150 during the cumulative calculation processing, whereby the calculation processing can be sped up. The configuration of the PE 100 is simplified, and thus the circuit size can be reduced.

As described above, in the first embodiment, the difference absolute value accumulating process has been described. However, the operation of the bit inverting circuit 151 is fixed so as not to be inverted by the control signal s3 using the same circuit configuration as that of FIG. And the first and second input data
Difference accumulation processing for Y and M can also be executed.

Also, in the PE 100, the arithmetic means 150 is replaced with, for example, an arithmetic logic unit (hereinafter, referred to as ALU),
The same arithmetic processing as described above is possible.

Second Embodiment FIG. 4 shows a second embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a PU capable of performing multiplication processing by using a plurality of PEs 100 in the figure, and FIG. 5 is a block diagram showing a configuration of a final stage accumulator used in the PU.

First, before describing the configurations of FIGS. 4 and 5, execution of multiplication will be described.

One of the techniques for configuring the multiplier is a technique using the Booth algorithm. First, this method will be described.

An arbitrary value X is represented by an n-bit two's complement expression as follows.

Where X ⁱ (i = 0 to n−1); 1 or 0 with a 1-bit numerical value. Becomes Therefore, an arbitrary multiplication XY is as follows.

Expressions (4) and (5) in parentheses are second-order Booth encoding expressions Z = −2X ^{2k + 1} + X ^2k + X ^2k−1 (6), and are either 0, ± 1, ± 2. Takes the encoded value of.

For example, if X is a 16-bit multiplier, the multiplication XY is expressed by the following equation (7).

^{XY = (- X 15 2 1} + X 14 2 0 + X 13 2 0) Y2 14 + (- X 13 2 1 + X 12 2 0 + X 11 2 0) Y2 12 + (- X 11 2 1 + X 10 2 0 + X 9 2 ⁰ ) Y2 ¹⁰ + (− X ⁹ 2 ¹ + X ⁸ 2 ⁰ + X ⁸ 2 ⁰ ) Y 2 ⁸ + (− X ⁷ 2 ¹ + X ⁶ 2 ⁰ + X ⁵ 2 ⁰ ) Y 2 ⁶ + (− X ⁵ 2 ¹ + X ⁴⁾ 2 ⁰ + X ³ 2 ⁰ ) Y 2 ⁴ + (− X ³ 2 ¹ + X ² 2 ⁰ + X ¹ 2 ⁰ ) Y ^{2 2} + (− X ¹ 2 ¹ + X ⁰ 2 ⁰ ) Y 2 ⁰ …… (7) The accumulation process ΣXY can also be expressed by the following equation (8).

^{ΣXY = Σ (-X 15 2 1} + X 14 2 0 + X 13 2 0) Y2 14 + Σ (-X 13 2 1 + X 12 2 0 + X 11 2 0) Y2 12 + Σ (-X 11 2 1 + X 10 2 0 + X ⁹ 2 ⁰ ) Y2 ¹⁰ + Σ (−X ⁹ 2 ¹ + X ⁸ 2 ⁰ + X ⁷ 2 ⁰ ) Y2 ⁸ + Σ (−X ⁷ 2 ¹ + X ⁶ 2 ⁰ + X ⁵ 2 ⁰ ) Y2 ⁶ + Σ (−X ⁵ 2 ¹ + X ⁴ 2 ⁰ + X ³ 2 ⁰ ) Y2 ⁴ + Σ (−X ³ 2 ¹ + X ² 2 ⁰ + X ¹ 2 ⁰ ) Y ^{2 2} + Σ (−X ¹ 2 ¹ + X ⁰ 2 ⁰ ) Y 2 ⁰ …… (8) (8) The equation is as follows, when Φ _k = Σ (−X ^{2k + 1} 2 ¹ + X ^2k 2 ⁰ + X ^2k-1 2 ⁰ ) Y (9)

ΣXY = Φ ₀ 2 ⁰ + Φ ₁ 2 ² + Φ ₂ 2 ⁴ + Φ ₃ 2 ⁶ + Φ ₄ 2 ⁸ + Φ ₅ 2 ¹⁰ + Φ ₆ 2 ¹² + Φ ₇ 2 ¹⁴ …… (10) Therefore, ΣXY is a subtraction to calculate Φ _k And an arithmetic unit that shift-adds Φ _k .

The configuration of the PU in FIG. 4 for performing the above multiplication processing will be described.

The PU 500 includes eight PEs 100-0 to 100-7 in FIG. 1 for calculating Φ _k (k = 0 to 7) in the equation (10), and Φ _k
(K = 0 to 7) and a final-stage accumulator 200 that outputs a multiplication result or a multiplication accumulation result. Input bus group on the input side of PE100-0 to 100-7
An output bus group 400 is connected to the output side of the PEs 100-0 to 100-7 and the input and output sides of the final-stage accumulator 200.

The input bus group 300 receives data X, Y, and M from the outside and outputs the data to each of the PEs 100-0 to 100-7.
In particular, the data input from the input bus group 300, that is, the multiplication X is X ⁰ according to the second-order Booth algorithm.
To to X ¹⁵ are bit-sliced, each PE100-0~100-
7 is input. Output bus group 400 is PE100-0 to 100-
The output of 7 is input to the final-stage accumulator 200 or output to the outside, and the output of the final-stage accumulator 200 is output to the outside. The output bus group 400 outputs output data N such as a multiplication result or a multiplication accumulation result.

As shown in FIG. 5, the final-stage accumulator 200 receives a mode signal md and a clock ck from the outside and receives control signals s10 and s11.
Is output to the control circuit 210. Further, a shifter 220 that receives data from the output bus group 400 and shifts a predetermined bit based on the control signal s10 is provided, and an adder 230 and a register 240 are connected to the output side thereof. Adder
230 is a circuit for adding the output of the shifter 220 and the output of the register 240. The register 240 has a function of temporarily storing the output of the adder 230, inputting the stored content to the adder 230, and outputting the content to the output bus group 400.

An arithmetic processing method in the case of performing the multiplication processing using the PU 500 as described above will be described with reference to FIGS.

FIG. 6 is a timing chart at the time of the multiplication processing of PEs 100-0 to 100-7 in FIG. 4 constituted by the circuit of FIG. FIG. 7 shows the final-stage accumulator 20 in FIG.
FIG. 9 is a diagram illustrating a shift addition bit configuration of 0, that is, a bit configuration of a shift addition process of Expression (10). FIG.
6 is a timing chart of a shift addition process in the last-stage accumulator 200 of FIG.

For example, the multiplication accumulation process ΣXY Then, Φ _k becomes as follows.

Φ _k = (− X ₁ ^{2k + 1} 2 ¹ + X ₁ ^2k 2 ⁰ + X ₁ ^2k-1 2 ⁰ ) Y ₁ + (− X ₂ ^{2k + 1} 2 ¹ + X ₂ ^2k 2 ⁰ + X ₂ ^2k-1 2 ⁰ ) ^{_{Y 2 + (- X 3 2k}} + 1 2 1 + X 3 2k 2 0 + X 3 2k-1 2 0) Y 3 + (- X 4 2k + 1 2 1 + X 4 2k 2 0 + X 4 2k-1 2 0) Y ₄ ... (12) FIG. 6 is a diagram showing PE100-0 to 100 configured by the circuit of FIG.
9 is an operation timing chart of Φ _k calculation at −7. As shown in this figure, the first input data Y _{1 to} Y ₄
Shifter 120 in PE100-0 to 100-7, third input data X
₁ to X ₄ in the control circuit 110 in each PE100-0～100-7, are respectively sequentially input for each machine cycle MC1~MC5 .......
Each PE100-0~100-7 control circuit 110 in, in accordance with the first input data X ₁ ~X _4, (6) equation was calculated encoded value Z, the control signal s0 and a bit inversion circuit to the shifter 120 The control signal s3 to the adder 151 and the adder 152 is output.

Each of the PEs 100-0 to 100-7 enters a multiplication execution mode in response to the input of a mode signal md from the outside, and the first selector 130 fixedly outputs the control signal s1 so that the output of the shifter 120 is always selected and output. , The second selector 140 controls the control signal s2 so that the output of the second register 170 is always selected and output.
Is fixedly output.

The control circuit 110 in each of the PEs 100-0 to 100-7 as described above.
The PE100-0 to 100-7 add the output of the shifter 120 and the output of the second register 170 by the adder 152 for each machine cycle MC1 to MC5, and calculate the addition result. Φ _k is calculated by repeating the operation of outputting to the second register 170. FIG. 7 shows an example of execution of equation (12), in which Φ _k is calculated at the fifth machine cycle MC5.

Φ _k calculated in each of the PEs 100-0 to 100-7 as described above is input to the final-stage accumulator 200 via the output bus group 400 shown in FIG. Is executed. FIG. 7 shows the bit configuration of this shift addition processing. Further, FIG. 8 shows the operation timing of the shift addition process in the final-stage accumulator 200 in FIG.

In the final-stage accumulator 200 shown in FIG.
MC9 per ...., type [Phi _k to the shifter 220 adds the output of the output and the register 240 by the adder 230, by repeating the operation for outputting the addition result to the register 240 ShigumaXY
Is calculated. An execution example of the equation (10) is shown in FIG. As shown in this figure, ΔXY is calculated at the ninth machine cycle MC9, and the calculation result is output to the output bus group 400.

In the second embodiment, since the difference accumulation processing is executed by switching the mode signal md in FIG. 4, eight parallel processings can be performed. As described above, the multiplication process is performed using the second-order Booth algorithm, so that each PE100
Independence (parallel processing performance) of −0 to 100-7 and simplification can be realized, whereby the speed of the arithmetic processing in the PU 500 and the circuit scale can be reduced.

In the second embodiment, for example, the following modifications are possible.

(A) The final stage accumulator 200 in FIG. 4 may employ the PE configuration in FIG. 1 as it is, instead of the configuration shown in FIG. At this time, the first selector 130, the bit inversion circuit 151, and the first register 160 may be fixed in the through state by the control signals s1, s3, and s4 output from the control circuit 110 in FIG. By connecting nine PEs in parallel in this way, a PU that can also execute multiplication processing can be easily configured.

(B) Although the multiplication accumulation processing using the PU 500 in FIG. 4 has been described, a single multiplication processing as shown in the equation (7) can also be executed.

(C) In this embodiment, the case where the multiplier X, which is input data, is 16 bits has been described. However, even when the number of bits is arbitrary n bits, it can be easily handled by changing the number of PEs.

(D) When the multiplier X as input data is, for example, a fixed coefficient, a part of the control circuit 110 in the PE in FIG. 1 is replaced with a storage circuit such as a ROM, and the expanded data of X is stored in the storage circuit in advance. By storing, it is possible to simplify the arithmetic processing and thereby speed up the arithmetic processing.

Third Embodiment FIG. 9 shows a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a processor capable of performing parallel processing configured using four PUs in FIG.

This processor has four PU500-0s having the configuration shown in FIG.
4 × 4 matrix operation is performed by using the data X,
An input bus group 600 for inputting Y is connected, and an output bus group 700 for outputting output data Q is connected to the output side. Therefore, in this processor, 8 × 4 = 32
This means that PEs are connected.

FIG. 10 is an explanatory diagram when the 4 × 4 matrix operation of FIG. 9 is executed.

As shown in this figure, in the processor of FIG. 9, when input data X and Y are input to the input bus group 600, the matrix X
The multiplication of Y is performed according to the following equation (13).

That is, when performing the multiplication processing of the matrices X and Y of the equation (13), the first
0, as shown in FIG.
By allocating 3 and inputting, the 4 × 4 matrix operation processing is completed in four steps of the first to fourth steps, and the output data Q, which is the processing result, is output to the output bus group 70.
Output from 0.

In addition, in arithmetic logic operations such as addition and subtraction using this processor, since processing is performed in PE units, processing can be performed in parallel using 32 or 16 PEs.

In the third embodiment, since a processor capable of parallel processing is configured using the PUs 500-0 to 500-3 of FIG. 4 configured by connecting a plurality of PEs in parallel, a higher performance parallel processing is realized. Can be calculated.

Fourth Embodiment In the first to third embodiments, it has been described that the PU 500 of FIG. 4 and the processor capable of parallel processing of FIG. 9 can be constructed using the PE 100 of FIG. As shown in the figure, the operation timing in the arithmetic logic accumulation operation that performs PE independent processing such as the difference absolute value accumulation processing is input every other machine cycle, which is not efficient. Therefore, FIG. 11 shows a principle diagram of a configuration of a PE that can solve the problem of inefficiency in the calculation logic accumulation operation and that can perform processing continuously and that can be operated at high speed.

FIG. 11 shows a fourth embodiment of the present invention and is a block diagram of a PE capable of high-speed operation.

This PE inputs first and second input data A and B,
Selector 830 that selects and outputs input according to control signal cs
And an adder 852 for performing an addition process on the output of the selector 830 and the third input data C, and first and second outputs for inputting the output of the adder 852 based on the control signals cr1 and cr2 and outputting the output to the outside. And two registers 860 and 870.

FIG. 12 is a timing chart of FIG. 11, and the arithmetic processing method will be described with reference to FIG.

For example, as shown in FIG. 12, input data A _i + C _i , B _i +
Consider the case where the operation of C _i is executed. For the data A _i , B _i , and C _i sequentially input for each machine cycle MC, the selector 830 is switched by a control signal cs at a double rhythm, that is, at a timing of つ の, so that two By inputting the data to the adder 852, two additions are performed. Then, control signals cr1, cr2 having the same cycle as the control signal cs.
, The result of A _i + C _i is sequentially input to the first register 860 and the result of B _i + C _i is input to the second register 870 with a time width of one machine cycle MC.

In this way, the selector 830 connected to the input stage of the adder 852 in the PE shown in FIG. 11 is switched to the selector 830 at a rhythm twice the data input rhythm, that is, at a timing half the data input timing. By switching the adder 8
The operation speed of 52 can be improved, and thereby the calculation processing can be speeded up.

(Fifth Embodiment) FIG. 13 shows a fifth embodiment in which the speed-up technique in the fourth embodiment is incorporated into, for example, the operation of the PE configuration shown in FIG.

FIG. 13 is a timing chart in a case where the absolute difference value accumulation processing is performed using the PE of FIG.

In the speeding-up method of FIG. 13, unlike the timing chart of FIG. 3 showing the first embodiment, both the first and second selectors 130 and 140 of FIG. 1 are controlled by using the control signals s1 and s2. By switching at a rhythm that is twice as long as the input data timing, that is, at a timing that is 1/2, the difference processing and the accumulation processing are executed within the same machine cycle time.

When the timing chart of FIG. 13 is compared with FIG. 3, the output data O _i resulting from the equation (2) is processed for six machine cycles in FIG.
On the other hand, in FIG. 13, the processing is performed for three machine cycles, and the processing is performed at the fourth machine cycle MC4, and the arithmetic processing speed is doubled. Moreover,
Data can be sequentially input for each machine cycle, and the data input speed is doubled.

(Effects of the Invention) As described in detail above, according to the first and second inventions, the arithmetic processing is performed using the arithmetic means including the bit inverting means and the adding means. The configuration is simplified, and the circuit size can be reduced. In particular, by repeatedly using the same arithmetic means during the cumulative arithmetic processing, the PE is simplified and the parallel processing performance is further improved, so that the circuit scale can be further reduced.

According to the third aspect, since the selector output is switched at half the input timing of the input data group, the arithmetic processing on the input data can be efficiently performed at high speed.

According to the fourth and fifth aspects of the present invention, the arithmetic processing is performed by using the Booth algorithm technique.
Alternatively, the independence (parallel processing) and simplification of the PEs that compose the processor can be improved, so that more PEs can be implemented and a highly functional PU or processor with high parallelism and no waste is realized. it can.

According to the sixth aspect, by repeatedly using the same calculation method, it is possible to execute high-speed and efficient calculation processing without waste. Moreover, 1/2 of the input data timing
The switching of the selector is performed at the timing described above, so that the arithmetic processing can be further speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of the structure of a PE showing a first embodiment of the present invention, and FIGS. 2 (a), 2 (b) and 2 (c) are explanatory views of the prior art, and FIG. FIG. 3B is a block diagram of the PE in FIG. 3A, FIG. 3C is a processing block diagram, and FIG. 3 is an absolute difference between the PEs in FIG. FIG. 4 is a block diagram of a PU showing a second embodiment of the present invention, FIG. 5 is a block diagram of a final stage accumulator in FIG. 4,
FIG. 6 is a timing chart of the PE multiplication accumulation processing of FIG. 4, FIG. 7 is a diagram showing the shift addition bit configuration of the last stage accumulator in FIG. 4, and FIG. 8 is the last stage accumulation in FIG. FIG. 9 is a timing chart of the shift addition processing of the processor, FIG. 9 is a block diagram showing the configuration of a processor showing a third embodiment of the present invention, and FIG.
FIG. 11 is a diagram for explaining the execution of a 4 × 4 matrix operation, FIG. 11 is a block diagram of a PE showing a fourth embodiment of the present invention, and FIG.
FIG. 11 is a timing chart of the difference absolute value accumulating process according to the fifth embodiment of the present invention. 100,100-0 ~ 100-7 ... PE, 110,210 ... Control circuit,
120,220 …… Shifter, 130,140,830 …… Selector, 150…
... Calculation means, 151 ... Bit inversion circuit, 152,230,852 ...
Adder, 160, 170, 240, 860, 870 …… Register, 300,600…
… Input bus group, 400,700 …… Output bus group, 500,500-0
500-3: PU, 200: Final stage accumulator.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Masato Yamazaki 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-2-170227 (JP, A) JP-A JP-A-2-127727 (JP, A) JP-A-1-126819 (JP, A) JP-A-63-207234 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 7 / 50

Claims (6)

(57) [Claims] 1. A processor element for outputting a cumulative value of an absolute value of a difference between first input data and second input data as digital data, wherein a positive or negative addition result is obtained based on a fourth control signal. A first storage means for storing, and a second storage means for storing a cumulative addition result based on a fifth control signal.
A first selector for selectively inputting the first input data and the positive or negative addition result stored in the first storage means based on a first control signal; A second selector for selectively inputting the second input data and the cumulative addition result stored in the second storage unit based on a second control signal; and Bit inverting means for bit-inverting and outputting the first input data and the negative addition result input from the first selector, respectively, and outputting the positive addition result as it is, the third control A signal is input as a carry signal, the output of the bit inversion means is added to the output of the second selector, and the positive or negative addition result is output and stored in the first storage means. Output cumulative addition result Adding means for storing the negative addition result in the second storage means when the negative addition result is bit-inverted by the bit inversion means. A logic "1" is added to the sum of the contents, and when the positive addition result is output from the bit inversion means as it is, the sum of the output and the contents of the second storage means is calculated by accumulating the absolute difference value. A processor element, wherein a value is stored in the second storage means as a value. 2. The processor element according to claim 1, wherein a shifter for shifting the first input data by a predetermined bit based on a control signal is provided on an input side of the first selector, and an output of the shifter is provided to the first selector. A processor element characterized in that input is made to one selector. 3. The processor element according to claim 1, wherein said first and second selectors are configured to generate 1/1 of an input timing of input data to said selector based on said first and second control signals. A processor element configured to switch the selector output at the timing of 2. 4. An apparatus according to claim 1, further comprising (n + 1) processor elements (where n is a positive integer), wherein each of the input sides of the first processor element to the n-th processor element is provided. In the input bus group, each output side is connected to the output bus group, and the input and output sides of the (n + 1) th processor element are connected to the output bus group. 1
, Respectively, by the n-th processor element, and by performing a shift addition by the (n + 1) -th processor element to perform multiplication or multiplication accumulation processing,
And a processing unit for performing n arithmetic logic accumulation processes in parallel. 5. The processing unit according to claim 4, wherein m (where m is a positive integer) each input side of the m-th processing unit from the first processing unit to an input bus group, and each output unit A processor connected to each output bus group to perform addition / subtraction, multiplication, logical operation, and accumulation of the mxm matrix. 6. A shifter for shifting a first input data by a predetermined bit, a first selector for selectively outputting an output of the shifter or an output of a first register, and a second selector for second input data or data output. A second selector for selecting and outputting the output of the second register, and an operation means for inputting the first and second selector outputs, performing an operation process, and outputting the operation result to the first and second registers. In a first arithmetic processing mode set by a mode signal, in a first stage, the first selector selects and outputs the shifter output, and the second selector outputs the second input data. And outputs the first and second selector outputs by the operation means, and outputs the operation result to the first and second selectors.
In a second stage, first and second selectors select and output the first and second register outputs, respectively, and accumulate the outputs with the arithmetic means. The first and second stages are stored in the second register, and the first and second stages are repeatedly executed once or a plurality of times. In a second arithmetic processing mode set by the mode signal, the first selector is provided with the shifter. The output is fixed so as to be selectively output, the second selector is fixed so as to selectively output the second register output, the arithmetic means performs cumulative processing on the shifter output, and the processing result is stored in the second register. A processing method for repeatedly executing a stage to be stored once or a plurality of times, wherein the first stage and the second stage in the first processing mode are different from each other. The first, the switching of the second selector, said first arithmetic processing method, which comprises carrying out at half the timing of the input timing of the second input data to.