JP3223160B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an improvement of a microcomputer having a nonvolatile memory.

[0002]

2. Description of the Related Art Generally, a microcomputer has a built-in mask ROM for storing an operation control program and a RAM for storing data. On the other hand, as a memory, a nonvolatile memory (flash memory) capable of electrically erasing written data electrically at a time has been developed and has become well known. Recently, microcomputers having a built-in nonvolatile memory instead of the mask ROM and RAM have appeared. A microcomputer having a built-in nonvolatile memory has an advantage that a program for operation control can be easily rewritten because data that has been electrically written in the nonvolatile memory can be erased.

[0003]

As shown in FIG. 2, a microcomputer having a built-in nonvolatile memory is provided with a mask ROM 1 for storing only a program for rewriting a program written in the nonvolatile memory. The address numbers of the program rewriting mask ROM 1 and the non-volatile memory 2 are assigned consecutive address numbers. For example, if the mask ROM1 is 000
Assuming that addresses from 0H to 0100H are assigned, 0101H to FFFFH are assigned to the nonvolatile memory 2.

Here, since the programs written in the mask ROM 1 and the nonvolatile memory 2 are for operation control, it is desirable to control the addresses of the two memories by the same addressing signal. In addition, a microcomputer having a built-in nonvolatile memory directly uses the address control of a microcomputer having a built-in ROM or RAM. Therefore, the address number is R
Consecutive addresses are assigned over OM1 and RAM2. However, in this case, since the non-volatile memory 2 also has an unused area designated by the addresses 0000H to 0100H, the use efficiency of the non-volatile memory 2 is low.

[0005]

According to the present invention, there is provided a nonvolatile memory which can be electrically erased in a batch, and a ROM in which a program is stored, wherein an address of the ROM is overlapped with an address of the nonvolatile memory. The attached microcomputer is characterized by comprising a selector for selecting an address of the ROM during a normal operation and selecting an address of the non-volatile memory during a test.

A microcomputer controller for generating address signals for the ROM and the nonvolatile memory; wherein the selector converts the address signal to the ROM or the nonvolatile memory in response to a test signal applied from an external circuit; To be electrically connected. In particular, the selector includes two transmission gates that are turned on or off in response to the test signal.

According to the present invention, the normal operation ROM and the nonvolatile memory have the same address.
Is specified, and R is stored in the nonvolatile memory during the test.
Since the same address as that of the OM is specified, a specific area of the non-volatile memory which is not used in the normal operation is used in the test.

[0008]

FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 1 denotes a mask ROM in which a program for rewriting a program in a nonvolatile memory is written, and includes an address control unit 1a and a data output unit 1b. Reference numeral 2 denotes a nonvolatile memory in which a program for controlling the operation of the microcomputer itself is written, and includes an address control unit 2a, a data input unit 2b, and a data output unit 2c. Reference numeral 3 denotes a microcomputer control unit, which is a program counter PC that generates an address signal according to a count value, an instruction decoder IDEC that decodes program data into an instruction, a RAM address circuit ADR that generates an address signal in an external RAM, and temporarily stores data. It has a register RG for storing. Reference numeral 4 denotes a selector for selecting and outputting an address signal from the microcomputer control unit 3 to the mask ROM 1 and the non-volatile memory 2. Reference numeral 5 selects output data of the mask ROM 1 and the non-volatile memory 2 and outputting the data to the microcomputer control unit 3. Selector. Reference numerals 6 and 7 are transmission gates for conducting an address signal to the mask ROM 1 or the nonvolatile memory 2 in response to a test signal TEST from an external circuit. Reference numerals 8 and 9 denote transmission gates for conducting output data from the mask ROM 1 or the nonvolatile memory 2 in response to a test signal TEST from an external circuit. Reference numeral 10 denotes an external RAM.

Referring to FIG. 1, a data read operation during a test operation will be described. An H-level test signal TEST is applied to the transmission gate 6 via an external pin PIN.
To 9. Therefore, transmission gates 6 and 8 are turned off by the action of inverter 9, and transmission gates 7 and 9 are turned on. In this state, the address 0000H is set by the program counter PC.
It is assumed that an address signal ad for designating one address among 0-100H is output. In the microcomputer control unit 3,
It is determined that an address signal designating addresses 0000H to 0100H has been output, and a first state select signal SE is output. Therefore, the selector 4 outputs the address signal ad to the transmission gates 6 and 7, and the selector 5 selects the output data of the transmission gates 8 and 9 and outputs the data to the microcomputer control unit 5.

Since the transmission gates 7 and 9 are turned on, the address signal ad is supplied to the selector 4
Through the transmission gate 7 and input to the address control circuit 2a in the nonvolatile memory 2.
Addresses 0000H to 010 are generated by the address signal ad.
0H is designated, and the data in the designated address is read. The read data is output from the data output unit 2c, passes through the transmission gate 9, and is input to the microcomputer control unit 3 via the selector 5.

[0011] In the data writing at the time of the test, the address is specified in the above-described procedure. The data to be written is input to the data input section of the nonvolatile memory 2, and then the data is sequentially written to the specified address. Next, the normal operation will be described. During normal operation, an L-level test signal TEST is input, transmission gates 6 and 8 are turned on, and transmission gates 7 and 9 are turned off. In such a state, an operation according to a program written in the nonvolatile memory 2 will be described. The count value of the program counter PC of the microcomputer control unit 3 is incremented, and an address signal ad is generated according to the count value. Note that the address signal ad in this case has addresses 0101H to FFFFH.
Is specified. The microcomputer control unit 3 determines that an address signal designating the addresses 0101H to FFFFH has been output, and outputs a second state select signal SE. Therefore, the selector 4 outputs the address signal ad to the nonvolatile memory 2, and the selector 5 selects the output data of the nonvolatile memory 2 and
Output.

The address of the nonvolatile memory 2 is designated by the address signal ad, and the program data is read. The program data is input to the microcomputer control unit 3 through the selector 5 and the instruction decoder IDE
At C, the instruction is decoded into a program instruction, and various operations are executed. Thereafter, the count value of the program count IDEC is incremented, the next address is specified in the nonvolatile memory 2, and various instructions are executed according to the program data. The microcomputer repeats the above operation and performs a normal operation.

Next, rewriting of data by an external interrupt during normal operation will be described. After the count value of the program counter PC during normal operation is stored in the register RG, the count value of the program counter PC is set to a predetermined value (for example, 0000H). Thus, it is determined that an address signal designating any one of addresses 0000H to 0100H has been output, and a select signal SE in the first state is output. Therefore, the address signal ad
Is input to the address control unit 1a of the mask ROM 1 via the selector 4 and the transmission gate 6.
Then, the address of the ROM 1 is specified, and the program data of the ROM 1 is read. The program data passes through the transmission gate 8 and is input to the microcomputer control unit 3 via the selector 5. Thereafter, the program counter PC is incremented, and the next address in the ROM 1 is specified.

A program for rewriting data in the nonvolatile memory 2 is written in the ROM 1, and the microcomputer control section 3 operates according to the program. First, an address of the external RAM 12 is specified, and data to be rewritten is read. The read data is held in the register RG of the microcomputer control unit 3 and then read from the nonvolatile memory 2.
Is transferred to the data input unit 2b. The data in the data input unit 2b is written to the nonvolatile memory 2, and the data rewriting is completed. When the rewriting is completed, the count value immediately before the external interrupt stored in the register RG is set to the count value, and the operation returns to the normal operation.

As described above, by applying the H-level test signal, data can be read and written from / to 0000H to 0100H of the nonvolatile memory 2 assigned the same address as that of the ROM 1, and the L-level can be read. By applying the test signal, the program in the ROM 1 can be read.

[0016]

According to the present invention, in the ROM and the nonvolatile memory to which the same address is assigned, the RO during the normal operation is stored.
Since the address of M is designated and the same address as the ROM of the nonvolatile memory is designated at the time of the test, a specific area of the nonvolatile memory which is not used at the time of the normal operation is used at the time of the test. Therefore, the nonvolatile memory can be used effectively.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ROM 2 Non-volatile memory 3 Microcomputer control part 4, 5 Selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/277 G06F 12/00-12/06 G06F 15/78

Claims (3)

(57) [Claims] 1. A non-volatile memory that can be electrically erased in a batch, and a memory for rewriting data in the non-volatile memory.
And a rewriting program is stored ROM, the
The address of a partial area of the nonvolatile memory is
A microcomputer to which the same address as the address is assigned generates an address signal for the nonvolatile memory and the ROM.
The non-volatile memory during normal operation.
Addresses in other areas of the memory and the ROM are continuous.
The address is generated as shown in the figure.
Myco generating address to use some area
A microcomputer comprising a computer control unit . 2. A method according to claim 1, further comprising the steps of :
During normal operation, the address signal for designating the ROM
OM, and select the non-volatile memory during the test.
Selector to select input to some area of the memory
2. The microcomputer according to claim 1 , wherein the selector is configured to conduct the address signal to the ROM or the nonvolatile memory in accordance with a test signal applied from an external circuit. 3. The microcomputer according to claim 2, wherein the selector includes two transmission gates that are turned on or off in accordance with the test signal.