JP3216258B2 - Insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to an insulated gate semiconductor device suitable for high frequency applications.

[0002]

2. Description of the Related Art Conventionally, in the field of insulated gate field effect transistors (MOSFETs) for power use, the Institute of Electronics, Information and Communication Engineers Autumn National Convention C-481 and 1991, 1990.
As described in IEICE Spring National Convention C-569, the gate length and the length of the low-concentration drain region were shortened to improve the high-frequency characteristics, thereby improving the cut-off frequency and the capacitance between the drain and the substrate. Measures were taken to reduce emissions.

[0003]

The above prior art includes M
When the gate length of the OSFET is shortened, the high frequency characteristics are limited by the resistance of the gate electrode and deteriorate,
There has been a problem that the threshold voltage is reduced and the safe operation area is narrowed. Therefore, one object of the present invention is to improve the high frequency characteristics by reducing the resistance of the gate electrode. It is another object of the present invention to provide a high-performance insulated gate semiconductor device by improving a threshold voltage characteristic and a safe operation area.

[0004]

According to one embodiment of the present invention, a second semiconductor region of a first conductivity type is formed on a first semiconductor region of a first conductivity type. (2)
And a third semiconductor region (3) of the first conductivity type formed so as to reach the first semiconductor region (1) from the semiconductor main surface.
And the fourth semiconductor region (4) of the second conductivity type is MOSF
A second conductive type low impurity concentration fifth semiconductor region (5) formed in the second semiconductor region (2) and a second conductive type high impurity concentration sixth semiconductor region ( 6) is a drain region, a gate electrode (9) is formed between the source and the drain via an insulating film (8), and the thickness of the gate electrode (9) is larger than the gate length. (See FIG. 1). A preferred embodiment of the present invention is characterized in that a first conductive type seventh semiconductor region (7) provided adjacent to the end of the source region is provided (see FIG. 1). According to a preferred embodiment of the present invention, the first conductive type seventh semiconductor region (7).
Are formed by ion implantation in a direction oblique to the semiconductor main surface using the gate electrode or an insulator covering the gate electrode as a mask (see FIG. 3).

[0005]

In a typical embodiment of the present invention (FIG. 1), the gate electrode of a MOSFET having a short channel has a thickness greater than the gate length. As a result, the resistance of the gate electrode can be significantly reduced, and the high-frequency characteristics can be improved (FIG. 4).
reference). In a preferred embodiment of the present invention, a high-concentration base region is provided in a pocket shape adjacent to the end of the source region. As a result, the resistance of the gate electrode can be significantly reduced, the high-frequency characteristics of the MOSFET can be improved (see FIG. 4), and the threshold voltage can be reduced (see FIG. 5) by the pocket-like high-concentration base region. A high-performance MOSFET can be provided by preventing a reduction in the safe operation area. When the MOSFET of the present invention is used as a high-frequency power amplifier, it can be operated at an operating frequency of 20 GHz, and the additional efficiency at 2.5 GHz can be improved.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view of an insulated gate semiconductor device according to a first embodiment of the present invention. This element is a common source type high frequency MOSFET. This structure is 0.02Ωcm
A low-concentration P-type semiconductor layer 2 having a thickness of 5 μm epitaxially grown on the following P-type semiconductor substrate 1 is used. From the semiconductor surface, a P-type region 3 serving as a base contact layer
Is formed to a depth of 5 μm or more so as to reach the P-type semiconductor substrate 1. The gate insulating film 8 has a thickness of 30 nm, the gate electrode 9 is made of molybdenum metal, and has a thickness of 0.8 μm and a gate length of 0.4 μm. Here, the feature is that the gate electrode film thickness is larger than the gate length, and as a result, an increase in gate resistance due to a shortened gate length is prevented. Then, the side wall at the end of the gate electrode is placed on the insulator spacer 7.
The low-concentration N-type region 6 having a surface concentration of 1 × 10 ¹⁸ / cm ³ or less is self-aligned in a semiconductor surface region below the insulator 71. Here, the width of the spacer is 0.8 μm, and the width of the drain
The width of the contact region is 0.6 μm. Further, the end of the source region 4 is covered with a pocket-shaped P-type semiconductor region 7, which is connected to the base region 3. The aluminum metal drain electrode 12 and the source electrode 10
Are connected to the high-concentration N-type regions 6 and 4. The source electrode 11 on the back surface is connected to the source electrode 10 via the P-type semiconductor substrate 1 and the P-type region 3.

FIG. 2 is a plan view of a MOSFET according to the present invention. The gate electrode 9 is formed in a stripe shape, and the length of the stripe is 300 μm. The gate extraction electrode is connected to a bus line portion of the stripe electrode. Further, the drain electrode 12 serves as an extraction electrode as it is, and the source electrode 10 functions as a short bar connecting the base 3 and the source 4.

FIG. 3 is a sectional structural view showing a main manufacturing process of the MOSFET of the present invention.

(A) After forming the gate insulating film 8, a molybdenum metal and an insulating film 70 are applied to form a gate electrode 9. Thereafter, (b) the insulating film is formed to a thickness of 0.8 μm by the CVD method.
Then, an insulating film spacer 71 is formed by dry etching on the entire surface. Next, the semiconductor main surface is obliquely irradiated with boron ions 7 'as shown in the figure. The acceleration energy is 75 ke
V, the dose is 5 × 10 ¹³ / cm ² . In this case, the gate electrode 9 and the insulating film spacer 71 which are juxtaposed as shown in the figure serve as a mask, and the P-type region 7 on the pocket is hardly formed in the drain region but formed only on the source side. (C) Using the insulating film spacer 71 as a mask, the low concentration drain region 5 and the high concentration source region 4 are formed by ion implantation. The implantation amount was 5 × 10 ¹³ / cm ^{2 for} phosphorus at the drain and 1 × 10 ¹⁵ / cm for arsenic at the source.
cm ² . (D) A high concentration drain region 6 for drain electrode contact is formed. The implantation amount is 1 × 10 ¹⁵ / cm ² arsenic.
It is. The following steps can be manufactured by using a high-frequency semiconductor process that is usually performed, and thus description thereof is omitted. The feature of this structure is that the thickness of the gate electrode film is larger than the gate length, so that the increase in gate resistance is suppressed even if the gate length is shortened, and a pocket-like base region is provided to cover the source end. Therefore, even if the gate length is shortened, the threshold voltage and the safe operation area are suppressed from being reduced, and further, since the pocket-shaped base region hardly contacts the drain region, the increase in the capacitance between the drain and the source is also suppressed. .

FIGS. 4 and 5 are explanatory diagrams of characteristics showing the effect of the present invention. FIG. 4 shows the cutoff frequency ft of the power MOSFET.
Is dependent on the channel length Lc. Here, the gate electrode film thickness is constant at 0.3 μm in the conventional structure, but is 0.6 μm or more when Lc is 0.5 μm and Lc is 0.1 μm in the structure of the present invention.
At 3 μm, it is set to 0.6 μm or more. ft is Lc
However, when Lc is 0.5 μm or less, the conventional structure is limited by an increase in gate resistance. On the other hand, in the structure of the present invention, even if Lc becomes 0.5 μm or less, ft improves as shown in the figure. FIG.
Is the channel length Lc dependence of the threshold voltage V _T of the MOSFET. Here, in the structure of the present invention, a pocket-shaped base region is provided. Lc is 1.0 μm in the conventional structure
In the following cases, performance degradation such as a decrease in V _{T and an} increase in variation occurs.
Up to about μm, performance degradation hardly occurs. Also,
The power MOSFET having the structure of the present invention does not cause a reduction in the safe operation area due to secondary breakdown or the like.

FIG. 6 is a sectional structural view of an insulated gate semiconductor device according to a second embodiment of the present invention. In this embodiment, the MO
The drain region 61 of the SFET is formed by stacking polycrystalline silicon doped with an N-type impurity on the low concentration drain region 5. As a result, the contact area between the high-concentration drain region and the silicon substrate was reduced, and the capacitance between the drain and the source could be reduced. Further, the distance from the end of the high-concentration drain region 61 to the end of the gate electrode 9 in the low-concentration drain region 5, that is, the effective offset length was increased, and the drain withstand voltage was improved by about 10V.

FIG. 7 is a sectional structural view of an insulated gate semiconductor device according to a third embodiment of the present invention. In this embodiment, the MO
The drain electrode of the SFET is multi-layered and a second extraction drain electrode 13 is provided to increase the current capacity and improve the degree of freedom of the interconnection of the extraction electrode. In this structure, since the width of the first layer drain electrode is small, it is necessary to increase the current capacity.

FIG. 8 is a sectional structural view of an insulated gate semiconductor device according to a fourth embodiment of the present invention. In this embodiment, the MO
The source electrode 10 of the SFET is taken out from the surface of the semiconductor substrate. A plurality of juxtaposed gate electrodes 9 have a film thickness of 0.8 μm and a gate length of 0.4 μm, and are formed by using an insulator spacer 71 formed so as to cover an end side wall of the gate electrode as a mask. Concentration source region 2,
An N-type low-concentration drain region 5, an n-type high-concentration drain region 6, and a pocket-shaped base region 7 are formed.
As a result, the area of the source region can be reduced, and the degree of integration is improved.

FIG. 9 is a circuit layout diagram of a communication high-frequency amplifier module according to a fifth embodiment of the present invention. In this embodiment, the MOSFETs (Q1, Q1) described in the first embodiment are used.
In addition to 2, Q3), a high-frequency matching circuit such as a resistor, a capacitor, and an impedance was arranged as shown in the figure and modularized on a ceramic substrate. As a result, at a power supply voltage of 3 V and an operating frequency of 2.5 GHz, an output power of 2 W and an additional efficiency of 60% were achieved, and the performance was significantly improved as compared with the conventional one.

[0015]

According to the present invention, the resistance of the gate electrode can be greatly reduced, the cutoff frequency of the MOSFET can be improved, and the threshold voltage can be reduced and the safe operation can be achieved by the pocket-like high concentration base region. Since a high-performance MOSFET can be provided by preventing the area from being reduced, the MOS
There is an effect that the high frequency characteristics of the FET are significantly improved.

[Brief description of the drawings]

FIG. 1 is a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a semiconductor device illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a characteristic explanatory diagram of the first embodiment of the present invention.

FIG. 5 is a characteristic explanatory diagram of the first embodiment of the present invention.

FIG. 6 shows a semiconductor device according to a second embodiment of the present invention.

FIG. 7 shows a semiconductor device according to a third embodiment of the present invention.

FIG. 8 shows a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 shows a semiconductor device according to a fifth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type high concentration semiconductor substrate, 2 ... P type semiconductor region, 3 ...
P-type base region, 4 ... N-type source region, 5 ... N-type low-concentration drain region, 6 ... N-type high-concentration drain region, 61 ... N
Type polycrystalline drain region, 7 P-type base region, 7 'boron ion beam, 70 insulating film, 71 insulating film spacer, 8 gate insulating film, 9 gate electrode, 10 source electrode, 11 source Back electrode, 12 ... Drain electrode, 1
3 ... take-out drain electrode, 14 ... base substrate electrode.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-88773 (JP, A) JP-A-63-124572 (JP, A) JP-A-3-11731 (JP, A) JP-A-2- 174169 (JP, A) JP-A-53-84484 (JP, A) JP-A-52-86777 (JP, A) JP-A-1-98262 (JP, A) JP-A-2-260449 (JP, A) (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78

Claims (4)

(57) [Claims] A semiconductor substrate of a first conductivity type; a first semiconductor region of the same conductivity type as the semiconductor substrate, the first semiconductor region having a channel formed on a main surface of the semiconductor substrate; A gate electrode formed on the semiconductor region via a gate insulating film, and a source region and a drain region of a second conductivity type formed in the first semiconductor region and having a conductivity type opposite to the first conductivity type. A second semiconductor region of a first conductivity type reaching the semiconductor substrate from the surface of the first semiconductor region;
A drain electrode connected to the drain region; a source electrode connected to the source region and the second semiconductor region; a source electrode on a back surface connected to the back surface of the semiconductor substrate; and a connection to the drain electrode. A drain electrode formed on the side of the source region, the first region being located below the gate electrode in contact with the source region on the side of the source region.
A third semiconductor region of conductivity type is provided, and a PN junction is formed by the source region and the third semiconductor region. On the drain region side, a PN junction is formed by the drain region and the first semiconductor region. An insulated gate semiconductor device, wherein a junction is formed, and a thickness of the gate electrode is larger than a gate length. 2. The insulated gate semiconductor device according to claim 1, wherein said first conductivity type is P-type and said second conductivity type is N-type. 3. The drain region includes a low-concentration region and a high-concentration region formed in separate steps, the drain electrode is connected to the high-concentration region, and the low-concentration region and the first
3. The insulated gate semiconductor device according to claim 1, wherein a PN junction is formed with said semiconductor region. 4. A semiconductor substrate of a first conductivity type, a first semiconductor region of the same conductivity type as the semiconductor substrate, the first semiconductor region being formed on a main surface of the semiconductor substrate and having a channel formed therein; A gate electrode formed on the semiconductor region via a gate insulating film, and a source region and a drain region of a second conductivity type formed in the first semiconductor region and having a conductivity type opposite to the first conductivity type. A second semiconductor region of a first conductivity type reaching the semiconductor substrate from the surface of the first semiconductor region;
A drain electrode connected to the drain region; a source electrode connected to the source region and the second semiconductor region; a source electrode on a back surface connected to the back surface of the semiconductor substrate; and a connection to the drain electrode. A third semiconductor region of a first conductivity type is provided on the source region side in contact with the first semiconductor region and below the gate electrode, and a third semiconductor region of the first conductivity type is provided on the source region side. An insulated gate semiconductor device, wherein a PN junction is formed by the drain region and the third semiconductor region, and a PN junction is formed by the drain region and the first semiconductor region on the drain region side. .