JP3214673B2 - MUSE decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for quickly detecting the deenergization of a video signal so that the audio data and the like superimposed on the video signal can be detected .
The present invention relates to a decoder circuit that can quickly mute a reproduction output .

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 3-124 previously proposed by the applicant.
Japanese Patent Publication No. 178 discloses that audio data compressed and multiplexed on a time axis in a MUSE signal is separated and expanded on a time axis, a loss of an audio frame synchronization signal included in the audio data is detected, and the detected loss is determined by a specified number of times. A technique for muting the demodulated audio data when the above-described continuous occurrence occurs is disclosed, in which a specified number of times is switched according to the transmission system of the input MUSE signal. Accordingly, the audio mute is performed only when the synchronization loss for a certain period or more has occurred.

[0003]

However, when the above-mentioned conventional example is adopted, even if the MUSE signal is suddenly extinguished, the mute is delayed by further synchronizing the frame synchronization signal after the time base is extended. . Therefore, when the MUSE signal was suddenly interrupted, a noise sound was generated before the mute.

[0004] Therefore, it is necessary to quickly detect the interruption of the MUSE signal.

[0005]

Accordingly, a decoder circuit according to the present invention comprises: a phase detecting means for detecting a phase of a horizontal synchronizing signal in a video signal to generate a phase detection output; A comparison unit that compares the output with a reference range and generates a comparison output when the phase detection output is out of the reference range; and generates a detection output when the comparison output from the comparison unit is counted by a certain number or more. Signal deactivation detecting means. Also, the decoder circuit of the present invention detects a phase of a horizontal synchronization signal in a video signal to generate a phase detection output, and compares the phase detection output from the phase detection means with a reference range, A comparison unit that generates a comparison output when the phase detection output is out of a reference range; a signal deactivation detection unit that generates a detection output when the comparison output from the comparison unit is counted by a certain number or more; And an audio mute unit for receiving a detection output from the deactivation detection unit and preventing derivation of a demodulated output of audio data superimposed on the video signal.

[0006]

According to the present invention, when the phase fluctuation of the horizontal synchronizing signal is detected more than a certain number of times, the interruption of the MUSE signal is detected.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. In the present embodiment, as shown in FIG. 2, the AD conversion data is converted into the corresponding latch pulse P4 at the fourth sampling point, the sixth sampling point, and the eighth sampling point in each horizontal scanning period of the MUSE signal. Latching is performed at P6 and P8, and the value of the latched data is calculated to detect the attenuation of the horizontal synchronization amplitude or the deviation of the horizontal synchronization phase a predetermined number of times, thereby detecting the deactivation of the video signal.

FIG. 3 shows an amplitude detecting circuit 14 which inputs the first latch data L1 at the fourth sampling point, the second latch data L2 at the sixth sampling point, and the third latch data L3 at the eighth sampling point. FIG. 3 is a circuit block diagram specifically showing a phase detection circuit 15, and an amplitude detection circuit 14 for detecting a horizontal synchronization amplitude is provided with first and third latch data L1.
L3 is subtracted by the first subtraction circuit 14A, and the value is
The absolute value is converted into an absolute value by the absolute value conversion circuit 14B to obtain the absolute value of the amplitude. Further, the phase detection circuit 15 for detecting the phase of the horizontal synchronizing signal converts the addition value obtained by inputting the first and third latch data L1 and L3 to the addition circuit 15A into a value obtained by doubling the data of the horizontal synchronization timing. The second latch data L2 is input to the doubling circuit 15B, the doubling value obtained is obtained as comparison timing data, and the second subtraction circuit 15C subtracts the doubling value from the addition value and calculates the subtraction value. The value is obtained as a phase shift amount, and the value is obtained as a second absolute value
The absolute value is calculated at D.

Hereinafter, the circuit operation of the present embodiment shown in FIG. 1 will be described. First, the MUSE signal input from the MUSE disk player is A-degree converted by the AD conversion circuit 1 and input to the first to third latch circuits 11, 12, and 13 and the data decompression circuit 2, respectively. The data decompression circuit 2 separates the time-division-compressed and multiplexed compressed and modulated audio data and expands the time axis to generate continuous modulated audio data. Therefore, the compressed modulated audio data separated from the vertical blanking period is expanded in the subsequent video period and is derived as modulated audio data. The ternary / binary conversion circuit 3 which receives the modulated audio data demodulates the ternary data into binary data. The demodulated audio data is subjected to frame deinterleaving, word deinterleaving, and dot deinterleaving by a deinterleaving circuit 4. The deinterleaved data is D
The signal is demodulated by the PCM demodulation circuit 5, input to the DA conversion circuit 10 via the mute circuit 6, and derived as an audio signal.

The above-mentioned mute circuit 6 is configured to be in a mute state when synchronization is interrupted for a certain period of time when normal mute data is detected. 7 and a synchronization detection / compensation circuit 8. The mute code detection circuit 7 detects that the 16th bit of the speech suppression data included in the control code in the speech data has become “1” at a certain frequency or more, and generates a mute detection output. I have. In addition, the synchronization detection / compensation circuit 8
In addition to detecting an audio frame synchronizing signal having an msec period, the synchronizing component is supplied to the DPCM demodulation circuit 5 by synchronizing for a fixed period of 36 msec during the synchronizing loss period. Output is occurring. Accordingly, the mute control circuit 9, which inputs the mute detection output and the signal loss detection output, supplies a mute signal to the mute circuit 6 in response to the input of each output, and activates the mute circuit 6. The above D
The PCM demodulation circuit 5 generates a demodulated output for a fixed period even during the synchronization loss period by the synchronization compensation.

In this embodiment, in addition to the above-described conventional configuration,
The mute circuit 6 is activated by detecting the interruption of the MUSE signal quickly. First, the first latch circuit 11 latches the AD conversion data at the fourth point with a latch pulse P4 synchronized with the fourth point, and generates a first latch output L1. The second latch circuit 12 outputs a latch pulse P6 synchronized with the sixth point.
Latches the AD conversion data at the sixth point to generate a second latch output L2. Further, the third latch circuit 13 latches the A / D conversion data at the eighth point with a latch pulse P8 synchronized with the eighth point, and generates a third latch output L3.

The amplitude detection circuit 14 has a first latch output L1
And the third latch output L3, and the absolute value of the amplitude is detected as described above. Similarly, the phase detection circuit 15
Also, the first latch output L1, the second latch output L2, and the third latch output L3 are input to detect the absolute value of the phase shift amount. The amplitude detection output obtained from the amplitude detection circuit 14 is compared with a reference value F in a first comparison circuit 16 and generates an attenuation detection output when the amplitude detection output is equal to or smaller than the reference value. The phase detection output obtained from the phase detection circuit 15 is
Is compared with the reference range G, and a phase shift detection output is generated when it is out of the reference range.

The selection circuit 18 selects one or both of the attenuation detection output and the phase shift detection output according to the setting, and supplies it to a counter 19 functioning as a signal deactivating means. The counter 19 generates a video signal deactivation detection output when the selection output continuously counts over the set value, and supplies the output to the mute control circuit 9. The set value of the counter 19 can be manually switched to four types of 2, 4, 8, and 16, and the continuous loss period can be set in the range of 2 to 16 lines.

The mute signal output from the mute control circuit 9 is output during the period when the audio signal is stably derived even if the MUSE signal is suddenly interrupted. As a result, the mute circuit 6 operates before noise occurs due to signal interruption.
In the above-described configuration, the mute state is set on the assumption that the reproduction synchronization signal is always lost at the end of the reproduction MUSE signal. There is also a MUSE playback player for switching. MUS like this
The E player needs to momentarily interrupt the reproduction MUSE signal immediately before switching to the blue back.

FIG. 4 is a circuit block diagram of a MUSE disk player for correctly operating the MUSE decoder of this embodiment. As is clear from this figure, the reproduced FMMUSE signal obtained from the pickup 20 is FM-demodulated by the FM demodulation circuit 21 and digitized by the AD conversion circuit 22. On the other hand, the reproduced pilot signal reproduced from the pickup is selected by the bandpass filter 23,
It is supplied to the LL circuit 24. This PLL circuit 24 generates a PLL output whose frequency changes according to the jitter component. The write address generation circuit 25 which receives the PLL output as a clock input supplies the write address signal to a jitter correction memory 26, and the memory 26 stores the AD conversion output in synchronization with the jitter component. On the other hand fixed crystal oscillation circuit 2
The oscillation output of 7 is supplied to a read address generation circuit 28 and a blue back data number generation circuit 29. The read address signal is supplied to the memory 26 to derive MUSE data without jitter components from the memory 29. This MUS
The E data is supplied to the switching circuit 30 together with the blue-back data, and at the same time, is input to the synchronization detection circuit 31. The detected frame synchronization pulse is input to the blue-back data generation circuit 29 as a reset input and is also supplied to a switching pulse generation circuit 32. As a result, the blue background data is synchronized with the MUSE data. The switching pulse generation circuit 32
Is a first switching pulse that is inverted at the end timing of the frame synchronization pulse immediately after the stop signal generated by the system control circuit not shown in response to a reproduction stop operation, and 10 horizontal synchronizations are performed at the end timing of the frame synchronization pulse. A second switching pulse that is output only during the interval is generated. The switching circuit 30 having these switching pulses as control inputs receives intermediate level data generated by the intermediate level data generating circuit 33 as a third signal input, and responds to the first switching pulse to output MUSE data and blue-back data. The data is switched, and the switching output and the intermediate level data are switched in response to the second switching pulse. A switching output obtained as a result is derived through a DA conversion circuit 34, and is output as a reproduced MUSE signal as shown in FIG.
Supplied to the decoder. Therefore, the reproduced MUSE signal is
As shown in FIG. 5, the MUSE decoder temporarily interrupts and switches to the blue back signal, and the MUSE decoder that detects this interruption as interruption of the reproduction synchronization signal mutes the audio signal in response to the end of reproduction. If the MUSE disk player is configured in this manner, the MUSE signal is interrupted during the vertical blanking period, so that there is no effect on the video and stable switching is possible.

In the above-described embodiment, the circuit block diagram is constituted by a hardware circuit. However, a part of the circuit block diagram may be constituted by microcomputer software, and such a structure is included in the present invention. Nor. Furthermore, the illustrated embodiment can be variously modified as necessary, and it goes without saying that the present invention is included in the present invention as long as the modifications are included in the claims.

[0017]

Thus, according to the present invention, the audio signal is muted almost simultaneously with the interruption of the video during the period in which the audio signal is correctly derived.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a horizontal synchronization signal waveform and a sampling point.

FIG. 3 is a main part circuit block diagram of the present embodiment.

FIG. 4 shows a MUS for normal operation of the embodiment of the present invention.
It is a circuit block diagram of an E disk player.

FIG. 5 is a diagram showing a no-signal-necessary waveform of FIG. 4;

[Explanation of symbols]

 6 Mute circuit 14 Amplitude detecting means 15 Phase detecting means 16 First comparing means 17 Second comparing means 19 Counter

Continuation of front page (72) Inventor Tateo Toyama 2-18 Keihanhondori, Moriguchi City Sanyo Electric Co., Ltd. (56) References JP-A-1-314483 (JP, A) (58) Fields investigated (Int. H04N ^7/ 00-7/088 H04N 5/04 H04N 5/44 H04N 5/60

Claims (2)

(57) [Claims] 1. A comparison between the phase detection means for generating a phase detection output by detecting the phase of the horizontal synchronizing signal in the video signal, and a phase detection output and the reference range from the phase detecting means, the phase detection output A decoder circuit for generating a comparison output when the reference value is out of a reference range, and a signal deactivation detection unit for generating a detection output when the comparison output from the comparison means is counted by a certain number or more. . 2. A comparison between the phase detection means for generating a phase detection output by detecting the phase of the horizontal synchronizing signal in the video signal, and a phase detection output and the reference range from the phase detecting means, the phase detection output A comparison means for generating a comparison output when the value is out of a reference range, a signal deactivation detection means for generating a detection output when the comparison output from the comparison means is counted by a certain number or more, and the signal deactivation detection means And an audio mute means for receiving a detection output from the audio signal and preventing derivation of a demodulated output of audio data superimposed on the video signal.