JP3211352B2 - Method of forming metal plug in semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a metal plug in a semiconductor device, and more particularly to a method for forming a metal plug by a selective CVD method.

[0002]

2. Description of the Related Art In a semiconductor device, a contact hole or a via hole (hereinafter, also referred to as a connection hole) is formed in order to electrically connect an upper wiring layer with an impurity diffusion region or a lower wiring layer formed in a semiconductor substrate. Is provided. In order to form a connection hole, a method is generally used in which an interlayer insulating layer is formed on such a semiconductor substrate, an opening is provided in the interlayer insulating layer, and a wiring material is embedded in the opening. As a method of embedding a wiring material in an opening, a method of forming a metal wiring material such as aluminum by a sputtering method has been conventionally used.

However, as the size of the opening becomes finer and the aspect ratio becomes larger, it becomes more difficult to fill the opening by sputtering. Therefore,
As a technique for embedding a fine opening with a wiring material, a so-called blanket CVD method or a selective CVD method has attracted attention.

An outline of a technique for forming a metal plug (tungsten plug) in an opening by a blanket CVD method using tungsten as a wiring material is as follows. First, an opening is provided in an interlayer insulating layer formed on a semiconductor substrate, a tungsten layer is formed on the upper surface of the interlayer insulating layer and the opening by a CVD method, and then a tungsten layer formed on the upper surface of the interlayer insulating layer is formed. To etch back. As a result, a metal plug made of tungsten is formed in the opening. In this blanket tungsten CVD method, since tungsten grows from the bottom and side walls of the opening, voids are likely to occur at the center of the metal plug formed in the opening. Therefore, in the blanket tungsten CVD method, embedding in an opening having a diameter of 0.35 μm is limited, and it is desirable to employ a selective CVD method in order to embed a finer opening with a wiring material. It is considered.

The outline of a conventional method of forming a connection hole by a selective CVD method using tungsten as a wiring material is as follows. First, an interlayer insulating layer is formed on a semiconductor substrate by a thermal CVD method or the like, and an opening is provided in the interlayer insulating layer by, for example, a photolithography method and a reactive ion etching method. Next, by applying the fact that tungsten is difficult to deposit on the interlayer insulating layer, tungsten is deposited only in the opening by the CVD method, and a tungsten plug is formed in the opening. Thus, a connection hole in which the opening is filled with tungsten is completed.

[0006]

The selective tungsten C is directly placed on the impurity diffusion region formed in the silicon substrate.
Applying the VD method, for example, a thin film transistor (TFT)
Is formed, the TFT is subjected to a heat treatment at 600 ° C. or higher in a later step, but in this heat treatment step, tungsten reacts with Si of the silicon substrate. As a result, there arises a problem that the junction formed on the silicon substrate is destroyed and the leak current increases.

As a countermeasure, a method of forming a barrier metal layer at an interface between a silicon substrate and a tungsten plug has been studied. However, select tungsten
The CVD method has a problem that it is difficult to form tungsten on the barrier metal layer. Another problem is that it is difficult to form a barrier metal layer only in the opening.

Therefore, a method for simply forming a barrier metal layer only in an opening and a method for easily forming a growth nucleus for crystal growth of a wiring material for forming a metal plug only on the barrier metal layer in the opening. There is a need for a way to do that.

Accordingly, it is an object of the present invention to provide a barrier metal layer which can be simply formed only in an opening, and a growth nucleus for crystal-growing a wiring material for forming a metal plug is formed in the barrier metal in the opening. An object of the present invention is to provide a method for forming a metal plug that can be easily formed only on a layer.

[0010]

According to the present invention, there is provided a method of forming a metal plug, comprising the steps of: forming an opening in an interlayer insulating layer formed on a semiconductor substrate; Then, a metal plug is formed in the opening by a selective CVD method. (A) forming a barrier metal layer on the upper surface of the interlayer insulating layer and in the opening, and then forming a growth nucleus on the barrier metal layer for crystal growth of a wiring material for forming a metal plug; (B) removing a growth nucleus and a barrier metal layer formed on the upper surface of the interlayer insulating layer by a polishing method; and (c) crystal-growing a wiring material from the growth nucleus by a selective CVD method, Forming a metal plug on the substrate.

The barrier metal layer is made of TiN, Ti / Ti
N, TiSi ₂ / TiN, TiON, Ti / TiON,
Preferably, it is made of TiSi ₂ / TiON, TiW. A metal plug is formed on TiN, TiON or TiW. For example, the barrier metal layer is made of Ti, TiSi so that a good ohmic contact can be obtained by reacting with an impurity diffusion region or the like formed on the silicon substrate.
₂ , MoSi ₂ , WSi ₂ , other metal layers or metal silicide layers.

The growth nucleus is formed by reducing the material gas of a metal plug used in the selective CVD method, such as Ti, W, Mo, Ni or a silicide of these metals, copper, aluminum, polysilicon, amorphous silicon, etc. The wiring material forming the plug can be selected from substances capable of crystal growth.

The metal plug and the wiring material for forming the metal plug are made of tungsten. Alternatively,
It can also be formed by selective CVD using aluminum.

The polishing method (chemical mechanical polishing method)
In recent years, mirror-finished semiconductor substrates, SOI (Silicon On I
nsulator) is a technology used in devices, for example, the document "Trench Insulator by Selective Epi and CV
D Oxide Cap ”J. Electrochem SOC, Vol. 137, No. 1
2, as disclosed in December 1990, it is also applied to the planarization of an interlayer insulating layer. FIG. 4 shows an outline of the polishing apparatus 100 used for the polishing method. This polishing device 1
Reference numeral 00 includes a polishing plate 102, a substrate support 110, and a slurry supply system 116. The polishing plate 102 is supported by a rotating polishing plate rotation shaft 106, and a polishing pad 104 is provided on the surface thereof. Substrate support 1
Numeral 10 is arranged above the polishing plate 102 and is supported by a substrate support base rotating shaft 112. Substrate 1 to be polished
08 is placed on the substrate support 110. The substrate support base rotation shaft 112 is attached to a polishing pressure adjusting mechanism 114 that presses the substrate support base in the direction of the polishing pad. The slurry 120 containing the abrasive is supplied from the slurry supply system 116 to the polishing pad 104 through the slurry supply port 118.

The polishing method uses such a polishing apparatus 100.
Is used. Then, the polishing plate 102 is rotated while the slurry 120 containing the abrasive is supplied to the polishing pad 104. At the same time, the polishing pressure of the substrate 108 with respect to the polishing pad 104 is adjusted by the polishing pressure adjusting mechanism 114 while rotating the substrate 108 placed on the substrate support 110. Thus, the surface of the substrate 108 can be polished.

Alternatively, as described in Japanese Utility Model Laid-Open No. 63-754, slurry is applied to a polishing plate rotating shaft 1.
06 and the inside of the polishing plate 102, the slurry can be supplied from a slurry supply port 118 provided in the polishing pad 104 (see FIG. 5).

In a preferred embodiment of the method of the present invention, the growth nucleus is made of a metal or a metal silicide, and the barrier metal layer and the growth nucleus are formed by an electron cyclotron resonance CVD method (hereinafter, also referred to as an ECR CVD method). It is formed.

Further, in a further preferred embodiment of the method of the present invention, between the steps (b) and (c), the growth nuclei formed on the side walls of the opening are removed by plasma etching.

[0019]

According to the metal plug forming method of the present invention, after forming the barrier metal layer and the growth nucleus, the growth nucleus and the barrier metal layer formed on the upper surface of the interlayer insulating layer are removed by the polishing method. , A barrier metal layer and a growth nucleus are left. Therefore, the metal plug can be reliably formed in the opening by the selective CVD method.

In a preferred embodiment of the present invention, the barrier metal layer and the growth nucleus are formed by ECRCVD. A thin film formed by ECR CVD has an anisotropic deposition shape. That is, the barrier metal layer and the growth nucleus are formed thinner on the interlayer insulating layer and on the side wall of the opening than at the bottom of the opening. This is because the reaction gas activated by electron cyclotron resonance has directionality.
Anisotropic deposition is more pronounced at lower pressures, as the mean free path of the reactant gas increases.

In a further preferred embodiment of the present invention, the growth nuclei formed on the side walls of the opening are removed by plasma etching. Since the plasma etching isotropically etches the growth nuclei, the growth nuclei formed on the side walls are etched earlier than the growth nuclei formed on the bottom of the opening. As a result, when the metal plug is formed by the selective CVD method in the next step, it is possible to prevent the wiring material from growing from the side wall of the opening and to form a finer connection hole.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. The method of the present invention will be described by way of an embodiment in which the barrier metal layer is made of Ti / TiN, the growth nucleus is made of Ti, and the wiring material for forming the metal plug and the metal plug are made of tungsten.

(Example 1) [Step-100] After an interlayer insulating layer 14 made of SiO ₂ and having a thickness of 800 nm is formed on a silicon substrate 10 by a CVD method, a conventional method such as a photolithography method and a relithography method is used. An opening 16 is formed in the interlayer insulating layer 14 by an active ion etching method (see FIG. 1A). Note that an impurity diffusion region 12 is formed in the silicon substrate 10.

[Step-110] A barrier metal layer 22 of Ti / TiN is formed on the interlayer insulating layer 14 and in the opening 16 by ECR CVD at 20/100 nm each. In FIG. 1B, reference numeral 18 denotes a Ti layer, and reference numeral 20 denotes a TiN layer. The thickness is a thickness on the interlayer insulating layer, and the same applies to the following description of the thickness. The thickness at the bottom of the opening varies depending on the conditions of the ECR CVD method and the structure (depth, diameter, etc.) of the opening, but is generally about 50% of the thickness on the interlayer insulating layer.

The conditions for forming the Ti layer 18 are as follows. TiCl ₄ / H ₂ / Ar = 10/30/5 sccm Microwave power 3 kW Temperature 600 ° C. Pressure 0.1 Pa Note that H ₂ and Ar are turned into plasma by electron cyclotron resonance. The conditions for forming the TiN layer 20 are as follows. TiCl ₄ / N ₂ / H ₂ / Ar = 10/15/50 / 5scc
m Microwave power 3 kW Temperature 600 ° C. Pressure 0.1 Pa Note that N ₂ , H ₂ and Ar are turned into plasma by electron cyclotron resonance.

[Step-120] Next, a growth nucleus 24 is formed to a thickness of 50 nm on the barrier metal layer 22 by ECR CVD (see FIG. 1B). The conditions for forming the growth nuclei 24 are as follows. TiCl ₄ / H ₂ / Ar = 10/30/5 sccm Microwave power 3 kW Temperature 600 ° C. Pressure 0.1 Pa Note that H ₂ and Ar are turned into plasma by electron cyclotron resonance.

[Step-130] Next, the barrier metal layer 22 and the growth nuclei 24 formed on the interlayer insulating layer 14 are polished (chemical mechanical polishing).
Method) (see FIG. 1C). The conditions for removal are as follows. As the polishing apparatus, the polishing apparatus shown in FIG. 4 was used. Polishing pressure = 5.0 PSI Polishing plate / substrate support base rotation speed = 12/26 RPM

[Step-140] Thereafter, a metal plug 26 made of heat-resistant tungsten is formed by a selective tungsten CVD method (see FIG. 2). The conditions of the selective tungsten CVD method were as follows. WF ₆ / SiH ₄ / H ₂ = 10/7/1000 sccm Temperature 260 ° C. Pressure 27 Pa Tungsten as a wiring material is crystal-grown from a growth nucleus 24 made of Ti, and a metal plug 2 is formed inside the opening 16.
6 are formed.

In this embodiment, the barrier metal layer 22
In addition, the growth nuclei 24 can be easily formed only inside the openings 16. The upper surface of the interlayer insulating layer is not covered at all, and the wiring material does not grow from the upper surface of the interlayer insulating layer.

Example 2 In Example 2 described below, [Step-130] and [Step-14] of Example 1 were used.
0], a step of removing the growth nuclei formed on the side walls of the opening by plasma etching is adopted.

[Step-200] This step is the same as [Step-100] to [Step-130] in Example 1, and the description thereof is omitted.

[Step-210] Next, plasma etching is performed under the following conditions. As the plasma etching apparatus, a magnetic field microwave etching apparatus was used, but any apparatus that can perform plasma etching may be used. BCl ₃ / Cl ₂ = 30/20 sccm RF wave power 15 W Microwave power 100 W Pressure 100 Pa As shown in FIG. 3, the growth nucleus 2 made of Ti formed on the side wall 16 A of the opening 16 by plasma etching.
Only four need be removed. This can be easily performed by controlling the time of plasma etching. The growth nucleus 24
In addition, a part of the barrier metal layer 22 may be removed. Thus, in the next selective CVD step, the wiring material forming the metal plug can be crystal-grown from the bottom of the opening 16.

[Step-220] Then, selective tungsten CVD is performed in the same manner as in [Step-140] of the first embodiment.
A heat-resistant metal plug is formed in the opening by a method.

In this embodiment, the barrier metal layer 22
Can be easily formed only inside the opening 16, and the growth nucleus 24 can be easily formed at the bottom of the opening 16. Since the wiring material can be grown from the bottom of the opening and prevented from growing from the side wall of the opening, a finer connection hole can be formed than in the first embodiment.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The interlayer insulating layer is made of PSG instead of SiO ₂ .
BSG, BPSG, AsSG, PbSG, SbSG, a silicon nitride film, SOG, SiON, or the like can be used.

In the embodiment, the interlayer insulating layer is formed on the semiconductor substrate on which the impurity diffusion region is formed. However, it is also possible to form the interlayer insulating layer on the semiconductor substrate on which the lower wiring layer is formed. It is included in the method of forming a metal plug.

[0037]

According to the metal plug forming method of the present invention, a growth nucleus consisting of a barrier metal layer and a metal or a metal silicide and serving as a seed for selective growth can be easily formed only in an opening. The metal plug can be reliably formed only in the opening by the method. Then, even in the heat treatment at 600 ° C. or more, a metal plug that does not break the junction formed on the silicon substrate can be formed.

Also, a so-called blanket tungsten CV
A finer connection hole can be formed than the method D.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of an embodiment of a metal plug forming method of the present invention.

FIG. 2 is a schematic partial cross-sectional view of the semiconductor device for illustrating a step following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of a more preferable embodiment of the metal plug forming method of the present invention.

FIG. 4 is a diagram showing an outline of a polishing apparatus suitable for a polishing method (chemical mechanical polishing method) .

FIG. 5 is a diagram showing a part of another polishing apparatus suitable for a polishing method (chemical mechanical polishing method) .

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Impurity diffusion region 14 Interlayer insulating layer 16 Opening 18 Ti layer 20 TiN layer 22 Barrier metal layer 24 Growth nucleus 26 Metal plug 100 Polishing device 102 Polishing plate 104 Polishing pad 106 Polishing plate rotation axis 108 Substrate 110 Substrate support 112 Substrate support rotating shaft 114 Polishing pressure adjusting mechanism 116 Slurry supply system 118 Slurry supply port 120 Slurry

Continuation of the front page (51) Int.Cl. ⁷ identification symbol FI H01L 21/768 H01L 21/88 B (56) References JP-A-2-185025 (JP, A) JP-A-3-233931 (JP, A JP-A-4-30421 (JP, A) JP-A-62-102544 (JP, A) JP-A-62-102543 (JP, A) JP-A-2-268425 (JP, A) 3965 (JP, A) JP 5-259109 (JP, A) JP 5-243179 (JP, A) JP 5-152250 (JP, A) JP 5-90204 (JP, A) JP-A-4-336422 (JP, A) JP-A-4-320330 (JP, A) JP-A-4-29327 (JP, A) JP-A-4-25159 (JP, A) JP-A-4-3934 (JP, A) JP-A-3-239365 (JP, A) JP-A-2-90519 (JP, A) JP-A-2-58217 (JP, A) JP-A-2-3227 (JP, A) JP-A-2-314 (JP, A) JP-A-1-307220 (JP, A) JP-A-64-55861 (JP, A) JP-A-3-255624 (JP, A) JP-A-2-241032 (JP, A) JP-A-63-291437 (JP, A) JP-A-62-291917 (JP, A) JP-A-61-291 248442 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/28 301 H01L 21/28 H01L 21/205 H01L 21/3205 H01L 21/768

Claims (2)

(57) [Claims] 1. A method of forming an opening in an interlayer insulating layer formed on a semiconductor substrate, forming a barrier metal layer, and then forming a metal plug in the opening by a selective CVD method. (B) forming a barrier nucleus on the upper surface of the interlayer insulating layer and in the opening, and then forming a growth nucleus on the barrier metal layer for crystal growth of a wiring material for forming a metal plug; Removing the growth nuclei and the barrier metal layer formed on the upper surface of the interlayer insulating layer by chemical mechanical polishing ; and (c) removing the growth nuclei formed on the side walls of the opening by plasma etching.
Removing by quenching from (d) the growth nucleus causes crystal growth of the wiring material by selective CVD method, characterized in that it comprises the step, thereby forming a metal plug in the opening, the metal plug in the semiconductor device Forming method. 2. The metal plug according to claim 1, wherein said growth nucleus is made of metal or metal silicide, and said barrier metal layer and said growth nucleus are formed by electron cyclotron resonance CVD. Formation method.