JP3208626B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a dynamic RAM having an equalizing circuit for shorting a bit line pair of a memory cell array and a precharge circuit for precharging a bit line.

[0002]

2. Description of the Related Art At present, in a dynamic RAM, a row (R
ow) During the active period of the selection signal, equalization for short-circuiting the bit line pair to equal potential and precharging of the bit line for charging the output capacitance in advance are performed. This is because it is necessary to read the minute electric charge stored in the memory cell capacitor. Conventionally, the equalizing and precharging have been performed on both ends of the bit line, that is, on the sense amplifier unit side and the opposite side.

[0003] That is, as shown in FIG. 10, the sense amplifier unit 101, and the bit line pair BL, with equalizing transistors 102 is connected between BL _B, and the bit line pair BL, BL _B and between the pre-charge power supply Are connected to precharge transistors 103 and 104, respectively, and a precharge / equalize control signal is applied to the gates of the equalize transistor 102 and the precharge transistors 103 and 104.

[0004] Also in the side opposite to the sense amplifier portion 101, similarly to the sense amplifier unit 101, and the bit line pair BL, with equalizing transistors 105 is connected between BL _B, and the bit line pair BL, BL _B Between transistors and precharge power supply, transistors 106 and 10 for precharge
7 are connected to each other, and an equalizing transistor 10
5, and a precharge / equalize control signal is applied to each gate of the precharge transistors 106 and 107.

[0005]

However, in the conventional dynamic RAM provided with the equalizing circuit and the precharge circuit having the above-described structure, the following problems occur as the miniaturization of the memory cell array progresses. That is, the bit line BL, and with wiring BL _B becomes thinner, since the wiring layer thickness is thin, resistance is increased a bit line BL, and BL _B, it takes time to equalize and precharge. In addition, as the cycle time of the dynamic RAM increases, the time available for equalizing and precharging becomes shorter.

Since the reduction in the size of the sense amplifier unit 101 cannot follow the reduction in the memory cell area, as shown in FIG. 11, the layout of the sense amplifier unit 101 is changed to the conventional two memory cell pitch (A). It is necessary to change the memory cell pitch from (4) to four (B).
When the memory cell pitch is changed to four, the sense amplifier unit 1
01 bit line BL, and must be placed at both ends of the BL _B, as apparent from FIG. 11 (B), the bit line B
L, equalize and precharge from both ends of the BL _B is impossible. This leads to an increase in the equalizing time and the precharge time.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide an equalizing circuit and a precharging circuit capable of shortening an equalizing time and a precharging time without lowering the yield. Is to provide.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells arranged adjacent to each other in a memory cell array.
A pair of memory cells connected between each word line and each bit line pair, and a storage node is short-circuited between the pair of memory cells. The configuration includes an equalizing circuit to which a control signal is applied.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a pair of memory cells connected between predetermined two adjacent word lines and bit line pairs in a memory cell array. In each of the pair of memory cells, the storage node and the cell plate are short-circuited, and a precharge circuit for applying a precharge control signal to two word lines is provided. According to a third aspect of the present invention, there is provided a semiconductor memory device including the equalizing circuit according to the first aspect and the precharge circuit according to the second aspect.

[0010]

In the semiconductor memory device according to the first aspect, by using a memory cell as the equalizing transistor, a required number of equalizing transistors can be arranged at a necessary place while maintaining the regularity of the memory cell pattern. According to this, since the regularity of the memory cell pattern is not broken, the yield does not decrease, and the equalizing transistors can be freely arranged, so that the equalizing time can be shortened.

[0011] In the semiconductor memory device according to claim 2,
By using a memory cell as a precharge transistor, a required number of precharge transistors can be arranged at a necessary place while maintaining regularity of a memory cell pattern. According to this, since the regularity of the memory cell pattern is not broken, the yield does not decrease and the precharge transistors can be freely arranged, so that the precharge time can be shortened.

The semiconductor memory device according to claim 3,
By using a memory cell as the equalizing / precharging transistor, the required number of equalizing / precharging transistors can be arranged at a necessary place while maintaining the regularity of the memory cell pattern. According to this, since the regularity of the memory cell pattern is not broken, the yield is not reduced, and the equalizing / precharging transistors can be freely arranged, so that the equalizing / precharging time can be shortened.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, a one-transistor type memory cell 10 including a MOS capacitor C for storing electric charges and a MOS transistor Tr for transferring the electric charges is arranged in an array to form a memory cell array 20.

In this memory cell array 20, predetermined two adjacent word lines, in this example, word line W
Two dummy word lines DWL1 and DW between L3 and WL4
The memory cells 11 _n and 12 _n (n =
..) Are used as dummy memory cells for equalization. This dummy memory cell 1
Of the 1 _n and 12 _n , memory cells connected to the bit line pair BL and BL _B form a pair.

[0015] For example, the memory cell 11 ₁ and the memory cell 1
2 ₁ forms a pair, and this pair of memory cells 11 ₁ , 12
_The storage nodes N1 and N2 are short-circuited between each other. Accordingly, the bit line pair BL by both the memory cells 11 _1, 12 ₁ of the MOS transistor is turned on, equalizing circuit for short-circuiting the BL _B is constituted. An equalizing control signal for operating the equalizing circuit includes word lines WL1 and W1.
After L2,... Are deselected, they are applied to the two dummy word lines DWL1, DWL2,
The MOS transistors ₁₁ and 12 ₁ are turned on.

FIG. 2 shows a pair of memory cells 11 ₁ and 12 _1.
FIG. 14 is a layout diagram showing an example of short-circuiting storage nodes N1 and N2 between each other. FIG. 3 shows a cross-sectional structural view thereof. The memory cell in this example is a stack type memory cell, and is of a type called a shielded bit line type in which the bit line BL is below the storage electrode 21. In this stacked memory cell, a memory transistor is formed from word lines WL1, WL2,... Made of polysilicon and diffusion layer 22, and a dummy word line DWL is formed.
1, an equalizing transistor is formed from DWL2 and the diffusion layer 22, and a bit line BL made of polysilicon is formed thereover via an insulating film (not shown).

The diffusion layer 22 and the bit line BL are connected by a contact portion 23. A storage electrode 21 made of polysilicon is formed further above the bit line BL via an insulating film (not shown). This storage electrode 21
The contact portion 24 is connected to the diffusion layer 22. Further, a cell plate 25 is formed above the storage electrode 21 via a capacitance forming insulating film (not shown). In this example, a pair of memory cells 11 ₁ ,
The short-circuit between the storage nodes N1 and N2 between the storage electrodes 12 _{1 and} 12 _{1 is} particularly apparent from FIG.
1 are connected. In FIG. 2, the storage electrode 21 that is short-circuited is indicated by a thick frame.

FIG. 4 shows a pair of memory cells 11 ₁ and 12 _1.
FIG. 13 is a layout diagram showing another example of short-circuiting storage nodes N1 and N2 between each other. FIG. 5 shows a sectional structural view thereof. In this example, a pair of memory cells 1
Shorting of the storage nodes N1 and N2 between 11 ₁ and 12 ₁ is realized by connecting the diffusion layers 22 of both cells, as is particularly clear from FIG. In FIG. 4, the short-circuited diffusion layer 22 is indicated by a thick frame.

[0019] By employing the circuit configuration and layout configuration as described above, it is possible to equalize for equipotential by shorting the bit line pair BL, BL _B. That is, in the dynamic RAM having the equalizing circuit having the above configuration, after the word lines WL1, WL2,... Are deselected, the equalizing dummy word lines DWL1, DWL
By selecting 2, for example, the memory cells 11 ₁ , 1
2 ₁ bit line pairs each MOS transistor is turned on The BL, for short BL _B, it can be realized equalization. In each of the above examples, a pair of memory cells 11 ₁ ,
12 ₁ between each other, the storage node of both cells by connecting the storage electrode 21 or the diffusion layer 22 of both cells N
1 and N2 are short-circuited, but it goes without saying that both the storage electrode 21 and the diffusion layer 22 of both cells may be connected.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In FIG. 6, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, in the memory cell 20 having the same structure as that of the first embodiment, for example, the word line WL
3 and WL4, two dummy word lines DWL1 and DWL
2 connected to the memory cells 11 _n , 12 _n (n = 0,
1, 2,...) Are dummy memory cells for precharging.

In each of the pair of memory cells 11 ₁ and 12 ₁ , the storage nodes N 1 and N 2 and the cell plate 25
Is short-circuited. Thus, a pair of memory cells 11 _1, 12 ₁ of the MOS transistor is turned on, the bit line BL, and a precharge circuit for precharging BL _B to the potential Vcp of the cell plate 25 is formed. The precharge control signal for operating the precharge circuit includes word lines WL1, WL2,.
Are not selected after the two dummy word lines DWL
1, DWL2 and both memory cells 11 ₁ , 12 ₁
Are turned on.

FIG. 7 is a sectional structural view of a memory cell in the case of the second embodiment. In the drawing, the storage node N1 in a pair of memory cells 11 _1, 12 ₁ each,
A short circuit between N2 and the cell plate 25 can be used as an insulating film (not shown) for forming a capacitance of a memory cell used for precharging.
Is realized by removing a part or all of the above and connecting the storage electrode 21 and the cell plate 25.

In the dynamic RAM having the precharge circuit having the above configuration, the word lines WL1, WL2,.
Are deselected, the dummy word lines DWL1 and DWL2 for precharge are selected, for example, the MOS transistors of the memory cells 11 ₁ and 12 ₁ are turned on, and the bit lines BL and BL _B are pre-selected. Charge. At this time, the bit line BL is connected to the potential Vcp of the cell plate 25.
Precharged until When the precharge level is set to a potential different from the potential Vcp of the cell plate 25, a cell plate of a memory cell used for precharge is separated from a cell plate of a normal memory cell, and a different potential is applied. realizable.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention. In the drawing, the same parts as those in FIG. 1 are denoted by the same reference numerals. The configuration of this embodiment is a configuration in which the first embodiment and the second embodiment are combined. That is,
A pair of memory cells 11 _1, 12 ₁ as well as short storage nodes N1, N2 between each other, the storage node in the pair of memory cells 11 _1, 12 ₁ of each N1, N
2 and the cell plate 25 are short-circuited, and an equalizing circuit and a precharge circuit are realized using the same memory cell.

As shown in FIG. 9, the structure of the first embodiment (for example, the structure shown in FIG. 3) and the structure of the second embodiment (structure shown in FIG. 7) are combined. Can be realized by In the dynamic RAM having the equalizing circuit and the precharge circuit having the above configuration, after the word lines WL1, WL2,... Are deselected, the dummy word lines DWL1, DWL for equalizing and precharging are used.
By selecting 2, it is possible to realize equalization and precharge of the bit line.

In each of the above embodiments, a case has been described in which the present invention is applied to a dynamic RAM using a memory cell of a stack type shielded bit line. However, the present invention is not limited to this. The present invention is also applicable to a dynamic RAM using cells.

[0027]

As described above, according to the first aspect of the present invention, a dummy memory cell is used as an equalizing transistor, and the equalizing transistor is placed in a necessary place while maintaining the regularity of the memory cell pattern. By enabling the required number of arrangements, the regularity of the memory cell pattern is not broken, so that the yield does not decrease and the equalizing transistors can be arranged freely, so that the equalizing time can be shortened. .

According to the second aspect of the present invention, a required number of precharge transistors can be arranged at required locations while using a dummy memory cell as a precharge transistor while maintaining the regularity of the memory cell pattern. By doing so, the regularity of the memory cell pattern is not broken, the yield does not decrease, and the transistors for precharge can be arranged freely, so that the precharge time can be shortened.

According to the third aspect of the present invention, a memory cell is used as an equalizing / precharging transistor, and the required number of equalizing / precharging transistors is provided at a necessary place while maintaining regularity of a memory cell pattern. By enabling the arrangement, the regularity of the memory cell pattern is not broken, so that the yield does not decrease, and the equalizing / precharging transistors can be freely arranged, thereby shortening the equalizing / precharging time. become.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a layout diagram showing an example of a case where a storage node is short-circuited between a pair of memory cells.

FIG. 3 is a sectional structural view in the case of FIG. 2;

FIG. 4 is a layout diagram showing another example in which a storage node is short-circuited between a pair of memory cells.

FIG. 5 is a sectional structural view in the case of FIG. 4;

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a sectional structural view in the case of the second embodiment.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

FIG. 9 is a sectional structural view in the case of the third embodiment.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a configuration diagram before (A) and after (B) a miniaturization of a memory cell array.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Memory cell 11, 12 Dummy memory cell 20 Memory cell array 21 Storage electrode 22 Diffusion layer 23, 24 Contact part 25 Cell plate N1, N2 Storage node

Claims (3)

(57) [Claims] 1. A semiconductor memory device comprising: an equalizing circuit for short-circuiting a bit line pair of a memory cell array, wherein the equalizing circuit comprises a pair of predetermined two adjacent word lines and bit line pairs of the memory cell array. A pair of memory cells connected between the pair of memory cells, the storage node is short-circuited between the pair of memory cells, and an equalization control signal is applied to the two word lines. A semiconductor memory device characterized by the following. 2. A semiconductor memory device comprising a precharge circuit for precharging a bit line of a memory cell array, wherein the precharge circuit comprises two predetermined word lines and bit lines adjacent to each other in the memory cell array. A pair of memory cells connected between the pair of memory cells, a storage node and a cell plate of each of the pair of memory cells are short-circuited, and a precharge control signal is applied to the two word lines. Is applied. 3. A semiconductor memory device comprising: an equalizing circuit for short-circuiting a bit line pair of a memory cell array; and a precharge circuit for precharging a bit line, wherein the equalizing circuit comprises the equalizing circuit according to claim 1; 3. A semiconductor memory device, wherein the precharge circuit comprises the precharge circuit according to claim 2.