JP3206289B2 - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal insulated gate bipolar transistor (hereinafter, referred to as an IGBT) suitable for use in an integrated circuit device and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As is well known, IGBTs have the feature of having both the high input impedance of an insulated gate and the low output impedance of a bipolar transistor, and have very high frequency characteristics as a transistor for high voltage and large current. It has been widely adopted for applications that do not require it. Conventionally, this IGBT is usually used in the form of an individual element having a vertical structure. Recently, however, with the trend of so-called intelligence in power devices, a plurality of IGBTs are integrated with related control circuits into one. Increasing examples of integration into integrated circuit devices are increasing, and a IGBT is often of a horizontal structure because a so-called planar structure is advantageous for this integration.

The simplest way to make an IGBT a horizontal structure is to simply bring the backside structure of the chip in the conventional vertical structure to the front side, and FIG. 5 shows this conventional typical horizontal structure. The unit structure of the IGBT is shown in a sectional view. A chip or wafer for an integrated circuit is formed by, for example, growing an n-type epitaxial layer 2 on a p-type semiconductor substrate 1, for example, and an IGBT having a horizontal structure uses the epitaxial layer 2 as its semiconductor region. The unit structure U shown in the figure is repeatedly formed in the left and right direction a plurality of times.

[0004] The central part of the figure is the same as the vertical structure, and n
A p-type base layer 3 and a high impurity concentration base contact layer 4 are diffused from the surface of the semiconductor region 2 and a polycrystalline silicon gate 5 is formed on both peripheral portions of the base layer 3 through a thin gate oxide film 5a. And an n-type source layer 6 having a high impurity concentration is diffused under the insulated gate 5 as shown in the figure, and then the p-type base contact layer 4 and the n-type source layer 6 are diffused. The surface of 6 is short-circuited with an aluminum electrode film 9 to derive an emitter terminal E and a gate terminal G from an insulated gate 5.

The left and right end portions in FIG. 5 have a structure corresponding to the back side of the chip in the vertical structure. The same n-type buffer layer 7 as that from the surface of the semiconductor region 2 is diffused at a relatively high impurity concentration, and Then, a p-type collector layer 8 is diffused with a high impurity concentration, and an electrode film 9 conductively connected to the surface thereof is used as a collector terminal C. The collector layer 8 is usually formed by simultaneous diffusion with the base contact layer 4 having the same p-type and high impurity concentration.

In the horizontal IGBT shown in FIG. 5, a gate terminal G is applied while a voltage is applied between an emitter terminal E and a collector terminal C.
When a positive voltage is applied from the emitter terminal E to the surface of the p-type base layer 3 below the insulated gate 5, an n-type channel is formed, and electrons as majority carriers are transferred from the n-type source layer 6 to the semiconductor region 2. Flows through the buffer layer 7 to the collector layer 8. In response to this, holes as minority carriers are injected from the p-type collector layer 8 into the semiconductor region 2 through the buffer layer 7. As a result, a bipolar transistor comprising a p-type base layer 3, an n-type semiconductor region 2 and a p-type collector layer 8 is turned on, and the main terminals E and C are formed by the so-called conductivity modulation effect of electrons and holes in the semiconductor region 2. Are conducted with a very low ON voltage. When the IGBT is turned off, the gate terminal G is applied with the same voltage or a negative voltage as that of the emitter terminal E to cut off electrons flowing through the lower channel of the insulating gate 5. The buffer layer 7 is for controlling the amount of holes injected from the collector layer 8 into the semiconductor region 2.

[0007]

The above-mentioned lateral IGBT can have a high breakdown voltage by increasing the distance between the base layer 3 and the collector layer 8 and can have a large current by increasing the number of repetitions of the unit structure U. Latch-up, which is a drawback of IGBTs, is more likely to occur than vertical structures. FIG. 6 is an enlarged view of the right part of FIG.
And the movement path of the minority carrier hole h. The electrons e enter the semiconductor region 2 from the source layer 6 through the channel below the insulating gate 5, and flow from the buffer layer 7 to the collector layer 8 via a path along the surface. On the other hand, hall h
Is injected into the semiconductor region 2 from the collector layer 8 via the buffer layer 7 and contributes to conductivity modulation while passing through a range close to the surface as shown in FIG. And enters the base contact layer 4 via the lower side of the source layer 6.

As described above, in the IGBT having the horizontal structure, the holes h, which are minority carriers, flow in the base layer 3 under the source layer 6 in the lateral direction. 6 will be injected
P-type collector layer 8, n-type semiconductor region 2, and p-type base layer 3
The thyristor structure of four layers of pnpn existing between the gate and the n-type source layer 6 is ignited and latch-up easily occurs. Such injection of the holes h into the source layer 6 is particularly likely to occur when an excessive overvoltage is applied between the collector terminal C and the emitter terminal E during turning off of the IGBT or the like. The reason is that when the potential drop due to the hole h flowing in the base layer 3 in the lateral direction increases, the base layer 3 and the source layer 6 are short-circuited by the emitter terminal E. The potential at the point indicated by I rises, and the pn junction is forward biased at that point, and the hole h
Is easy to be injected. For this reason, the horizontal structure IGBT has a problem that the allowable current or the latch-up withstand capability that can flow through the IGBT significantly decreases compared to the conventional vertical structure.

An object of the present invention is to solve such a problem and improve the latch-up resistance of an IGBT having a horizontal structure.

[0010]

In the IGBT according to the present invention,
A semiconductor region of one conductivity type, a base layer of the other conductivity type diffused from the surface of the semiconductor region, a source layer of one conductivity type diffused to the surface in the base layer, An insulated gate buried in a recess dug from the surface through the base layer to reach the semiconductor region, and the other conductive diffused from the surface of the semiconductor region on the side opposite to the insulated gate of the source layer Shaped collector layer and base
Overlies the periphery of the layer and contacts the source layer
Is diffused to a higher impurity concentration than the source layer.
And a base contact layer of the conductivity type, the base contactee
The above object is achieved by deriving an emitter terminal from a gate layer and a source layer, a collector terminal from a collector layer, and a gate terminal from an insulated gate.

The recess comprises a groove, and insulating grooves are provided on both side walls of the groove.
A base layer, a source layer, and a base layer are formed on both sides of the groove.
It is assumed that the contact layer and the collector layer have been formed.
You.

Further, as a method of manufacturing an IGBT having such a lateral structure according to the present invention, a step of diffusing a base layer from a surface of a semiconductor region of one conductivity type with another conductivity type, a method of forming a source layer on a surface in the base layer, Diffusing with one conductivity type;
A step of digging a recess only from the inside surface of the source layer reaches the semiconductor region passes through the base layer, burying an insulation gate to the recess, opposite the insulated gate of the source layer
From the surface of the lateral semiconductor region, the collector layer is
Diffusion step. Further, it is advantageous that the base contact layer is diffused to the surface side of the base layer with the same other conductivity type so as to overlap the periphery thereof and contact the source layer at the same time as the step of diffusing the collector layer.

[0013]

In the conventional IGBT having the horizontal structure, the collector layer 8 is disposed on the same side as the insulating gate 5 with respect to the source layer 3 as shown in FIG. A collector layer is disposed on the side of the source layer opposite to the insulated gate, so that minority carriers that cause latch-up do not pass laterally through the base layer below the source layer as in the related art. By directly pulling out from the base layer or its contact layer to the emitter terminal, injection of minority carriers into the source layer is almost completely prevented, and the latch-up resistance is improved. In the embodiment in which the base contact layer for connecting the base layer to the emitter terminal is provided, almost all of the minority carriers are pulled out through only the base contact layer having the high impurity concentration and the low resistance, so that the effect of improving the latch-up resistance can be further enhanced. Can be.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the IGBT of the present invention, and FIG.
FIG. 3 shows a method of manufacturing an IGBT corresponding to the embodiment of FIG.
4 and 4 show different embodiments of the present invention. FIG.
(a) is a sectional view showing a unit structure U of the horizontal IGBT according to the present invention corresponding to the above-mentioned FIG. 5, and shows a chip or wafer for an integrated circuit in which the IGBT is manufactured in the same manner as in the conventional case.
For example, an n-type epitaxial layer 12 is grown at a predetermined impurity concentration on a p-type semiconductor substrate 11, for example. The IGBT of the present invention uses the epitaxial layer 12 as a semiconductor region for the unit structure U in the figure. Are usually repeated several tens of times and connected in parallel.

The emitter side shown in the center of the figure is a characteristic portion of the lateral IGBT of the present invention. The p-type base layer 22 is diffused slightly deeper from the surface of the n-type semiconductor region 12 described above. And an n-type source layer on the inner surface of the base layer 22.
After shallow diffusion of 23 with high impurity concentration, trench-shaped recess
24 is dug from the central surface of the source layer 23 through the base layer 22 to reach the semiconductor region 12 therebelow.
24 is filled with, for example, polycrystalline silicon insulated by a very thin gate oxide film 25a to form an insulated gate 25. In the example shown in the figure, a p-type is formed so as to overlap with the periphery of the base layer 22 and to be in contact with the source layer 23. Base contact layer 27
At a high impurity concentration. Base layer 22 and source layer
An electrode film 31 for leading the emitter terminal E from 23 is provided so as to short-circuit the surfaces of the source layer 23 and the base contact layer 27. Further, a gate terminal G is derived from the insulated gate 25.

The collector side shown on the left and right portions of the drawing has the same structure as the conventional one, and the same n-type buffer layer 21 is diffused from the surface of the semiconductor region 12 with a relatively high impurity concentration, and the p-type Of the collector layer 26 is diffused with a high impurity concentration and the collector terminal C is derived from the electrode film 32 conductively connected to the collector layer 26. In the conventional structure shown in FIGS. In contrast to the arrangement of the collector layer 8, in the present invention, the collector layer 26 is used as an insulated gate of the source layer 22.
The difference is that it is located on the opposite side to 25.

FIG. 1B shows a moving path of the majority carrier or the electron e and the minority carrier or the hole h in the ON state of the IGBT of the present invention configured as described above, in a manner corresponding to FIG. In the IGBT of the present invention, since the insulated gate 25 is of a buried type, a channel is formed on the side of the recess 24 of the base layer 22 in contact with the gate oxide film 25a, and electrons e pass through the channel from the source layer 23 to the semiconductor. After flowing into the lower portion of the base layer 22 in the region 12, it flows into the collector layer 26 via the buffer layer 21 via an oblique flow path indicated by Pe in the figure. The holes h generated from the contact layer 26 due to the inflow of the electrons e are injected into the semiconductor region 12 through the buffer layer 21, and then a part of the holes h act between the electrons e as shown in FIG. After flowing through the internal flow path Ph1 and the other part through the surface flow path Ph2, the base layer 22, the contact layer 27 in the example of the drawing, is drawn into the electrode film 31 on the surface. It is to be noted that the conductivity modulation between the hole h and the electron e occurs in the on state as in the conventional case.

In the present invention, since the collector layer 26 is provided on the opposite side of the source layer 22 from the insulated gate 25 as described above, FIG.
As can be seen from (b), the location where the hole h is drawn is on the same side as the collector layer 26 with respect to the source layer 23. Accordingly, in the present invention, the holes h may pass through the base layer 22 below the source layer 23 in the lateral direction and be injected into the source layer 23 due to the forward bias of the pn junction between the two layers, as shown in FIG. And the latch-up resistance can be improved. In particular, in the embodiment in which the base contact layer 27 having a high impurity concentration is provided as shown in the figure, since the specific resistance is much lower than that of the base layer 22, the possibility that holes h are injected due to the forward bias of the pn junction is further reduced. Thus, the effect of improving the latch-up resistance can be further enhanced.

When the IGBT is turned off, the electrons e and holes h remaining in the semiconductor region 2 are swept out to expand the depletion layer. Since the Coulomb force on the hole h decreases sharply, most of the hole h is covered by the aforementioned surface flow channel Ph.
Pulled out via 2 Therefore, in the present invention, the possibility of holes h being injected into the source layer 23 at the time of turning off can be further reduced than at the time of turning on, so that the latch-up resistance of the horizontal IGBT can be increased. As described above, in the IGBT having the horizontal structure according to the present invention, the latch-up withstand capability can be several times higher than that of the conventional IGBT when it is turned on, and can be increased by about one digit when it is turned off. Further, in the IGBT of the present invention, the turn-off time can be reduced as compared with the conventional case. That is, the turn-off characteristic is substantially determined by the time for sweeping out the hole h having a lower mobility than the electron e. However, the drift time becomes shorter as the hole h is pulled closer to the collector layer 26 than before, and the withstand voltage of the IGBT is reduced. The turn-off time can be reduced by 20-30%, depending on the application.

Next, a method of manufacturing the IGBT of the present invention will be described with reference to FIG. Figure 2 (a) shows the base layer
22 shows the diffusion process. In the figure, only an n-type semiconductor region 12 which is an epitaxial layer is shown in a wafer 10, and an IGBT
When the breakdown voltage of the semiconductor region 12 is about 300 V, the semiconductor region 12 has a specific resistance of about 40 Ωcm and a thickness of at least 10 μm to several tens μm. In the example of the figure, first, an n-type buffer layer 21 for the collector layer is
After diffusion to a depth of 4 μm at an impurity concentration of ¹⁷ atoms / cm ³ , the p-type base layer 22 is diffused to a depth of ³ to 4 μm at an impurity concentration of, for example, 10 ¹⁷ atoms / cm ³ . Either method may be performed by ion implantation and thermal diffusion of impurities using a photoresist as a mask.

In the step of FIG. 2B, the source layer 23 is diffused in an n-type. The diffusion pattern is smaller than the base layer 22 as shown in the figure.
By diffusing to a depth of about 0.1 μm with a high impurity concentration of 10 ¹⁹ atoms / cm ³ , this is formed on the inner surface of the base layer 22. FIG. 2C shows a process of excavating the recess 24. The reactive ion etching method is advantageous for digging the trench-shaped recess 24 as shown in the figure. First, a low-temperature oxide film having a thickness of 1 to 1.5 μm is applied as a mask M to the digging portion of the recess 24. After opening the window with a width of, for example, 3 μm, 10 Pa of an etching gas obtained by mixing silicon tetrachloride and nitrogen is used.
By performing reactive ion etching for about 30 minutes in an atmosphere of about 4 to 6 μm so that the recess 24 passes through the base layer 22 from the surface of the central portion of the source layer 23 to reach the lower semiconductor region 12. Dig into the depth of. This figure 2
After step (c), the mask M is removed.

FIG. 2D shows a gate oxide film for the insulating gate 25.
This is the step of coating 25a and growing polycrystalline silicon. First, the gate oxide film 25 is thinly formed to a thickness of about 0.1 μm on the surface including the recess 24 by a usual thermal oxidation method,
Polycrystalline silicon doped with impurities for the insulating gate 25 is grown to a thickness of, for example, 2 μm by the method to completely fill the recess 24. FIG. 2 (e) shows a step of removing unnecessary portions of polycrystalline silicon. The unnecessary portions of polycrystalline silicon are removed by dry etching using a photoresist as a mask, and then gate oxidation is performed by simple wet etching with a fluorine solution. By removing unnecessary portions of the film 25a, the insulating gate 25 is formed, for example, in a sectional shape as shown in the figure.

In this embodiment, the same p-type base contact layer 27 is diffused simultaneously with the collector layer 26 in the next step of FIG. 2 (f). As shown, the collector layer 26 has a high impurity concentration of about 10 ¹⁸ atoms / cm ^{3 in the} buffer layer 21, and the base contact layer 27 has a high impurity concentration of about 10 ¹⁸ atoms / cm ³ so as to overlap the periphery of the base layer 22 and contact the source layer 23. For example, it diffuses to a depth of 1 to 1.5 μm. This completes the semiconductor layer diffusion step. To change the state of FIG. 2 (f) to the completed state of FIG. 1, cover the surface of the wafer 10 with an interlayer insulating film or the like and open a window at a key point. Opening, aluminum electrode films 31 and 32 are provided for the emitter terminal E and the collector terminal C, respectively, and an electrode film for the gate terminal G is provided at a place other than the illustrated cross section of the insulated gate 25,
Further, it may be covered with a conventional protective film.

Next, a preferred embodiment of the IGBT of the present invention will be described with reference to a partially enlarged top view shown in FIG. The vertical direction in FIG. 3 is the horizontal direction in FIG. 1, and for convenience of illustration, FIG. 3 shows a state in which the central portion in the horizontal direction is omitted and the electrode films 31 and 32 are removed from FIG. . The insulated gate 25 has a buried portion in the recess 24 in the left-right direction of the figure, which is like a comb tooth, and the comb teeth are interconnected by the polycrystalline silicon of the insulation gate 25 covering the left surface of the figure. The gate terminal G has a comb-like structure derived from the connecting portion. The collector layer 26 is also diffused into a pattern in which the p-shaped comb teeth elongated in the left-right direction are connected by an auxiliary collector layer 26a.
Since a is originally p-type as shown by (p) in the figure, the collector layer 26 and the insulated gate 25 have a comb-like structure in which they are intricate with each other.

The surface of the semiconductor region 12 interposed between the insulated gate 25 and the collector layer 26, the buffer layer 21, the source layer 23, and the base contact layer 27 have a bent meandering pattern. As described above, the emitter terminal E is derived from the source layer 23 and the base contact layer 27, and the collector terminal C is derived from the collector layer 26. However, since holes h are concentrated near the tip of the pattern of the source layer 23 from the collector layer 26 surrounding it as shown by the arrow in the figure, the tip is most likely to cause latch-up due to the injection of the holes h. It becomes a place. In the embodiment shown in FIG. 3, noting this point, an n-type auxiliary collector layer 26a instead of a p-type auxiliary collector layer 26a as shown in FIG.
The surface of the collector layer 26 is diffused with the electrode film 32 of FIG.
To short-circuit the collector terminal C. As a result, the portion where the n-type auxiliary collector layer 26a, which is the same as the source layer 23, is diffused becomes a field-effect transistor free from latch-up, so that the latch-up capability of the IGBT can be reduced by the n-type auxiliary collector layer.
This can be further improved over the embodiment of FIG. 1 without 26a. As described above, the auxiliary collector layer 26a may be p-type, but is more preferably n-type.

In the embodiment shown in FIG. 4 in a cross section corresponding to FIG. 1 (a), the emitter side at the center of the figure is the same as the embodiment of FIG. 1, but the n-type auxiliary collector layer 26b is provided on the collector side. To p
In contact with the collector layer 26 in the form shown in the figure, it is diffused so as to be surrounded by the collector layer 26, and the surface of the collector layer 26 is short-circuited with the electrode film 32 to form a collector terminal C. Auxiliary collector layer
26b may be diffused simultaneously with the source layer 23, for example. In this embodiment, since a considerable amount of electrons e flow toward the auxiliary collector layer 26b, the on-voltage of the IGBT slightly increases, but the hole h increases.
Can be reduced to improve the latch-up resistance.

[0027]

As described above, in the IGBT having the lateral structure according to the present invention, the semiconductor region of one conductivity type, the base layer of the other conductivity type diffused from the surface of the semiconductor region, and the semiconductor layer in the base layer. A source layer of one conductivity type diffused into the surface, an insulated gate buried in a recess dug from the surface of the source layer through the base layer to the semiconductor region, and an insulated gate of the source layer. Is the collector layer of the other conductivity type diffused from the surface of the semiconductor region on the opposite side overlapped with the peripheral edge on the surface side of the base layer?
Is diffused in contact with the source layer and is higher than the source layer.
And a base contact layer of the other conductivity type with a pure concentration.
In addition , since the emitter terminal is derived from the base contact layer and the source layer, the collector terminal is derived from the collector layer, and the gate terminal is derived from the insulated gate, the following effects can be obtained.

(A) By burying the insulated gate in the recess, a collector layer can be provided on the side of the source layer opposite to the insulated gate, and a contact layer having a high impurity concentration and a low resistance is provided for the base layer. The minority carriers that cause the erroneous carriers do not pass laterally below the source layer as in the conventional structure in which the collector layer is disposed on the same side of the source layer as the insulated gate. By directly extracting the minority carriers, the injection of minority carriers into the source layer can be almost completely prevented, and the latch-up resistance can be improved.

(B) After the supply of electrons to the semiconductor region is stopped when the IGBT is turned off, the Coulomb force acting on the hole decreases, and most of the hole is pulled out via a flow path near the surface of the semiconductor region. The risk of holes being injected into the source layer
Can increase the latch-up withstand capability at the time of turn-off.

(C) Since the collector layer is disposed on the side of the source layer opposite to the insulated gate, and the hole extraction point is on the same side as the collector layer with respect to the source layer, that is, closer to the collector layer than in the conventional case, it is more mobile than electrons The drift time in the semiconductor region during the turn-off of the IGBT with a low degree of hole is shortened,
By sweeping holes out of the semiconductor region and expanding the depletion layer in a short time, the turn-off time of the IGBT can be reduced and the applicable frequency can be increased.

Note that the horizontal IG having such features of the present invention is provided.
BT is suitable for incorporation into an integrated circuit device, and can provide a high withstand voltage of several hundred volts and a current capacity of 1 A or more as necessary in addition to the excellent latch-up withstand capability and turn-off characteristics described above.

[Brief description of the drawings]

FIGS. 1A and 1B show an embodiment of an IGBT according to the present invention, wherein FIG. 1A is a cross-sectional view of a unit structure thereof, and FIG. 1B is a main view of FIG. It is a part enlarged sectional view.

FIGS. 2A and 2B show a method of manufacturing an IGBT according to the embodiment of FIG. 1 in a state of each main step, and FIG. 2A shows a diffusion step of a base layer and the like;
FIG. 3 (b) shows a source layer diffusion process, FIG. 4 (c) shows a recess digging process, FIG. 4 (d) shows a growth process of polycrystalline silicon or the like for an insulated gate, and FIG. Gate formation process, same figure
(f) shows the state during the diffusion process of the collector layer etc.
FIG. 2 is an enlarged sectional view of a main part of the IGBT.

FIG. 3 is an enlarged top view of a main part of an IGBT showing a different embodiment of the present invention together with a planar pattern of the IGBT according to the embodiment of FIG. 1;

FIG. 4 is a sectional view of a unit structure of an IGBT showing still another embodiment of the present invention.

FIG. 5 is a sectional view of a unit structure of a conventional horizontal IGBT.

FIG. 6 is an enlarged sectional view of a main part showing a flow of electrons and holes inside the IGBT of FIG. 5;

[Explanation of symbols]

 10 IGBT chip or its wafer 12 Semiconductor region or epitaxial layer 21 Buffer layer 22 Base layer 23 Source layer 24 Depression 25 Insulated gate 25a Gate oxide film 26 Collector layer 26a Auxiliary collector layer 26b Auxiliary collector layer 27 Base contact layer C Collector terminal E Emitter terminal e Electron or majority carrier G Gate terminal h Hole or minority carrier Pe Electron flow path Ph1 Internal flow path of hole Ph2 Surface flow path of hole

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (4)

(57) [Claims] A semiconductor region of one conductivity type, a base layer of another conductivity type diffused from a surface of the semiconductor region,
A source layer of one conductivity type diffused into its surface in the base layer, an insulated gate buried in a recess dug from the surface of the source layer through the base layer to reach the semiconductor region, A collector layer of the other conductivity type diffused from the surface of the semiconductor region on the side opposite to the insulated gate of the layer ;
Higher impurity than source layer diffused in contact with source layer
And a base contact layer of the other conductivity type concentration, base
An insulated gate bipolar transistor wherein an emitter terminal is derived from a source contact layer and a source layer, a collector terminal is derived from a collector layer, and a gate terminal is derived from an insulated gate. 2. The recess comprises a groove, and insulating grooves are provided on both side walls of the groove.
A base layer, a source layer, and a base layer are formed on both sides of the groove.
2. The insulated gate bipolar transistor according to claim 1 , wherein a contact layer and a collector layer are formed . 3. A base from the surface of a semiconductor region of one conductivity type.
Diffusing the base layer with the other conductivity type, and
Diffusing the source layer in one conductivity type on the surface of the
Through the base layer only from inside the surface of the base layer to the semiconductor region
The process of digging a recess that reaches
Embedding process and the side of the source layer opposite to the insulated gate
From the surface of the other semiconductor region with the other conductivity type
Diffusion step.
A method for manufacturing a polar transistor. 4. A base from the surface of a semiconductor region of one conductivity type.
Diffusing the base layer with the other conductivity type, and
Diffusing the source layer in one conductivity type on the surface of the
From the surface of the base layer to the semiconductor region through the base layer
Digging a place and embedding an insulated gate in this recess
Process and semi-conductor on the side of the source layer opposite the insulated gate
Diffuses the collector layer from the surface of the body region with the other conductivity type
Process and surface of base layer between collector layer and insulated gate
Side partially overlaps its periphery and touches the source layer
To diffuse the base contact layer of the other conductivity type
And a step of diffusing the collector layer.
And the step of diffusing the target layer is performed simultaneously.
A method for manufacturing an insulated gate bipolar transistor.