JP3204449B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3204449B2 JP3204449B2 JP25856897A JP25856897A JP3204449B2 JP 3204449 B2 JP3204449 B2 JP 3204449B2 JP 25856897 A JP25856897 A JP 25856897A JP 25856897 A JP25856897 A JP 25856897A JP 3204449 B2 JP3204449 B2 JP 3204449B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- insulating layer
- semiconductor device
- conductive
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000002955 isolation Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】この発明は半導体装置に関
し、特に、絶縁層を介した２つの導電層間の電気的容量
の増大に関するものである。
【０００２】
【従来の技術】図２は従来の半導体装置を図解する概略
的な断面図である。この図において、シリコン基板１上
にはシリコン酸化物からなる第１の絶縁層３が形成され
ており、第１の絶縁層３はシリコン酸化物からなる素子
分離領域２によって囲まれている。第１の絶縁層３上に
は、フォトレジストマスクを用いる化学的食刻法によっ
て、多結晶シリコンからなる第１の導電層４が形成され
ており、この第１の導電層４は分離領域２上の一部にま
で広がっている。第１の導電層４上にはその多結晶シリ
コンを熱酸化して得られるシリコン酸化物からなる第２
の絶縁層５が重ねられており、この第２の絶縁層５は第
２の導電層６によって覆われている。
【０００３】このような半導体装置において、第１の導
電層４は第２の絶縁層５を介して第２の導電層６と対向
しているので、これらの導電層は電気容量として働くこ
とができる。この場合に、その電気容量は第２の絶縁層
５の膜厚に依存し、また第１の導電層４と第２の導電層
６が第２の絶縁層５を介して重なる部分の面積に依存す
る。ところで、分離領域２によって分離された隣り合う
素子領域から延びている２つの第１の導電層４の間の食
刻幅はフォトレジストマスクの加工精度に依存し、また
化学的食刻時におけるフォトレジストマスク下への過剰
食刻後退量に依存する。現在の技術では、この食刻幅は
最小で約１．０μｍになっている。
【０００４】
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、第１の導電層４と第２
の導電層６との間の電気容量を増大させるためには、第
２の絶縁層５を薄くするか、または第２の絶縁層５を介
するこれら２つの導電層４と６の重なり部分の面積を広
げなければならない。しかし、第２の絶縁層５を薄くす
れば、第１の導電層４と第２の導電層６との間の絶縁性
が低下し、装置の信頼性が低下する。また、２つの導電
層４と６の重なり部分の面積を広げようとすれば、装置
の平面積を増大させる結果となり、装置の微細化を損な
う。
【０００５】本発明はこのような問題点を解消するため
になされたもので、第２の絶縁層５の絶縁性を低下させ
ることなく、かつ装置の面積的な大きさを増大させるこ
となく２つの導電層４と６の間の電気容量が増大された
半導体装置を提供することを目的としている。
【０００６】
【課題を解決するための手段】本発明による半導体装置
は、半導体基板の表面を複数の素子領域に分離するため
の絶縁体分離領域と、各素子領域の表面に形成された第
１の絶縁層と、各素子領域の両端の前記絶縁体分離領域
上に形成された溝と、第１の絶縁層を覆いかつ前記絶縁
体分離領域の一部を覆う第１の導電層と、溝の側壁部を
覆いかつその溝の上部に比べて下部の方が厚い、第１の
導電層に接続している第２の導電層と、第１および第２
の導電層上を覆う第２の絶縁層と、第２の絶縁層を覆う
第３の導電層とを備えていることを特徴としている。
【０００７】すなわち、この半導体装置は、絶縁体分離
領域上に形成された溝の側壁部を覆いかつその溝の上部
に比べて下部の方が厚い、第１の導電層に接続された第
２の導電層と、これらの第１および第２の導電層を覆う
第２の絶縁層と、この第２の絶縁層を覆う第３の導電層
とを備えている。したがって、第１および第２の導電層
と第３の導電層とは、半導体装置の平面的な大きさを増
大させることなく互いに重なり合う面積を増大させるこ
とができ、電気容量を増大させることができる。さら
に、第２の導電層の特徴的な形状により、溝上部の角部
での第１および第２の導電層と第３の導電層との間の電
界集中が緩和され、第２の絶縁層の絶縁性が優れたもの
となる。
【０００８】
【発明の実施の形態】図１は本発明の実施の形態の一例
による半導体装置を図解する概略的な断面図である。こ
の図において、シリコン基板１上にはシリコン酸化物か
らなる第１の絶縁層３が形成されており、この絶縁層３
はシリコン酸化物からなる素子分離領域２によって囲ま
れている。
【０００９】第１の絶縁層３上には多結晶シリコンから
なる第１の導電層７が形成され、これは分離領域２上の
一部にまで延びている。このような第１の導電層７は、
第１の絶縁層３と分離領域２の上に形成された多結晶シ
リコン膜の表面を熱酸化した後に、フォトレジストマス
クを用いて選択的に化学的食刻をすることによって得ら
れる。分離領域２上には溝８が形成されている。この溝
８は、第１の導電層７を選択的に化学食刻した後に、そ
のフォトレジストマスクを除去せずにそのまま素子分離
領域２を選択的な異方性化学的食刻することによって形
成することができる。この溝８のほぼ垂直な壁に沿っ
て、第１の導電層７に繋がる第２の導電層９が形成され
る。このような第２の導電層９は、溝８の表面と第１導
電層７上のシリコン酸化物とを覆って多結晶シリコン膜
を堆積させ、そしてフォトレジストを用いないで全面的
に異方性化学食刻を行なうことによって形成することが
できる。こうして第１の導電層７とその両端部のそれぞ
れに第２導電層９が形成された後に、第１導電層７上の
シリコン酸化物の膜を除去し、その後に第１導電層７と
第２導電層９を同時に熱酸化することによって、第１と
第２の導電層７，９の表面にシリコン酸化物からなる第
２の絶縁層１０が形成される。この第２絶縁層１０は、
第３の導電層１１によって覆われる。
【００１０】このように形成される装置において、分離
領域２の厚さを１．０μｍとし、溝８の深さを０．２５
μｍとし、第１と第２の導電層７，９の膜厚を０．３μ
ｍとし、第２絶縁層１０の厚さを０．０５μｍとし、第
１導電層７の水平長さを３μｍとし、第１と第２の導電
層７，９の図１における奥行方向の幅が一定であるとす
れば、第１および第２の導電層７，９と第３導電層１１
とが第２絶縁層１０を介して重なる部分の面積は従来装
置に比べて約１３％だけ増大する。この重なり部分の面
積の増大はそのまま第１および第２の導電層７，９と第
３導電層１１との間の電気容量の増大となる。また、分
離領域２をさらに厚くして溝８をさらに深く形成するこ
とによって、装置の平面的な面積を増大させることなく
第１および第２の導電層７，９と第３導電層１１との間
の電気容量をさらに増大させることができる。また、上
述の実施の形態の寸法例による構造では、分離領域上で
隣り合う第１導電層７同士の間の化学食刻幅が約１．０
μｍでも十分に第２導電層９を形成することができ、か
つ第３導電層１１は断線を生じることなく形成すること
ができる。また、図１に示すように、第２導電層９の形
状は溝８の上部に比べて下部の方が厚いので、図２の従
来のものに比べて、溝上部の角部での第１および第２の
導電層と第３の導電層との間の電界集中が緩和され、第
２の絶縁層の絶縁性が優れたものとなる。
【００１１】なお、上述の実施の形態では、既に形成さ
れた分離領域２内に化学食刻で溝８を形成する例を示し
たが、シリコン基板１を化学食刻して溝８を形成し、そ
の後にその溝から酸化させて分離領域としてもよいこと
が理解されよう。
【００１２】また、多結晶シリコン膜を堆積させてその
表面を熱酸化した後にフォトレジストマスクを用いた選
択的化学食刻により第１導電層７を形成したが、この熱
酸化に代えて化学気相成長法によるシリコン酸化物の膜
またはシリコン窒化物の膜を形成してもよいことが理解
されよう。さらに、多結晶シリコン膜を異方性化学食刻
することによって第２導電層９を形成する際に、この食
刻を精度よく行なえば、前述の第１導電層７上のシリコ
ン酸化物またはシリコン窒化物の膜を省略することがで
きる。
【００１３】
【発明の効果】以上のように、本発明によれば、絶縁体
分離領域上に形成された溝の側壁部を覆いかつその溝の
上部に比べて下部の方が厚い、第１の導電層に接続され
た第２の導電層と、第１および第２の導電層上を覆う第
２の絶縁層と、第２の絶縁層を覆う第３の導電層とを備
えているので、第１および第２の導電層と第３の導電層
とは、半導体装置の平面的な大きさを増大させることな
く互いに重なり合う面積を増大させることができ、電気
容量を増大させることができる。 さらに、第２の導電層
の特徴的形状により、溝上部の角部での第１および第２
の導電層と第３の導電層との間の電界集中が緩和され、
第２の絶縁層の絶縁性が優れたものとなる。 Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to an increase in electric capacitance between two conductive layers via an insulating layer. 2. Description of the Related Art FIG. 2 is a schematic sectional view illustrating a conventional semiconductor device. In this figure, a first insulating layer 3 made of silicon oxide is formed on a silicon substrate 1, and the first insulating layer 3 is surrounded by an element isolation region 2 made of silicon oxide. A first conductive layer 4 made of polycrystalline silicon is formed on the first insulating layer 3 by a chemical etching method using a photoresist mask. It extends to the upper part. On the first conductive layer 4, a second layer made of silicon oxide obtained by thermally oxidizing the polycrystalline silicon is formed.
The second insulating layer 5 is covered with a second conductive layer 6. In such a semiconductor device, the first conductive layer 4 faces the second conductive layer 6 with the second insulating layer 5 interposed therebetween, so that these conductive layers may function as electric capacitance. it can. In this case, the electric capacity depends on the film thickness of the second insulating layer 5, and the area of the portion where the first conductive layer 4 and the second conductive layer 6 overlap with the second insulating layer 5 interposed therebetween. Dependent. By the way, the etching width between two first conductive layers 4 extending from adjacent element regions separated by the separation region 2 depends on the processing accuracy of the photoresist mask, and the photolithography at the time of chemical etching. Depends on the amount of excessive etching retreat under the resist mask. With current technology, this etching width is at least about 1.0 μm. Since the conventional semiconductor device is configured as described above, the first conductive layer 4 and the second conductive layer
In order to increase the electric capacitance between the first conductive layer 6 and the second conductive layer 6, the second insulating layer 5 is made thinner or the area of the overlapping portion of the two conductive layers 4 and 6 with the second insulating layer 5 interposed therebetween. Must be spread out. However, if the thickness of the second insulating layer 5 is reduced, the insulation between the first conductive layer 4 and the second conductive layer 6 is reduced, and the reliability of the device is reduced. Further, if the area of the overlapping portion between the two conductive layers 4 and 6 is increased, the plane area of the device is increased, and the miniaturization of the device is impaired. The present invention has been made to solve such a problem, and has been made without reducing the insulating property of the second insulating layer 5 and without increasing the area of the device. It is an object of the present invention to provide a semiconductor device in which the capacitance between two conductive layers 4 and 6 is increased. [0006] The semiconductor device according to the present invention SUMMARY OF THE INVENTION comprises a dielectric isolation region for isolating the surface of the semiconductor substrate into a plurality of elementary sub area, formed on the surface of the element regions A first insulating layer, grooves formed on the insulator isolation regions at both ends of each element region, a first conductive layer covering the first insulation layer and partially covering the insulator isolation region, And the side wall of the groove
A second conductive layer connected to the first conductive layer, the second conductive layer being covered and having a lower portion thicker than an upper portion of the groove;
And a third conductive layer that covers the second insulating layer. In other words, this semiconductor device covers the side wall of the groove formed on the insulator isolation region and has the upper part of the groove.
The lower portion is thicker than the first portion, which is connected to the first conductive layer.
2 conductive layers and covers these first and second conductive layers
A second insulating layer, and a third conductive layer covering the second insulating layer
And Therefore, the first and second conductive layer and the third conductive layer, it is possible to increase the area of overlap with each other without increasing the planar size of the semiconductor device, to increase the electrical capacity it can. Further
In addition, due to the characteristic shape of the second conductive layer, the corner at the top of the groove is formed.
Between the first and second conductive layers and the third conductive layer at
With reduced field concentration and excellent insulation of the second insulating layer
Becomes FIG. 1 is a schematic sectional view illustrating a semiconductor device according to an embodiment of the present invention. In this figure, a first insulating layer 3 made of silicon oxide is formed on a silicon substrate 1.
Are surrounded by an element isolation region 2 made of silicon oxide. [0009] On the first insulating layer 3 first conductive layer 7 of polycrystalline silicon is formed, this is extends to the part of the isolation region 2. Such a first conductive layer 7
It is obtained by thermally oxidizing the surface of the polycrystalline silicon film formed on the first insulating layer 3 and the isolation region 2 and then selectively performing chemical etching using a photoresist mask. A groove 8 is formed on the isolation region 2. The trench 8 is formed by selectively chemically etching the first conductive layer 7 and then selectively anisotropically etching the element isolation region 2 without removing the photoresist mask. can do. Along the substantially vertical wall of the groove 8, a second conductive layer 9 connected to the first conductive layer 7 is formed. Such a second conductive layer 9 covers the surface of the groove 8 and the silicon oxide on the first conductive layer 7 to deposit a polycrystalline silicon film, and is entirely anisotropic without using a photoresist. It can be formed by performing chemical etching. After the first conductive layer 7 and the second conductive layers 9 are formed on both ends thereof in this manner, the silicon oxide film on the first conductive layer 7 is removed.
By simultaneously thermally oxidized second conductive layer 9, the first and
A second insulating layer made of silicon oxide is formed on the surfaces of second conductive layers and. This second insulating layer 10
Covered by the third conductive layer 11. In the device formed as described above, the thickness of the isolation region 2 is set to 1.0 μm, and the depth of the groove 8 is set to 0.25 μm.
μm, and the thickness of the first and second conductive layers 7 and 9 is 0.3 μm.
m, the thickness of the second insulating layer 10 is 0.05 μm, the horizontal length of the first conductive layer 7 is 3 μm, and the width of the first and second conductive layers 7 and 9 in the depth direction in FIG. If it is constant, the first and second conductive layers 7 and 9 and the third conductive layer 11
The area of the portion that overlaps with the second insulating layer 10 increases by about 13% as compared with the conventional device. The increase in the area of the overlapping portion directly increases the electric capacity between the first and second conductive layers 7, 9 and the third conductive layer 11. Further, by making the isolation region 2 thicker and forming the groove 8 deeper, the first and second conductive layers 7 and 9 and the third conductive layer 11 can be connected without increasing the planar area of the device. The electric capacity between them can be further increased. In the structure according to the dimension example of the above-described embodiment, the chemical etching width between the first conductive layers 7 adjacent to each other on the separation region is about 1.0.
The second conductive layer 9 can be sufficiently formed even with a thickness of μm, and the third conductive layer 11 can be formed without disconnection. In addition, as shown in FIG.
Since the lower part is thicker than the upper part of the groove 8,
First and second at the corner at the top of the groove compared to the conventional one
Electric field concentration between the conductive layer and the third conductive layer is reduced,
The insulating property of the second insulating layer is excellent. In the above-described embodiment, an example has been shown in which the trench 8 is formed by chemical etching in the isolation region 2 already formed. However, the trench 8 is formed by chemically etching the silicon substrate 1. It will be understood that the trench may then be oxidized from the trench to form an isolation region. After the polycrystalline silicon film is deposited and its surface is thermally oxidized, the first conductive layer 7 is formed by selective chemical etching using a photoresist mask. It will be understood that a silicon oxide film or a silicon nitride film may be formed by a phase growth method. Further, when the second conductive layer 9 is formed by performing anisotropic chemical etching of the polycrystalline silicon film, if the etching is performed accurately, the silicon oxide or silicon on the first conductive layer 7 can be formed. The nitride film can be omitted. As described above, according to the present invention, the side wall of the groove formed on the insulator isolation region is covered and the groove is formed.
The lower part is thicker than the upper part and is connected to the first conductive layer.
A second conductive layer formed on the first and second conductive layers;
A second insulating layer and a third conductive layer covering the second insulating layer.
The first and second conductive layers and the third conductive layer
This does not mean increasing the planar size of the semiconductor device.
The area that overlaps each other can be increased,
The capacity can be increased. Further, the second conductive layer
1 and 2 at the corner at the top of the groove
Electric field concentration between the conductive layer and the third conductive layer is reduced,
The insulating property of the second insulating layer becomes excellent.
【図面の簡単な説明】
【図１】 本発明の実施の形態の一例による半導体装置
を図解する概略的な断面図である。
【図２】 従来の半導体装置を示す断面図である。
【符号の説明】
１ シリコン基板、２ シリコン酸化物からなる分離領
域、３ シリコン酸化物からなる第１の絶縁層、４ 多
結晶シリコンからなる第１の導電層、５ シリコン酸化
物からなる第２の絶縁層、６ 第２の導電層、７ 多結
晶シリコンからなる第１の導電層、８ 溝、９ 多結晶
シリコンからなる第２の導電層、１０シリコン酸化物か
らなる第２の絶縁層、１１ 第３の導電層。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an example of an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 Silicon substrate, 2 Isolation region composed of silicon oxide, 3 First insulating layer composed of silicon oxide, 4 First conductive layer composed of polycrystalline silicon, 5 Second composed of silicon oxide 6, a second conductive layer, 7 a first conductive layer made of polycrystalline silicon, 8 grooves, 9 a second conductive layer made of polycrystalline silicon, a second insulating layer made of silicon oxide, 11 Third conductive layer.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭61−140168（ＪＰ，Ａ) 特開 昭60−225461（ＪＰ，Ａ) 特開 昭62−36870（ＪＰ，Ａ) 特開 昭62−52972（ＪＰ，Ａ) 特開 昭61−88554（ＪＰ，Ａ) 特開 昭60−68647（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/00 - 27/26 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-61-140168 (JP, A) JP-A-60-225461 (JP, A) JP-A-62-36870 (JP, A) JP-A-62 52972 (JP, A) JP-A-61-88554 (JP, A) JP-A-60-68647 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 27/00-27 / 26
Claims (1)
の絶縁体分離領域と、 各前記素子領域の表面に形成された第１の絶縁層と、 各前記素子領域の両端の前記絶縁体分離領域上に形成さ
れた溝と、 前記第１の絶縁層を覆いかつ前記絶縁体分離領域の一部
を覆う第１の導電層と、前記溝の側壁部を覆いかつその溝の上部に比べて下部の
方が厚い、 前記第１の導電層に接続している第２の導電
層と、 前記第１および第２の導電層上を覆う第２の絶縁層と、 前記第２の絶縁層を覆う第３の導電層とを備えているこ
とを特徴とする半導体装置。 ２．前記第１と第２の導電層は多結晶シリコンであり、
前記第２の絶縁層はシリコン酸化物であることを特徴と
する請求項１に記載の半導体装置。 ３．前記基板はシリコンであり、前記第１の絶縁層はシ
リコン酸化物であることを特徴とする請求項１または２
に記載の半導体装置。 ４．前記絶縁体分離領域はシリコン酸化物であることを
特徴とする請求項１から３のいずれかの項に記載の半導
体装置。 ５．前記半導体装置はメモリ装置であることを特徴とす
る請求項１から４のいずれかの項に記載の半導体装置。(57) [Claims] A semiconductor substrate, said semiconductor substrate surface a plurality of elementary sub area insulator isolation region for isolating the a, a first insulating layer formed on the surface of each of the device region, both ends of each device region A groove formed on the insulator isolation region, a first conductive layer covering the first insulation layer and partially covering the insulator isolation region, and a groove covering the side wall of the groove and forming the groove. At the bottom compared to the top
A second conductive layer connected to the first conductive layer, a second insulating layer covering the first and second conductive layers, and a second insulating layer covering the second insulating layer. 3. A semiconductor device, comprising: 2. The first and second conductive layers are polycrystalline silicon;
The semiconductor device according to claim 1, wherein the second insulating layer is a silicon oxide. 3. 3. The method according to claim 1, wherein the substrate is silicon, and the first insulating layer is silicon oxide.
3. The semiconductor device according to claim 1. 4. 4. The semiconductor device according to claim 1, wherein the insulator isolation region is a silicon oxide. 5. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25856897A JP3204449B2 (en) | 1997-09-24 | 1997-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25856897A JP3204449B2 (en) | 1997-09-24 | 1997-09-24 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62079140A Division JP2767104B2 (en) | 1987-03-30 | 1987-03-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1074900A JPH1074900A (en) | 1998-03-17 |
| JP3204449B2 true JP3204449B2 (en) | 2001-09-04 |
Family
ID=17322057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25856897A Expired - Lifetime JP3204449B2 (en) | 1997-09-24 | 1997-09-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3204449B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4855690B2 (en) * | 2005-02-15 | 2012-01-18 | セイコーＮｐｃ株式会社 | Semiconductor device having a capacitor |
-
1997
- 1997-09-24 JP JP25856897A patent/JP3204449B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1074900A (en) | 1998-03-17 |
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