JP3200056B2 - Error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial application field B Outline of the invention C Conventional technology (FIGS. 4 to 7) D Problems to be solved by the invention (FIG. 7) E Means for solving the problems (FIG. 1) And FIG. 3) F action (FIGS. 1 and 3) G embodiment (G1) First embodiment (FIGS. 1 and 2) (G2) Second embodiment (FIG. 3) (G3) Other Embodiments H Effects of the Invention A Industrial Field of the Invention The present invention relates to an error correction circuit, and more particularly to an error correction circuit for detecting and correcting errors in transmission data transmitted by adding an error correction code based on a product code format. It is suitable to be applied to.

B. Summary of the Invention In a first invention, an error correction circuit writes inner code correction data transmitted from an inner code error detection and correction means in a predetermined block data unit to a memory in accordance with address information obtained from a counter, By reading the memory in accordance with the outer code sequence using the memory offset information of the leading block data detected based on the identification data included in the error-free or error-correctable block data. Even when an error occurs in the identification data of the block data, valid block data can be transmitted to the outer code error detection and correction means, and the error detection accuracy and error correction performance can be improved as a whole.

According to a second aspect of the present invention, in the error correction circuit, the continuity of the identification data included in the block data input from the inner code error detection and correction means is monitored, and according to the monitoring result, whether the block data is regular block data or not. By judging whether or not the error has occurred and controlling the write address to the memory and the inner code error flag, even if an error is detected by the inner code error detection and correction means, the error is corrected by the outer code error detection and correction means. Can be prevented.

C Prior Art Conventionally, as a recording / reproducing apparatus for recording information data at a high density, a video of a so-called SMPTE D-1 format digital video tape recorder (digital VTR) in which a component digital video signal is recorded on a magnetic tape. A so-called ANSI ID-1 format (Third Draft PROPOS) which records and reproduces desired information data in place of data and audio data.
ED AMERICAN NATIONAL STANDARD 19mm TYPE ID-1 INST
RUMENTATION DIGITAL CASSETTE FORMAT X3B6 / 88−12 Pr
oject 592-D 1988-03-22) has been proposed.

In such a magnetic recording / reproducing apparatus, information data is recorded by adding an error correction code based on a Reed-Solomon product code format, and a transmission error is detected during reproduction and corrected. Thus, it is possible to prevent the occurrence of a reproduction error peculiar to the magnetic propagation system.

That is, the recording system 1 of the ID-1 format magnetic recording / reproducing apparatus is configured as shown in FIG. 4, and information data DT _USE to be recorded is input to the outer code generation circuit 2.

In the outer code generation circuit 2, first, the information data
After capturing one sector (= 36,108 bytes) of the DT _USE, delimiting the information data DT _USE of 306 pieces per 118-byte data blocks DT ₀ to DT _305, each data block DT using a predetermined generating polynomial 10 for each of _{0 to} DT ₃₀₅
Parity code RO ₀ consisting of byte Reed-Solomon code
RO ₃₀₅ is generated as an outer code, and this is added after each data block DT _{0 to} DT ₃₀₅ .

Subsequently, 306 outer data blocks DO _{0 to} DO each having a length of 128 bytes each generated in this manner.
₃₀₅ is a RAM (random access memor) as shown in FIG.
y) Data section of each of the two memory matrices MEM1 and MEM2 having a configuration in which a row and a column are each 153 bytes × 128 bytes
Data is sequentially written in the column direction of MEM _DT1 and MEM _DT2 .

In addition, from the left end of the memory matrices MEM1 and MEM2,
4 x 128 bytes of rows and columns have 4 rows each.
Block synchronization code SY with fixed byte length pattern
NC _BLK is pre-written.

In the memory matrices MEM1 and MEM2,
The 1 × 128 byte length of the row and column following the block synchronization code SYNC _BLK is allocated as identification data parts MEM _ID1 and MEM _ID2 , and is input from the identification data generation circuit 4 in the next first multiplexer circuit 3. The even-numbered ID _BLKA and the odd-numbered ID _BLKE of the block identification data ID _BLK to be _{processed correspond} to the identification data portions ME of the memory matrices _MEM1 and MEM2, respectively.
_Data is written in the column direction of M _ID1 and MEM _ID2 .

After this, the right end of this data section MEM _DT1 and MEM _DT2 is
In the inner code generation circuit 5, the block synchronization code SYNC
_BLK , inner data blocks DI ₀ , DI ₂ ,..., DI _{254 corresponding to} a 5-byte length in the row direction of the block identification data ID _BLK and a 153-byte length when the data portions MEM _DT1 and MEM _DT2 are viewed in the row direction.
, And DI ₁ , DI ₃ ,..., DI ₂₅₅ , parity codes RI ₀ , RI ₂ ,..., RI ₂₅₄ and RI ₁ , RI ₃ , which are 8-byte Reed-Solomon codes using a predetermined generator polynomial ......, R
I ₂₅₅ is generated and added as an inner code.

Subsequently, the memory matrices MEM1 and MEM2 are added to the second multiplexer circuit 6 for one sector SE.
The 4-byte sector identification data ID _SEC1 input as the preamble portion PR from the preamble portion postamble portion generation circuit 7 and the 6-byte length extended data DT _AUX input from outside are added to the beginning of the C portion. Following the sector SEC, a 4-byte length synchronization code SYNC _PS and sector identification data ID _SEC2 are added as a postamble portion PS, and then sent to the subsequent data distribution circuit 8.

In the data distribution circuit 8, first, following the preamble portion PR, 166 bytes in the row direction of the memory matrices MEM1 and MEM2 are used as one synchronization block BLK, and are sequentially alternated in ascending order of the identification data ID _BLK of the memory matrices MEM1 and MEM2. to read, adding the postamble portion PS Following one sector SEC fraction i.e. 256 sync blocks BLK ₀ ~BLK _255, and sends it to the 8-9 modulating circuit 9.

8-9 modulating circuit 9, a preamble portion PR of one sector is input, the synchronization block BLK ₀ ~BLK ₂₅₅ and postamble portion PS, at specified in ID-1 the format approach,
The data is modulated into a data format suitable for magnetic recording. In the third multiplexer circuit 10, the preamble portion PR indicates the start of one sector SEC input from the synchronization code generation circuit 11 in the preamble portion PR.
A rising sequence RUS having a length of 0 bytes and a synchronization code SYNC _{PR formed} of a fixed pattern having a length of 4 bytes are added and transmitted to the subsequent parallel / serial conversion circuit 12.

The parallel / serial conversion circuit 12 receives the preamble portion PR for one sector SEC and the synchronization blocks BLK _{0 to} BLK.
₂₅₅ and the postamble part PS are converted into a recording signal S _REC composed of serial data, and after the recording signal S _REC is amplified by the recording amplification circuit 13, the magnetic head 15 scans the magnetic tape 14 while performing a helical scan. Thus, the recording tracks TR (..., TR1, TR2, TR3, TR4,...) Are formed on the magnetic tape 14 as shown in FIG. An error correction code can be added to DT _USE based on the Reed-Solomon product code format and recorded.

The information data DT _USE recorded on the magnetic tape 14 by the recording system 1 of the magnetic recording / reproducing apparatus in this manner is the seventh data.
The data is reproduced by the reproducing system 20 of the magnetic recording / reproducing apparatus shown in FIG.

That is, in the reproducing system 20 of the magnetic recording / reproducing apparatus, first, the recording tracks TR (..., TR1, TR2, TR3, TR4,.
..) Are read out and sent to the reproduction amplifier circuit 21.

The reproducing amplifier circuit 21 is configured to include an equalizer and binary circuit or the like, binarizes the reproduced signal S _PB sent from the magnetic head 15, the resulting reproduced digital data DT _PB is followed Serial / parallel conversion circuit 22
In after being converted into parallel data DT _PR, 8-9 demodulation circuit
Supplied to 23.

The 8-9 demodulation circuit 23 receives the input parallel data DT _PR
If the rising sequence RUS of the preamble part PR and the synchronization code SYNC _PR are detected during the
The parallel data DT _PR for SEC is demodulated by the method specified in ID-1 format, and the resulting 1 sector SE is obtained.
The reproduction data DT _SEC for C is transmitted to the inner code error detection and correction circuit 24.

In this inner code error detecting and correcting circuit 24, following the preamble portion PR of demodulated reproduction data DT _SEC, for each synchronous block BLK ₀ ~BLK _255, and performs error detection and correction process using sequential inner code, The RAM has the same RAM configuration as described above with reference to FIG. 4, and has identification data in the row direction of two memory matrices having a capacity of 162 × 128 bytes.
ID _BLK, in the order of synchronization Bro poke data DT _BLK and parity code RI corresponding to the inner data blocks DI ₀ -DI _255, writes sequentially alternately.

In practice, the inner code error detection and correction circuit 24 generates the error-free synchronization block BLK or the error-corrected synchronization block B.
For LK, a memory address corresponding to the identification data ID _BLK of the synchronization block BLK, the identification data ID _BLK, writing in the order of synchronization Bro poke data DT _BLK and parity code RI, also the error uncorrectable synchronous block BLK is Only by adding the inner code error flag FLG _IN , the writing of the synchronization block BLK to the memory is stopped.

In the outer code error detection and correction circuit 25, the two memory matrices written by the inner code error detection and correction circuit 24 are sequentially read in units of 128 bytes in the column direction, and an error detection and correction process using an outer code is executed. Thus, the recorded information data DT _USE can be reproduced.

D Problems to be Solved by the Invention However, as in the reproducing system 20 of the magnetic recording / reproducing apparatus having such a configuration, in the inner code error detecting and correcting circuit 24, the synchronous block BLK for which the error cannot be corrected is converted into the synchronous block BLK for the memory. When the writing is controlled to be stopped, an error occurs in a portion other than the synchronization block data DT _BLK , that is, in the synchronization code SYNC _BLK , the identification data ID _BLK, or the parity code RI, so that error correction cannot be performed. In this case, the correct synchronous block data DT _BLK is not sent to the outer code error detection and correction circuit 25 because the synchronous block data DT _BLK that is not actually erroneous is not written into the memory. However, there is a problem that error correction becomes impossible.

Further, in the inner code error detection and correction circuit 24, when an error is corrected by mistake in a certain synchronous block BLK, and when the identification data ID _BLK of the synchronous block BLK is incorrect, the synchronous block BLK is stored in the wrong memory address. However, when the data is written as a correct synchronous block BLK, as a result, when an erasure operation is performed in the outer code error detection and correction circuit 25, there is a problem that the data is erroneously corrected.

Further, in the case where the identification data ID _BLK is other than the value "00", and the data of all "0" is input due to a dropout on the magnetic tape 14 or the like, the identification data ID _BLK is not changed to the value. To write the synchronous block BLK of all "0" as correct data to the address of the memory corresponding to "00", if the erasure operation is performed by the outer code error detection and correction circuit 25 in the same manner as described above, further erroneous correction will be made. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to solve the conventional problems at once and propose an error correction circuit capable of further improving error correction efficiency and accuracy.

Means for Solving E Problem In order to solve such a problem, in the first invention,
The error correction circuit 30, which adds the error correction codes RO and RI to the information data DT _USE based on the product code format and transmits the transmitted data DT _SEC and corrects the error,
An inner code error detection and correction means 24 for detecting an inner code error of DT _SEC and correcting the inner code error, and an inner code error detection and correction means 24 based on the supplied address information ADR _ROW.
Storage means 32 for storing the inner code correction data BLK (ID _BLK , DT _BLK , RI) output from the CPU in units of predetermined block data BLK, and a counter 33 operating in units of block data BLK
The address information ADR _ROW obtained from the block data BLK is _supplied to the storage means 32, and the block identification data ID which is included in the block data BLK in which no error exists or has been corrected and which is incremented for each block data BLK unit.
_BLK and address information ADR assigned to block data BLK in which no error exists or error correction has been performed.
Calculates the difference from _ROW and sets the result to OFFSET information OFF
Control means 35, 36, and 37, and control means 35, 3
The block data BLK is read out from the storage means 32 in accordance with the outer code sequence using the offset information OFF output from 6, 37, the outer code error is detected, and the outer code error is corrected and transmitted to the outside. A code error detection and correction means 25 is provided.

Further, in the second invention, the error correction circuit 40 for adding the error correction codes RO and RI to the information data DT _USE based on the product code format and receiving and correcting the transmission data DT _SEC , An inner code error detection and correction means 24 for detecting an inner code error of the transmission data and correcting the inner code error, and an inner code output from the inner code error detection and correction means 24 based on the supplied address information ADR _ROW. Storage means 24 for storing the correction data BLK (ID _BLK , DT _BLK , RI)
And inner code correction data BLK (ID _BLK , D BLK) transmitted from the inner code error detection / correction means 24 in units of predetermined block data BLK.
_TBLK , RI) for each block data BLK, counting means 43, and inner code correction data BLK (ID _BLK , DT
_BLK , RI) detecting means 46 for detecting block identification data ID _BLK which is included for each block data BLK unit and incremented for each block data BLK unit, and detects the count result C _OUT output from the counting means 43. Means 46
The determination means 45, 47 for determining whether or not the block identification data ID _BLK output from the storage device coincides, and the determination means 45, 47 determine that the count result C _OUT matches the block identification data ID _BLK . Block identification data ID in case
_While the address information ADR _ROW1 is generated by selecting _BLK , if it is determined that they do not match, the address generation means 44, 49 for selecting the count result C _OUT and generating the address information ADR _ROW1 , and the storage means An outer code error detection / correction means 25 for reading out the block data BLK from 42 according to the outer code sequence, detecting the outer code error, correcting the outer code error and sending it to the outside is provided.

F function According to the address information ADR _ROW obtained from the counter 33 operating in block data BLK units, the inner code correction data
The BLK (ID _BLK , DT _BLK , RI) is written into the storage means 32, the identification data ID _BLK included in the block data BLK in which no error exists or the error has been corrected, and the address information assigned to the block data BLK. The offset information OFF is calculated from the difference from the ADR _ROW, and the block data BLK is read from the storage means 32 using the offset information OFF, so that even if an error occurs in the identification data ID _BLK , the block data BLK is removed. It can be transmitted to the code error detection and correction means 25, and the error detection accuracy and error correction capability can be improved.

Also, the inner code correction data BLK (ID _BLK , DT _BLK , RI) is counted for each block data BLK unit, the identification data ID _BLK included for each block data BLK unit is detected, and the count result C _OUT is obtained. Compared with the identification data ID _BLK , if they match, the address information ADR _ROW1 is generated from the identification data ID _BLK, while if they do not match, the address information ADR _ROW1 is generated from the count result C _OUT Thus, the inner code error detection and correction means 24
Thus, even if erroneous detection occurs in, the erroneous correction by the outer code error detection and correction means 25 can be prevented.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) First Embodiment In FIG. 1 in which parts corresponding to those in FIG. 7 are assigned the same reference numerals, reference numeral 30 designates an error correction circuit as a whole according to the first invention, and a reproduction system of a magnetic recording / reproducing apparatus. As in the case of FIG. 20 (FIG. 7), the inner code error detection / correction circuit 24 performs synchronization blocks BLK _{0 to} BLK ₂₅₅ of the demodulated reproduction data DT _SEC for one sector SEC.
Each time, an error detection and correction process using an inner code is executed sequentially, and the identification data ID _BLK , synchronization block data DT _BLK , parity code RI, and inner code error flag FLG _IN having, for example, a 1-byte length obtained as a result are obtained. In accordance with the address information provided from the memory control circuit 31, a RAM (random access
memory) Write to the configured memory 32.

Also, the outer code error detection and correction circuit 25 reads the memory 32 sequentially in units of 128 bytes in the column direction according to the address information given from the memory control circuit 31, and then refers to the inner code error flag FLG _IN to determine the outer code. The used error detection and correction processing is executed, whereby the information data DT _USE recorded on the magnetic tape 14 can be reproduced.

In practice, the memory control circuit 31 receives the reset signal RST sent at the timing when the sector identification data ID _SEC1 is detected by the inner code error detection / correction circuit 24.
It has an 8-bit counter 33 that is reset to a value "0".

The counter 33, from the inner code error detecting and correcting circuit 24, Yotsute the count pulse CNT which is sent to each input of the synchronous block BLK ₀ ～BLK _255, the count value "0" to "255"
The counter comprises a cyclic counter which executes the count-up operation up to and returns to a value "0" upon overflow.

In the memory 32, two memory matrices MEM10 and MEM20 each having a capacity of 163 × 128 bytes are formed in the same configuration as the two memory matrices MEM1 and MEM2 described above with reference to FIG. The identification data ID _BLK for one synchronization block BLK, the synchronization block data DT _BLK , the parity code RI, and the 163 bytes of the inner code error flag FLG _IN input from the inner code error detection and correction circuit 24 can be stored in one line. It has been made like that.

The count value transmitted from the counter 33 is transmitted as a memory address ADR _ROW in units of one row of the memory matrices MEM10 and MEM20, and is supplied to the memory 32.

Here, the writing of the identification data ID _BLK for one synchronization block BLK, the synchronization block data DT _BLK , the parity code RI and the inner code error flag FLG _{IN to} the memory 32 is performed by sequentially writing even numbers of the memory address ADR _{ROW to} the first memory. Write to the matrix MEM10 and respond to the memory address ADR
The odd number of _ROW have been made to write in the order as soon as 2 of the memory matrix MEM20.

In addition to this, in the case of the memory control circuit 31 of this embodiment, the identification data ID _BLK for one synchronization block _BLK , the synchronization block data DT _BLK , the parity code RI, Inner code error flag FLG
_IN is sequentially input to the block ID detection circuit 34.

The block ID detection circuit 34 refers to the inner code error flag FLG _IN in one synchronization block BLK, and detects an error-free or error-corrected synchronization block BLK.
Detecting the identification data ID _BLK, and sends it to the subtraction circuit 35 and the adding circuit 36.

Actually, this identification data ID _BLK is the memory address AD sent from the counter 33 when there is no error or the error-corrected synchronous block BLK continues.
Like R _ROW , it is incremented for each synchronization block BLK.

Note that the subtraction circuit 35 calculates the difference between the identification data ID _BLK input from the block ID detection circuit 34 and the memory address ADR _ROW input from the counter 33, and sets the result of this calculation as a memory offset OFF to register It is sent to the offset detecting circuit 37 having the above configuration.

Actually, in this memory control circuit 31, one sector
During the synchronization block BLK for SEC, the counter 33 counts the count pulse CNT until the first error-free or error-corrected synchronization block BLK is input.
The identification data ID _BLK for one synchronization block _BLK , the synchronization block data DT _BLK , the parity code RI and the inner code error flag FLG _IN are written at a position where the count value is set as the memory address ADR _ROW. .

In addition, in the synchronous block BLK for one sector SEC, when the synchronous block BLK in which no error exists or the error is corrected is input first, the difference between the identification data ID _BLK and the memory address ADR _ROW is set as the memory offset OFF. The offset is held in the offset detection circuit 37.

Thereafter, even when a synchronous block BLK for which error correction is impossible is input, the identification data ID _BLK and the synchronous block data DT for one synchronous block BLK are stored at the position of the memory address ADR _ROW sent from the counter 33. Write _BLK , parity code RI and inner code error flag FLG _IN .

When an error-free or error-corrected synchronous block BLK is input, its identification data ID _BLK
And the memory offset held in the offset detection circuit 37.
OFF is added in the adder circuit 36, the result of the addition is loaded into the counter 33, and the identification data ID _BLK and the synchronous block data DT for one synchronous block BLK are stored at the position of the memory address ADR _ROW sent from the counter 33. Write _BLK , parity code RI and inner code error flag FLG _IN .

The memory offset OFF held in the offset detection circuit 37 and the memory address A sent from the counter 33
DR _ROW is input to the final address detection circuit 38.

This last address detection circuit 38 is a memory offset OF
When detecting a synchronous block BLK in which the memory address ADR _ROW for one sector SEC is obtained by adding the memory offset OFF value “255” using F, a memory control signal C for controlling the memory 32 to a write-protected state. _{The MEM} is sent out, and the writing of the synchronous block BLK to the memory 32 thereafter is stopped.

The outer code error detection and correction circuit 25 is an offset detection circuit
The first byte of the synchronous block data DT _BLK corresponding to the memory offset OFF obtained from 37 is set as the read start address, and the read address is counted up in the column direction every other column sequentially from this start address. 128 bytes of data obtained by the reading as an outer data block DO _0, executes outer code error detecting and correcting process.

Subsequently, the outer code error detection / correction circuit 25 repeats the same processing as described above 152 times, and then reads the first byte of the synchronous block data DT _BLK corresponding to the address obtained by adding the value "1" to the memory offset OFF. The read address of the 128-byte outer data block DO is set 153 times in the same manner as described above.

In this way, the outer code error detection and correction circuit 25 reads out the synchronous block data DT _BLK written in the memory 32, executes the outer code error detection and correction processing including the erasure operation referring to the inner code error flag FLG _IN, and ,
Run the sorting corresponding to the outer code sequence, In this way, by reproducing the information data DT _USE recorded on the magnetic tape 14, is configured so as to be able to sent the reproduction data DT _PB.

In the above configuration, for example, the identification data I for one synchronization block BLK sent from the inner code error
D _BLK , synchronous block data DT _BLK , parity code RI and inner code error flag FLG _IN are synchronized block input data D
If the synchronization block input data DT following the head of one sector SEC is sequentially numbered as T, the memory control circuit 31
Is the memory address ADR _ROW and the synchronous block input data
The writing process to the memory 32 is executed in the order as shown in FIG. 2 in which the identification data ID _BLK corresponding to the DT is displayed in hexadecimal.

That is, the counter 33 of the memory control circuit 31 outputs the reset signal RST sent from the inner code error detection and correction circuit 25.
The synchronous block input data DT reset at the beginning of one sector SEC and input from the beginning in one sector SEC is sequentially written to the memory 32 from the beginning address.

The memory 32 has two memory matrices MEM10 and M
Memory address with EM20 and sent from counter 33
First memory matrix ME when ADR _ROW has an even value
M10 and the second memory matrix MEM20 when the memory address ADR _ROW has an odd value, respectively.

Therefore, the synchronous block input data DT1 input first
Is that the memory address ADR _ROW in the first memory matrix MEM10 is written at the position of the value "00", and the subsequent synchronous block input data DT2 is written in the second memory matrix MEM20.
Memory address ADR _ROW is written in the position of the value "01" in further followed by a third synchronous block input data DT
3 is that the memory address ADR _ROW in the first memory matrix MEM10 is written at the position of the value “02”.

In FIG. 2, the first to third synchronous block input data DT1 to DT3 are assumed to be error-correctable and have no identification data ID _{BLK, and} are indicated by "■" in the figure. I have.

Further, the fourth and fifth synchronous block input data DT
4, DT5 has the identification data ID _BLK with the value "00" and "0
Although it exists as "1", the error cannot be corrected due to a cause other than the synchronous block data DT _BLK , so the memory address ADR _ROW sent from the counter 33 is written to a position having the values "03" and "04". .

Subsequently input sixth synchronous block input data DT6
Is the identification data ID _BLK in the block ID detection circuit 34.
Is detected as a value “02”, and is indicated by “□” in the figure as an error-free or error-correctable one.

In this case, the block ID detection circuit 34 outputs one sector.
The subtraction circuit 35 determines the identification data from the memory address ADR _ROW value “05” at this time because there is no error or the error is the synchronous block input data DT that can be error-corrected. Calculate the value "03" obtained by subtracting the ID _BLK value "02" as the memory offset OFF,
This is sent to the offset detection circuit 37, and the input sixth synchronization block input data DT6 is written at the position of the value "05" of the memory address ADR _ROW .

The seventh synchronous block input data DT7 subsequently inputted is, as can be seen from "□" in the figure, an synchronous block input data DT in which no error exists or error correction is possible. The value “03” of the identification data ID _BLK sent from the block ID detection circuit 34 and the value “0” of the memory offset OFF held in the offset detection circuit 37
The value "06" resulting from the addition is loaded into the counter 33, and the value of the seventh address inputted to the value "06" of the memory address ADR _ROW obtained as a result is added to the counter 33. Write the synchronous block input data DT7.

The three synchronization block input data DT subsequently inputted have identification data ID _BLK as values "04", "05", and "06", respectively, as can be seen from "■" in the figure. Synchronous block input data DT for which error correction was not possible due to a cause other than ID _BLK .

Therefore, the counter 33 sequentially counts up the value "06" loaded from the adding circuit 36, and obtains the memory address ADR _ROW values "07", "08", "09" obtained as a result.
Are sequentially written in the three synchronous block input data DT input to the CPU.

Such processing is repeated, and while the input synchronous block input data DT is sequentially written at a position corresponding to the value of the memory address ADR _ROW , the synchronous block input data DT having the identification data ID _BLK having the value “FD” is eventually obtained. When input, the memory address ADR _ROW sent from the counter 33 through the adder circuit 36 becomes the value “00” by adding the memory offset OFF value “03” to the identification data ID _BLK value “FD”, The memory address ADR _ROW goes around once.

In this case, the synchronous block input data DT1 has already been written at the position where the memory address ADR _ROW has the value "00", but the first synchronous block input data DT necessary for the outer code error detection and correction circuit 25 is As indicated by the offset OFF value `` 03 '', the data is written after the memory address ADR <sub>ROW</sub> value `` 03 '', and the previous synchronization block input data DT is meaningless to be transmitted to the outer code sequence. Is determined.

As a result, the synchronous block input data DT having the identification data ID _BLK having the value “FD” is overwritten at the position of the value “00” of the memory address ADR _ROW , and the identification data ID _BLK that is subsequently input has the value “FD”. Synchronous block input data DT having "FE" and "FF" are also overwritten at the values "01" and "02" of the memory address ADR _ROW , respectively, as described above.

At this time, the last address detection circuit 38
Detects that the memory address ADR _ROW output from 33 has reached the value "02", which is the value "FF" plus the memory offset OFF value "03", and controls the memory 32 to be write-protected. Then, the memory control signal C _MEM to be transmitted is transmitted, and the subsequent writing of the synchronous block input data DT to the memory 32 is stopped.

In this manner, in the error correction circuit 30, not only the synchronous block input data DT having no error or error correction but also the error-correctable synchronous block input data DT is transmitted from the counter 33. By writing data to the memory 32 based on the memory address ADR _ROW , even when error correction cannot be performed due to an error occurring in a place other than the synchronous block data DT _BLK , the outer code detection and correction circuit 25 Synchronous block data DT _BLK can be transmitted.

The outer code error detection and correction circuit 25 reads the memory 32 in which the synchronous block input data DT for one sector SEC has been written as described above, and the offset detection circuit 37.
Starting from the synchronous block data DT _BLK written in the second memory matrix MEM20 of the memory address ADR _ROW of the memory offset OFF value "03" obtained from the memory address ADR _ROW values "05" and "07"",......," FD ",
Synchronous block data DT read out from the 128 bytes in the column direction represented by "FF",..., "01" as an outer code sequence, and thereafter written into a memory address ADR _ROW having a value of "03"
_The 153 bytes from the top of the _BLK are sequentially read 153 times in the same manner, and the first memory matrix MEM10 is also sequentially read from the value "04" obtained by adding the value "01" to the value "03" of the memory offset OFF. The data of 128 bytes in the column direction is read 153 times in the same manner as described above.

According to the above configuration, the synchronous block input data DT sent from the inner code error detection and correction circuit 24 is written to the memory 32 according to the memory address ADR _ROW sent from the counter 33 regardless of the presence or absence of an error. Based on the identification data ID _BLK of the synchronous block input data DT in which no error exists or error can be corrected, the first synchronous block input data DT of one sector SEC is detected, and this is held as a memory offset OFF, and the external block is detected. In the code error detection / correction circuit 25, the memory 32 is read out in the order of the outer code sequence in accordance with the memory offset OFF, so that the error is not limited to the synchronous block input data DT in which no error exists or error can be corrected. For example, due to an error occurring at a place other than the synchronous block data DT _BLK , the error cannot be corrected. About DT,
The correct synchronous block data DT is supplied to the outer code detection and correction circuit 25.
_{The BLK} is transmitted, and thus the error correction circuit 30 that can further improve the error detection accuracy and the error correction capability as a whole can be realized.

(G2) Second Embodiment In FIG. 3, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, reference numeral 40 denotes an error correction circuit as a whole according to the second invention, and a reproducing system of a magnetic recording / reproducing apparatus. As in the case of FIG. 20 (FIG. 7), the inner code error detection / correction circuit 24 performs synchronization blocks BLK _{0 to} BLK ₂₅₅ of the demodulated reproduction data DT _SEC for one sector SEC.
Each time, an error detection and correction process using an inner code is sequentially performed, and the identification data ID _BLK , synchronization block data DT _BLK and parity code RI obtained as a result are stored in a memory control circuit 41.
RAM (random ac) according to the address information given from
cess memory).

Further, the outer code error detection and correction circuit 25 performs an error detection and correction process using the outer code by sequentially reading the memory 42 in units of 128 bytes in the column direction with reference to the inner code error flag FLG _IN. The information data DT _USE recorded on the magnetic tape 14 can be reproduced.

Actually, the memory control circuit 41 has an 8-bit value which is reset to a value "0" in response to the reset signal RST transmitted at the timing when the sector identification data ID _SEC1 is detected in the inner code error detection and correction circuit 24. It has a counter 43.

The counter 43, from the inner code error detecting and correcting circuit 24, Yotsute the count pulse CNT which is sent to each input of the synchronous block BLK ₀ ～BLK _255, the count value "0" to "255"
Run the counting up-operation of the up, at the time of the overflow consists of the cyclic counter back to the value "0", the count output C _OUT is delivered to the selector 44 and the subtraction circuit 45.

In the case of the memory control circuit 41, the identification data ID _BLK , the synchronization block data DT _BLK and the parity code RI for one synchronization block BLK sent from the inner code error detection and correction circuit 24 are sequentially transmitted to the block ID detection circuit 46. Has been entered.

The block ID detection circuit 46 refers to the inner code error flag FLG _IN in one synchronization block BLK, and detects an error-free or error-corrected synchronization block BLK.
Detecting the identification data ID _BLK, which is sent to the selector 44 and the subtraction circuit 45.

Actually, this identification data ID _BLK is equal to the count output C _OUT sent from the counter 43 when there is no error or when the error-corrected synchronous block BLK continues.
Similarly to the above, it is incremented for each synchronization block BLK.

Also, the memory 42 may be similar to that described above with reference to FIG.
Two memory matrices MEM10 and MEM20, each having a capacity of 163 × 128 bytes in rows and columns, are formed,
The identification data ID _BLK for one synchronization block _BLK and the synchronization block data DT input from the inner code error detection and correction circuit 24
_BLK , parity code RI and inner code error flag FLG _IN
163 bytes can be stored in one line.

The subtraction circuit 45 subtracts the count output C _OUT from the input identification data ID _BLK, and outputs the difference value SB to the determination circuit 47.
To supply.

The judgment circuit 47 receives the inner code error flag FLG _IN sent from the inner code error detection and correction circuit 24 together with the error flag generation circuit 48.

As a result, the determination circuit 47 sets the inner code error flag FLG _IN
, When it is detected that there is no error in the synchronization block BLK or error correction has been performed, the input difference value SB is calculated using a negative number N and a positive number Μ preset inside. It is determined whether or not the following expression N ≦ SB ≦ M (1) is satisfied. When the expression (1) is satisfied, the selector 44 sends a selector control signal C _SEL for selecting the identification data ID _BLK to the selector 44. Send out.

As a result, the identification data ID _BLK is transmitted to the address generation circuit 49 via the selector 44, and the identification data ID _BLK
At the position in the row direction corresponding to the memory address ADR _ROW1 generated based on the
D _BLK , synchronous block data DT _BLK , and parity code RI are written.

The determination circuit 47 _supplies the counter 43 with a counter control signal C _LD for loading the value of the identification data ID _BLK at this time.
Is transmitted, and thereafter, the counting operation is performed from the value of the identification data ID _BLK .

In addition, the determination circuit 47 sends an error flag control signal C _EF that allows the input inner code error flag FLG _IN to pass to the error flag generation circuit 48, whereby the inner code error flag FLG _IN Is written to the memory 42 as it is.

On the other hand, when the determination circuit 47 determines that the expression (1) is not established, the determination circuit 47 sends the count output C to the selector 44.
_The selector control signal C _SEL for selecting _OUT is transmitted.

As a result, the count output C _OUT is sent to the address generation circuit 49 via the selector 44, and the count output C _OUT
At the position in the row direction corresponding to the memory address ADR _ROW1 generated based on the
D _BLK , synchronous block data DT _BLK , and parity code RI are written.

Note decision circuit 47, to the error flag generating circuit 48 in addition to this, transmits an error flag control signal C _EF to set the inner code error flag FLG _IN forcibly, thereby inner code error flag FLG _IN is Even if it is not set, it is written to the memory 42 as an error.

In addition, 1 input from the inner code error detection and correction circuit 24
When the identification data ID _{BLK for} the synchronization block _BLK , the synchronization block data DT _BLK , and the parity code RI cannot be corrected, the determination circuit 47 sends a selector control signal to the selector 44 to select the count output C _{OUT. Send} C _SEL .

As a result, the count output C _OUT is sent to the address generation circuit 49 via the selector 44, and the count output C _OUT
At the position in the row direction corresponding to the memory address ADR _ROW1 generated based on the
D _BLK , synchronous block data DT _BLK , and parity code RI are written.

The determination circuit 47 sends an error flag control signal C _EF that allows the input inner code error flag FLG _IN to pass to the error flag generation circuit 48, whereby the inner code error flag FLG _IN is directly stored in the memory 42. Is written to.

This is because the identification data ID _BLK of the synchronization block BLK originally input sequentially has continuity, and when no error exists or the error-correctable synchronization block BLK is input continuously, the block ID is output. The value of the identification data ID _BLK sent from the detection circuit 46 is always equal to the value of the count output C _OUT sent from the counter 43.

Therefore, the difference value SB sent from the subtraction circuit 45 should always be the value "0". If the difference value SB does not become the value "0", the identification data of the synchronization block BLK is lost for some reason. It is _probable that ID _BLK became discontinuous.

Therefore, in the case of this embodiment, in the determination circuit 47,
The validity of the synchronization block BLK is determined by determining whether or not the equation (1) is satisfied. If the synchronization block BLK is determined to be valid, the memory address ADR obtained from the identification data ID _BLK is determined. The identification data ID _BLK for one synchronization block _BLK and the synchronization block data D are stored in _ROW1.
Write T _BLK and parity code RI.

Conversely, if it is determined that the block is not the regular synchronous block BLK, the count output C _OUT sent from the counter 43 is continuous from the identification data ID _{BLK of} the regular synchronous block BLK input before the synchronous block BLK. _Therefore , the memory address AD obtained from the count output C _OUT
In R _ROW1 , the identification data I for one synchronization block BLK is stored.
_DBLK , synchronous block data _DTBLK , and parity code RI are written.

Also, since it is determined that the block is not a regular synchronization block BLK, the inner code error detection flag F of the synchronization block BLK is determined.
An error is set in LG _IN and written to the memory 42.

Further, when the equation (1) is satisfied, that is, when it is determined that the synchronization block BLK is normal, the determination circuit 47 loads the counter 43 with the value of the identification data ID _BLK at that time and outputs the count output C The values of _OUT and the identification data ID _BLK are made to match.

Conversely, if the synchronization block BLK is not determined to be normal or if the inner code error detection flag FLG _IN indicates that error correction is not possible, the count output C _OUT of the counter 43 is sequentially counted up. .

According to the above configuration, by monitoring the continuity of the identification data ID _BLK of the synchronization block BLK input from the inner code error detection and correction circuit 24, it is determined whether or not the synchronization block BLK is a regular synchronization block BLK. However, by controlling the write address to the memory 42 and the inner code error detection flag FLG _IN , even if erroneous detection or the like occurs in the inner code error An error correction circuit 40 capable of preventing erroneous correction by the erasure operation of the code error detection and correction circuit 25 can be realized.

(G3) Other Embodiments (1) In the above-described embodiment, the synchronization block for one sector is halved in the memory according to the decentralization processing of the recording system.
Although the description has been made of the case where the memory matrices for storing the data are stored one by one, the same effect as that of the above embodiment can be realized by storing the synchronization blocks for one sector in one memory matrix instead.

(2) In the above-described first and second embodiments, the case where the memory address is obtained by the count output of the 8-bit cyclic counter has been described. The invention is not limited thereto, and various counters may be used according to the configuration of the memory matrix.

(3) In the above embodiment, the case where the present invention is applied to an ID-1 format magnetic recording apparatus has been described. However, the present invention is not limited to this, and the point is that the information data is formed in a product code format. Thus, the present invention is suitably applied to an information transmission apparatus to which an error correction code is added.

H Effect of the Invention As described above, according to the first aspect, the inner code correction data is written into the storage means in accordance with the address information obtained from the counter operating in units of block data, and no error exists or error correction is performed. The offset data is calculated from the difference between the identification data included in the block data and the address information assigned to the block data, and the block data is read from the storage means using the offset information, whereby the identification data has an error. When block error occurs, block data can be transmitted to the outer code error detection and correction means, and an error correction circuit capable of improving error detection accuracy and error correction capability can be realized.

Further, according to the second aspect, the inner code correction data is counted for each block data unit, the identification data included in each block data unit is detected, and the count result is compared with the identification data to determine the identification data. Address information is generated from the identification data when they match, and address information is generated from the count result when they do not match, so that an error is detected in the inner code error detection and correction means. Also, it is possible to realize an error correction circuit capable of preventing erroneous correction by the outer code error detection and correction means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an error correction circuit according to the first invention, FIG. 2 is a schematic diagram for explaining its operation, FIG. 3 is a block diagram showing an error correction circuit according to the second invention, and FIG.
The figure is a block diagram showing the recording system of the magnetic recording / reproducing apparatus.
The figure is a schematic diagram for explaining the memory matrix, and FIG.
FIG. 7 is a schematic diagram showing a format of a magnetic tape, and FIG. 7 is a block diagram showing a reproducing system of a magnetic recording / reproducing apparatus. 24 inner code error detection and correction circuit, 25 outer code error detection and correction circuit, 30, 40 error correction circuit, 31, 41 memory control circuit, 32, 42 memory, 33, 43 Counter, 34, 46 ... Block ID detection circuit, 35, 45 ... Subtraction circuit, 36 ... Addition circuit, 37 ... Offset detection circuit, 38 ...
... Last address detection circuit, 44... Selector, 47... Determination circuit, 48... Error flag generation circuit, 49.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hideto Suzuki 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-60-120680 (JP, A) 61-170962 (JP, A) JP-A-63-133721 (JP, A) Heitaro Nakajima "Illustrated DAT Reader" First Edition Ohmsha, July 1988, P.A. 68-73 (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 20/18 H03M 13/00

Claims (2)

(57) [Claims] An error correction circuit for receiving transmission data transmitted by adding an error correction code based on a product code format to information data and for correcting an error, wherein an inner code error of the transmission data is detected, Inner code error detection and correction means for correcting the inner code error, and storage means for storing inner code correction data output from the inner code error detection and correction means in predetermined block data units based on the supplied address information. The address information obtained from the counter operating in units of the block data is supplied to the storage means, and the address information is included in the block data in which no error exists or has been subjected to the error correction, and is incremented in each block data unit. The block identification data and the block data in which the error does not exist or the error is corrected Control means for calculating a difference from the address information assigned to the data, and outputting the calculation result as offset information; and removing the block data from the storage means using the offset information output from the control means. An error correction circuit comprising: an outer code error detection / correction unit that reads out according to a code sequence, detects an outer code error, corrects the outer code error, and sends the same to the outside. 2. An error correction circuit for receiving transmission data transmitted by adding an error correction code to information data based on a product code format and correcting the error, detecting an inner code error of the transmission data, Inner code error detection and correction means for correcting inner code errors; storage means for storing inner code correction data output from the inner code error detection and correction means based on the supplied address information; and A counting means for counting the inner code correction data transmitted from the means in a predetermined block data unit for each block data unit; and a counting means included in the inner code correction data for each of the block data units and for each of the block data units. Detecting means for detecting the incremented block identification data; and a count result output from the counting means. Determining means for determining whether or not the block identification data output from the detecting means matches; and, if the determining means determines that the block result matches the block identification data, the block While selecting the identification data and generating the address information, if it is determined that they do not match, an address generating means for selecting the count result and generating the address information; and storing the block data from the storage means. And an outer code error detecting / correcting means for reading out the outer code error according to the outer code sequence, detecting the outer code error, correcting the outer code error, and sending the same to the outside.