JP3298548B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a liquid crystal display device (international patent classification G02F1 / 1335) using a liquid crystal display panel and a backlight device.

[0002]

2. Description of the Related Art A conventional technique will be described below with reference to FIGS. FIG. 8 shows a conventional liquid crystal display device.

In FIG. 8, reference numeral 21 denotes a liquid crystal panel, 22 denotes a liquid crystal panel driving means for driving the liquid crystal panel 21 according to a video signal, 23 denotes a backlight, 24 denotes a backlight driving means for driving the backlight, and 25 denotes a backlight driving means. This is a PWM signal generation circuit. The PWM signal generating circuit 25 receives a vertical synchronizing signal and a horizontal synchronizing signal as inputs, and generates a PWM dimming pulse signal synchronized with the vertical synchronizing signal and having a frequency 2.5 times that of the vertical synchronizing signal. Further, the PWM dimming pulse signal is controlled by the PWM signal generation circuit 25 so as to have a duty ratio according to the PWM duty ratio setting data. Here, the PWM dimming means a method of controlling the brightness of the backlight by PWM (pulse width modulation).

With the configuration shown in FIG. 8, the video signal and the blinking of the backlight are synchronized. As a result, flickering of the screen due to interference between the cycle of the image displayed on the liquid crystal panel and the cycle of the blinking of the backlight, and electromagnetic noise generated by the backlight and the backlight driving means are coupled to the video signal processing system. Screen disturbance due to the above can be reduced.

[0005] PWM in the conventional liquid crystal display device of FIG.
The signal generation circuit 25 will be described in more detail with reference to FIGS. FIG. 9 is a circuit configuration example of a PWM signal generation circuit. FIG. 10 shows an NTSC signal (525 lines / frame, interlace) applied to the PWM signal generation circuit shown in FIG.
5 is a timing chart when the signal of FIG. Here, the dividing ratio k was set to 105.

In FIG. 9, 28 is a frequency dividing circuit, and 26 is K
The frequency dividing circuit 27 is a comparison circuit. The divide-by-2 circuit 28 divides the input vertical synchronizing signal by 2 to form a reset signal. The k divider circuit counts up the output data using the horizontal synchronization signal as a clock, and the output data becomes (k-1).
By resetting the output after counting up to this point, the sawtooth waveform data obtained by dividing the horizontal synchronization signal by k is output.

At the same time, the k frequency dividing circuit is reset by the reset signal. Now k = 105 and 525/10
5 = 5, which is 5 times the frame frequency of 30 Hz, that is, 1
A 50 Hz sawtooth wave is obtained in synchronization with the vertical synchronization signal. By comparing the sawtooth wave with the PWM duty ratio setting data, a PWM dimming pulse signal synchronized with the vertical synchronizing signal and having a frequency 5/2 times the frequency of the vertical synchronizing signal can be obtained.

[0008]

However, the conventional liquid crystal display device configured as described above has the following problems. When the number of lines per frame corresponds to an input signal having a different number, the frequency division ratio K and the PWM duty ratio setting data must be changed. For example,
A dimming control value A representing brightness (0 ≦ A ≦ 1.0)
Let h be the number of lines per frame, m be the ratio of the frequency of the PWM dimming pulse signal to the frequency of the vertical synchronizing signal, and
Assuming that the M duty ratio setting data is R, it is expressed as (Equation 1), and the above calculation has to be performed by a microprocessor or the like.

[0009]

(Equation 1)

[0010] Therefore, there is a problem that the scale of the arithmetic means such as a microprocessor becomes large or the operation becomes slow.

Further, in the conventional liquid crystal display device,
When the number of lines per frame corresponds to an input signal having a different number, the number of gradations of PWM differs, and
If the frequency of the dimming pulse signal is set high, there is a problem that the number of PWM gradations decreases, and fine dimming of the backlight brightness cannot be performed.

In view of the above-mentioned problems, the present invention requires a simple circuit to recalculate the frequency division ratio and PWM duty ratio setting data even when a plurality of signals having different numbers of lines per frame are input. It is another object of the present invention to realize a liquid crystal display device that can obtain a constant PWM gradation number and perform fine dimming of backlight brightness even when signals of a plurality of systems having different numbers of lines per frame are input. Things.

[0013]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention creates a PWM dimming pulse for performing PWM dimming of a backlight in a display device of a video signal using a liquid crystal display panel. In this case, a clock cycle as a reference for generating a PWM signal is obtained from a vertical synchronizing signal of a video signal and a multiplication ratio m which is a ratio between the frequency of the PWM dimming pulse and the vertical synchronizing signal. By generating the PWM dimming pulse from the pixel clock of (i), the PWM dimming with a period of 1 / m is performed in synchronization with the vertical synchronizing signal.

Thus, even when a plurality of signals having different numbers of lines per frame are input by a simple circuit, it is not necessary to recalculate the frequency division ratio and the PWM duty ratio setting data. Even when signals of a plurality of systems with different numbers of lines are input, a constant number of PWM gradations can be obtained, and a liquid crystal display device capable of finely adjusting the brightness of the backlight can be obtained.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention relates to a method for generating a PWM dimming pulse for performing PWM dimming of a backlight in a display device of a video signal using a liquid crystal display panel. From a vertical synchronizing signal of a video signal and a multiplication ratio m (m is a natural number) which is a ratio between the frequency of the PWM dimming pulse and the vertical synchronizing signal, a clock cycle as a reference of PWM signal generation is obtained. By generating the PWM dimming pulse from the pixel clock of the video signal based on the
This is characterized by performing WM dimming, and thus, even if a simple circuit inputs signals of a plurality of systems having different numbers of lines per frame, the frequency division ratio and the PWM are controlled.
There is no need to recalculate the duty ratio setting data, and even when signals of a plurality of systems with different numbers of lines per frame are input, a constant number of PWM gradations can be obtained and subtle dimming of backlight brightness can be achieved. Has the effect of being able to do it.

According to a second aspect of the present invention, there is provided a liquid crystal display panel, liquid crystal panel driving means for driving the liquid crystal display panel in accordance with a video signal to display a screen, and a backlight provided on the back side of the liquid crystal panel. Driving the backlight, turning on the backlight when the PWM dimming pulse signal is on, and turning off the backlight when the PWM dimming pulse signal is off, thereby turning on the PWM dimming pulse signal. Backlight driving means for dimming the backlight in accordance with the duty ratio of off and on, a pixel clock synchronized with a video signal, a vertical synchronization signal and a multiplication ratio m
(M is a natural number) and a period detection circuit for obtaining the period of the PWM reference clock, and the PWM of the period detection circuit output
A first frequency dividing circuit that divides the pixel clock by using a period of a reference clock as a dividing ratio and outputs the divided frequency as the PWM reference clock; PW generating said PWM dimming pulse signal having a ratio
An M signal generating circuit, wherein the cycle of turning on and off the dimming of the backlight is set to 1 / m of the vertical synchronizing signal. Even when signals of a plurality of systems having different numbers of lines per frame are input, it is not necessary to recalculate the frequency division ratio and PWM duty ratio setting data, and signals of a plurality of systems having different numbers of lines per frame can be obtained. Even when input, a certain number of PWM gradations can be obtained, and there is an effect that fine dimming of the brightness of the backlight can be performed.

According to a third aspect of the present invention, in the liquid crystal display device according to the second aspect of the present invention, in the period detecting circuit, the number of gray scales n (n is a natural number) of the PWM signal generating circuit is set to a frequency dividing ratio and a pixel clock is set. a second frequency divider for dividing the frequency by n, a third frequency divider for dividing the output circuit of the second frequency divider by m (m is a natural number), and an output pulse of the third frequency divider And a first pulse counting circuit that counts the number of cycles of the vertical synchronization signal for one cycle period and outputs the cycle as the cycle of the PWM reference clock.
Thus, even when a plurality of signals having different numbers of lines per frame are input by a simple circuit, it is not necessary to recalculate the frequency division ratio and the PWM duty ratio setting data, and the number of lines per frame is reduced. Even when signals of a plurality of different systems are input, a constant PWM gradation number can be obtained, and there is an effect that fine dimming of backlight brightness can be performed.

According to a fourth aspect of the present invention, in the liquid crystal display device according to the second aspect of the present invention, the second pulse counting circuit adds the output data one by one according to the timing of the PWM reference clock. And a comparison circuit for comparing the output data of the second pulse counting circuit with the PWM duty ratio setting data, whereby a simple circuit per frame is provided. Even when signals of a plurality of systems with different numbers of lines are input, it is not necessary to recalculate the frequency division ratio and PWM duty ratio setting data, and is constant even when signals of a plurality of systems with different numbers of lines per frame are input. The number of PWM gradations described above can be obtained, and a delicate dimming of the backlight brightness can be performed.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 1 shows an embodiment of a liquid crystal display device according to the present invention. In FIG. 1, reference numeral 1 denotes a liquid crystal display panel, 2 denotes a liquid crystal panel driving means, 3 denotes a backlight, 4 denotes a backlight driving means, and 5 denotes a period. A detection circuit, 6 is a first frequency dividing circuit,
7 is a PWM signal generation circuit.

The liquid crystal panel driving means receives a video signal and drives the panel to display the video signal on the liquid crystal display panel.
Here, the cycle of the vertical synchronization signal (one cycle is represented by the number of pixel clocks) is Tv, the multiplication number which is the ratio of the PWM frequency to the vertical synchronization signal frequency is m, and the PWM of the PWM signal generation circuit 7 is PWM.
The number of gradations n, becomes the cycle of the PWM reference clock (representing one cycle by the number of pixel clock) and L (the number 2), the period detection circuit 5 is multiplication factor m previously given,
Using the PWM gradation number n and the pixel clock, the input vertical synchronization signal is measured to determine the period L of the PWM reference clock.

[0022]

(Equation 2)

The first frequency dividing circuit 6 divides the pixel clock by L using the period L obtained as described above, thereby obtaining PW
Obtain M reference clock.

The PWM signal generating circuit 7 obtains a PWM cycle Tpwm by dividing the PWM reference clock by n.
That is, (Equation 3) is obtained, and from (Equation 2) and (Equation 3),
(Equation 4)

[0025]

(Equation 3)

[0026]

(Equation 4)

Therefore, the PWM cycle is Tv / m,
It can be seen that the M frequency is m times the vertical synchronization signal frequency.

Further, the PWM signal generation circuit 7 controls the PWM duty ratio of the output pulse based on the PWM duty ratio setting data provided from the outside. Since the PWM cycle is constituted by frequency division using only the number of gradations n, the PWM duty ratio control at the n gradations is easy, and even if the video signal system or the multiplication number changes, the PWM duty ratio setting data is not changed. If it is constant, the PWM duty ratio will be constant.

The backlight driving means 4 controls the brightness of the backlight by turning on the backlight when the PWM pulse is Hi and turning off the backlight when the PWM pulse is Low.

By the above operation, the blinking of the backlight is synchronized at the frequency of m times the vertical synchronizing signal, and even if the noise generated in the backlight driving means 4 leaks into the video signal, the noise component remains on the liquid crystal display screen. The pattern becomes static and hardly noticeable.

Although the brightness of the backlight is controlled by the PWM duty ratio setting data, the brightness of the backlight does not change or the number of gradations does not change even if the video signal system changes.

FIG. 2 is a diagram showing a more specific embodiment of the present invention. FIGS. 3, 4, 5 and 6 are timing charts showing the operation of the embodiment of FIG. The operation of the embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the PWM gradation number n is fixed at 256.

The period detecting circuit 5 includes a second frequency dividing circuit 8 and a third frequency dividing circuit 8.
And a first counting circuit 10. The first pulse counting circuit 10 further includes an incrementer 12b
It consists of an it latch.

First, the operation of the second frequency dividing circuit 8 and the third frequency dividing circuit 9 will be described with reference to FIGS. The second frequency divider 8 divides the pixel clock by 256. Where 2
56 is a value of the PWM gradation number n. Hereinafter, the clock is a pixel clock unless otherwise specified. The second frequency divider 8 is reset by the vertical synchronizing signal. Second frequency divider 8
Outputs a pulse having the same width as the pixel clock cycle once every 256 clocks.

The third frequency dividing circuit 9 enables the output pulse of the second frequency dividing circuit 8 and outputs a pulse having the same width as the pixel clock cycle once every m output pulses. Here, the division ratio m is multiplication ratio setting data provided from the outside.

The third frequency dividing circuit is reset by the vertical period circuit. However, since the output pulse of the second frequency dividing circuit is delayed by one clock from the reset timing by the vertical synchronizing signal, the third frequency dividing circuit is reset. The reset pulse given to the frequency dividing circuit is given with a delay of one clock of the vertical synchronizing signal. The output pulse of the third frequency divider 9 has a cycle of 256 × m clocks.

Next, the operation of the first pulse counting circuit will be described with reference to the timing charts of FIGS.

The incrementer is the third frequency divider 9
Are used as enable pulses, and the number of enable pulses is integrated. The incrementer is set by a vertical synchronization signal. When the incrementer is set, all the internal register outputs become "1". In the 12-bit incrementer, it is FFFh, and it is incremented by the next enable pulse input, and the internal register output is 000h
Becomes That is, the initial value when the incrementer is set is -1, and the operation of counting up from -1 is performed.

The incrementer is set by delaying the reset pulse of the third frequency dividing circuit by one clock with respect to the delay amount of the output pulse of the third frequency dividing circuit. 12bit
The latch holds the output data of the incrementer at the time of input of the next set pulse in a 12-bit register.

As can be seen from FIG. 4, equation (5) holds for L. The natural number L represented by this equation can be measured by the first counting circuit 10.

[0041]

(Equation 5)

However, since the incrementer counts up from -1, the output data of the first counting circuit 10 is not L but L-2. The reason for measuring L-2, in other words, setting the initial value of the incrementer to -1, will be described later.

Using the output data L-2 of the first counting circuit 10, the dividing ratio of the first dividing circuit 6 is determined. FIG. 7 is a circuit diagram of the first frequency divider 6. The operation of the first frequency divider will be described with reference to FIGS. 2, 5, and 7. FIG. The first frequency dividing circuit 6 counts up from 0, counts up to the output data L-2 of the first counting circuit 10, resets itself, counts up from 0 again, and outputs the carry output Co at the same time. Therefore, the first frequency dividing circuit 6 performs an operation of dividing the pixel clock by (L-1). Conversely, when (L-1) frequency division is performed by the circuit configuration shown in FIG. 7, the data from the first counting circuit 10 is not (L-1) but (L-2).
Must be.

Next, referring to FIG. 2, FIG. 5, and FIG.
The operation of the signal generation circuit 7 will be described. Second counting circuit 11
Counts the carry output Co of the first frequency dividing circuit 6. The counting starts from 0, and after counting up to 255, the counting is started again from 0 by self reset. Therefore, the second counting circuit 11 operates as a 256 frequency dividing circuit, and its output cycle is (L−1) × 256 clocks.

The second counting circuit 11 not only operates as a 256 frequency dividing circuit, but its output data is a sawtooth wave having a value between 0 and 255. The comparison circuit 12 compares the output data of the second counting circuit 11 with the PWM duty ratio setting data R. Here, the value of R is 0 to 25
5 When the output data of the second counting circuit 11 ≦ R, the output of the comparing circuit 12 is Hi, and the output of the second counting circuit 1
When the output data of 1> R, the output of the comparison circuit 12 is L
ow.

On the other hand, the PWM signal generating circuit 7 is reset by the vertical synchronizing signal. The output cycle of the second counting circuit 11 is (L−1) × 256, and from (Equation 5), m × (L
-1) × 256 <Tv ≦ m × L × 256, so PWM
The signal generation circuit 7 outputs m pulses during the period of the vertical synchronization signal, and the reset is applied by the vertical synchronization signal in the middle of the (m + 1) th pulse. A period in which the reset by the vertical synchronization signal is performed after the output of the m-th pulse is referred to as a remaining period.

The maximum value of the remainder period is m × 256 clocks. If the video signal is a VGA signal, the pixel clock is 25 MHz, the vertical synchronization signal frequency is 60 Hz, and Tv is 420,000 clocks.

If m = 4, L = 411 and P
The WM cycle is (L-1) × 256 = 104960,
The maximum value of the remainder period is 1024. Therefore, the maximum error of the PWM cycle in a portion where the reset by the vertical synchronization signal occurs is 1% or less. In general, when the fluorescent lamp is subjected to PWM dimming, the lighting duty ratio is set to 10% to 100%. If the lighting duty ratio is 10% or less, the discharge of the fluorescent tube becomes unstable, so that the lighting is not performed or the dimming accuracy cannot be obtained. Since the error due to the remaining period falls within the range of the minimum duty ratio of 10% even when the PWM duty ratio is changed, the PWM frequency does not change due to the remaining period.

However, the first counting circuit 10
In the case where the initial value of the count in is set to 0 and the output of the first counting circuit 10 is set to L-1 instead of L-2, the remainder period becomes a negative value. That is, the PWM signal generation circuit 7
Is reset by the vertical synchronization signal while outputting the m-th pulse. The minimum value of this negative remainder period is −m × 256 clocks. At this time, PWM
Duty ratio setting data R = 255/256 = 99.6
When set to%, PWM pulses filled by a negative remainder period, PWM frequency is not the m multiple of the vertical synchronizing signal, it becomes m-1 multiplication.

However, even in this case, the error of the average value of the PWM duty ratio does not change, so that it does not affect the brightness of dimming. If there is no effect on the screen, or P
In an application in which the maximum value of the WM duty ratio is limited to less than 100%, the output of the first counting circuit 10 is L-
It may be configured to be 1.

Further, in an application in which some error is allowed, the circuit may be configured so that the output of the first counting circuit 10 becomes L or a value close to L.

[0052]

As described above, according to the present invention, the division ratio and the PWM duty ratio setting data are recalculated with a simple circuit even when signals of a plurality of systems having different numbers of lines per frame are input. A liquid crystal display device that can obtain a constant number of PWM gradations and perform fine dimming of the backlight brightness even when signals of a plurality of systems having different numbers of lines per frame are input without the need for It is the purpose.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a timing chart according to the embodiment of the present invention.

FIG. 4 is a timing chart according to the embodiment of the present invention.

FIG. 5 is a timing chart according to the embodiment of the present invention.

FIG. 6 is a timing chart according to the embodiment of the present invention.

FIG. 7 is a block diagram of a first frequency divider according to the embodiment of the present invention;

FIG. 8 is a block diagram of a conventional liquid crystal display device.

FIG. 9 is a block diagram of a PWM signal generation circuit in a conventional liquid crystal display device.

FIG. 10 is a timing chart of a PWM signal generation circuit in a conventional liquid crystal display device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 liquid crystal display panel 2 liquid crystal panel driving means 3 backlight 4 backlight driving means 5 cycle detection circuit 6 first frequency dividing circuit 7 PWM signal generating circuit 8 second frequency dividing circuit 9 third frequency dividing circuit 10 first Counting circuit 11 second counting circuit 12 comparison circuit 13 unit delay element

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-333011 (JP, A) JP-A-10-73801 (JP, A) JP-A-9-265074 (JP, A) JP-A-7- 325286 (JP, A) JP-A-5-127626 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 535 G09G 3/34 G09G 3/36 H05B 37/02 H05B 41/392

Claims (1)

(57) [Claims] 1. A video signal display device using a liquid crystal display panel, wherein when generating a PWM dimming pulse for performing PWM dimming of a backlight, a vertical synchronizing signal of the video signal and the PWM dimming pulse are generated. And the multiplication ratio m (m is a natural number), which is the ratio between the frequency of
A cycle of a clock serving as a reference for generating the M signal is obtained, and the PWM dimming pulse is created from a pixel clock of a video signal based on the cycle, thereby synchronizing with a vertical synchronization signal and having a cycle of 1
/ M PWM dimming liquid crystal display device.