JP3288677B2 - Variable-length code decoding device, digital broadcast receiving device, and DVD playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length code decoding device for decoding a compressed code sequence into a signal before encoding, a digital broadcast receiving device, and a DVD reproducing device.

[0002]

2. Description of the Related Art In recent years, MPEG (Moving Pic)
In particular, techniques for efficiently encoding and compressing an image have been actively researched, such as “Ture Experts Group”. FIG. 29 is a block diagram showing an example of a conventional variable-length code decoding device for decoding a variable-length code. In this figure, a bit stream buffer 1001 acquires a bit stream obtained by encoding a moving image from the outside,
Holds the acquired bit stream. The bit stream cutout unit 1002 includes a bit stream buffer 1
A bit string having the same length as the variable length code having the maximum bit length is extracted from the head of the bit stream stored in 001 and output to the bit length determination unit 1003. The bit length determining unit 1003 detects one code word from the output bit sequence, calculates the bit length of the detected code word, and uses the calculated bit length as the variable length code decoding unit 1004 and the bit stream cutout unit 1002. And the detected codeword is transferred to the variable-length code decoding unit 1004. The bitstream cutout unit 1002 advances the bitstream cutout position by the bit length transferred from the bit length determination unit 1003. The variable-length code decoding unit 1004 refers to a variable-length code table stored in the variable-length code decoding unit 1004, decodes the detected codeword, and executes a run length value (hereinafter, run) and a level. Value (hereinafter, level)
And generate The output control unit 1005 receives the generated run, and controls the output selection unit 1007 to select 0 output from the constant generation unit 1006 by the number of runs when the run is other than 0. Has an output selection unit 1
007 performs control so as to select the level output from the variable length code decoding unit 1004. Buffer 1008
Stores the signal selected by the output selection unit 1007. The inverse quantization unit 1009 reads a value stored in the buffer 1008, inversely quantizes the read value, and generates a block in the spatial frequency domain. Note that the method of detecting one codeword from a bit string by the bit length determination unit 1003 is described in “ISO / IEC 13818-
2 (ISO / IECJTC1, issued by ISO / IEC on March 31, 1995), which is publicly known and will not be described here.

[0003]

However, in the variable-length code decoding apparatus described above, since the preceding code is sequentially read and decoded, it takes a very long time to decode the variable-length code, However, there is a problem that a decrease in the processing speed of the decoding of the system causes a decrease in the processing speed of the entire system. To solve this, the entire system can be operated at a higher operating frequency to avoid a reduction in the processing speed of the entire system, but the operation at a high operating frequency increases the cost of the apparatus and increases power consumption. Connect.

[0004] In order to solve the above problems, the present invention provides a variable length code decoding device, a digital broadcast receiving device, and a digital broadcast receiver capable of decoding more variable length codes within a fixed time.
It is intended to provide a D playback device.

[0005]

[0006]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In addition, the present invention provides a variable length code decoding for decoding a variable length code.
A device, wherein two compressed code strings are adjacent to each other.
Code extracting means for simultaneously or sequentially extracting code words of
The compressed code string is composed of a sequence of a plurality of code words.
The code word is a variable length code, and the two codes
And a parallel decoding means for decoding in parallel a word, before Symbol compression code string, the signal is quantized and further comprising at least two codewords generated are entropy coded, the signal has a plurality of Generated by performing orthogonal transformation on image information,
The code extracting unit extracts two codewords generated from the image information, the two codewords are adjacent to each other, and the parallel decoding unit performs entropy processing of the two codewords in parallel. Code decoding means for generating two sets of coefficients by decoding, and a signal for generating two sets of signals in parallel by performing inverse quantization based on the two sets of generated coefficients. It is configured to include a recovery unit
It is.

Here, the variable-length code decoding device further includes selection accepting means for accepting selection of one of the decoding of the first compressed code sequence or the decoding of the first and second compressed code sequences, Here, the first compression code string is the compression code string, the second compression code string is another compression code string,
Consists of a sequence of multiple codewords, the signal is quantized,
In addition, the signal includes at least two code words generated by entropy coding, the signal is generated by performing orthogonal transform on a plurality of pieces of image information, and the code cutout means selects decoding of the first compressed code string. Is received, two adjacent codewords are cut out from the first compression code string, and when the selection of decoding the first and second compression code strings is received,
One code word may be cut out from each of the first and second compressed code strings, and the code decoding means may be configured to perform entropy decoding on the cut out two code words in parallel.

Here, the compressed code string includes at least two codewords generated by quantizing a signal and further entropy coding, and generating the signal by performing orthogonal transform on a plurality of pieces of image information. The code extracting means cuts out two code words generated from the image information,
Codewords are adjacent to each other and each have a code length equal to or less than a third predetermined value, and the parallel decoding means performs entropy decoding on the two codewords using one decoding table, Code decoding means for generating two sets of coefficients, and signal restoring means for generating two sets of signals in parallel by performing inverse quantization based on the two sets of generated coefficients. It may be configured as follows.

Here, the compression code string has at least 2
The same type of control information includes the same number of types of encoded control information, each of which is entropy-coded, and the control information is used to control decoding of image data. As a word, two adjacent pieces of coding control information are cut out from the compressed code string, and the parallel decoding unit performs entropy decoding on the two pieces of coding control information in parallel, thereby obtaining two pieces of coding control information. It may be configured to include code decoding means for generating control information.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1 A variable-length code decoding device 10 as one embodiment according to the present invention will be described. 1.1 Configuration of Variable Length Code Decoding Device 10 The configuration of the variable length code decoding device 10 will be described with reference to the block diagram shown in FIG.

The variable length code decoding apparatus 10 includes a first bit stream buffer 101, a first bit stream cutout section 102, a first bit length determination section 103, and a first decoding section 10.
4, a first address calculation unit 105, a second bit stream cutout unit 106, a second bit length determination unit 107, a second decoding unit 108, a second address calculation unit 109, a first buffer controller 118, a first buffer 119, It comprises a first inverse quantization unit 120, a second inverse quantization unit 121, a second buffer controller 122, and a second buffer 123. 1.1.1 First Bit Stream Buffer 101 The first bit stream buffer 101 is connected to an optical disk device, and stores a moving image bit stream from an optical disk medium in which a moving image bit stream compressed by the MPEG system is recorded. Among them, 4096 bytes are sequentially and repeatedly read, and the read bit stream of 4096 bytes is stored as partially compressed data.

A bit stream of a moving image compressed by the MPEG system is broadcast as a digital broadcast wave, and the first bit stream buffer 101 receives the digital broadcast wave and converts the received digital broadcast wave into four bits.
A bit stream of 096 bytes may be extracted and stored. 1.1.2 First Bitstream Extraction Unit 102 The first bitstream extraction unit 102 stores a data read position. The data read position indicates the bit position from the head of the partially compressed data stored in the first bit stream buffer 101 by the number of bits.

The first bit stream cutout unit 102 extracts a 48-bit bit string from the bit position indicated by the data read position out of the partial compressed data stored in the first bit stream buffer 101, and The extracted first bit string is used as a 1-bit length determination section 103 and a second bit stream extraction section 1
06.

The first bit stream cutout unit 102 stores the four bit streams stored in the first bit stream buffer 101.
The extraction of the bit string of 48 bits is repeated until the extraction of all the bit strings from the partial compressed data of 096 bytes is completed. Here, the bit length of the first bit string to be extracted is twice as long as the maximum length variable length code so as to include at least two code words. The maximum length of the variable length code is 24 bits. Therefore, the first bit string has a length twice as long as the maximum length of the variable length code, and its length is 48 bits.

The initial value of the data reading position is 0,
The top position of the partially compressed data stored in the first bit stream buffer 101 is shown. The first bit stream cutout unit 102 receives the code bit length from the second bit length determination unit 107, adds the received code bit length to the stored data read position, and newly reads the addition result. Store as position. 1.1.3 First Bit Length Determination Unit 103 The first bit length determination unit 103 receives a 48-bit first bit string from the first bit stream cutout unit 102,
One codeword from the beginning of the received first bit string is
The first codeword is detected as a codeword, and the bit length of the detected first codeword is calculated as the first bitlength.

The first bit length determining section 103 outputs the calculated first bit length to the first decoding section 104, the second bit stream cutout section 106, and the second bit length determining section 107,
Further, it outputs the detected first codeword to first decoding section 104. The process of detecting one codeword from a bit string is well known and will not be described in detail. 1.1.4 First Decoding Unit 104 The first decoding unit 104 includes a first decoding control unit 151, a fixed table 152, and an associative memory 153, as shown in FIG. The associative memory 153 stores the first table 154.
And a second table 155. (1) Fixed Table 152 As shown in FIG.
9 is a data table having a plurality of areas storing sets of the data and the level 162. An address 160 is assigned to an area where each set is stored. Address 160 is an address of 8 bits or less. Each address 160 is a variable-length code obtained by encoding a set of a run 161 and a level 162 stored in an area indicated by the address 160. (2) First Table 154 As shown in FIG.
64 is a data table having a plurality of areas storing 64, and an address 164 indicates an address of each area of the second table 166. An address 163 is assigned to an area where each address 164 is stored. The address 163 is an address of 9 bits or more and 24 bits or less. (3) Second Table 155 As shown in FIG.
9 is a data table having a plurality of areas storing sets of a set and a level 167. An address 165 is assigned to an area where each set is stored.

The number of areas in the first table 154 is equal to the number of areas in the second table 155.
Each area of the first table 154 corresponds to each area of the second table 155. Each address 163 of the first table 154 is stored in the second table 155.
Is a variable-length code obtained by encoding a set of a run 166 and a level 167 stored in an area indicated by one address. Here, the one address is the address 164 stored in the area indicated by the address 163. (4) First Decoding Control Unit 151 The first decoding control unit 151 receives the first bit length and the first codeword from the first bit length determining unit 103.

The first decoding control unit 151 receives the received first
Whether the bit length is less than or equal to 8;
Or, it is determined whether it is larger than 8. First decryption control unit 15
1 regards the received first codeword as the address 160 of the fixed table 152 when determining that the received first bit length is smaller than or equal to 8;
The set of the run 161 and the level 162 stored in the area indicated by the address 160 of the fixed table 152 is extracted. In this way, the first codeword is decoded, and a set of the run 161 and the level 162 corresponding to the first codeword is generated. Next, the first decoding control unit 151 outputs the extracted run 161 as the first run to the first address calculation unit 105 and the second address calculation unit 109, and sets the extracted level 162 as the first level to the first level. Output to the inverse quantization unit 120.

The first decryption control section 151 receives the received first
If it is determined that the bit length is larger than 8, the received first codeword is stored in the address 163 of the first table 154.
And the address 164 stored in the area of the first table 154 indicated by the address 163 is extracted. Next, the extracted address 164 is regarded as the address 165 of the second table 155, and the second table 15
5, a set of the run 166 and the level 167 stored in the area indicated by the address 165 is taken out. In this way, the first codeword is decoded, and a set of a run 166 and a level 167 corresponding to the first codeword is generated. The first decoding control unit 151 outputs the extracted run 166 as a first run to the first address calculation unit 105 and the second address calculation unit 109, and outputs the extracted level 167.
Is output to the first inverse quantization unit 120 as the first level. 1.1.5 Second Bitstream Extraction Unit 106 The second bitstream extraction unit 106 receives the 48-bit first bit string from the first bitstream extraction unit 102, Receive 1 bit length.

The second bit stream cutout unit 106 generates a second bit sequence by removing the received bit sequence of the first bit length from the beginning of the received 48-bit first bit sequence as a second bit sequence. Output to bit length determination section 107. 1.1.6 Second Bit Length Determination Unit 107 The second bit length determination unit 107 receives the second bit string from the second bit stream cutout unit 106, and extracts one codeword from the beginning of the received second bit string. Detected as two code words, and calculate the bit length of the detected second code word as the second bit length. Here, second bit length determining section 107
Detects one codeword as a second codeword from all types of codewords used when encoding image information.

The second bit length determining section 107 receives the first bit length from the first bit length determining section 103. The second bit length determining unit 107 adds the received first bit length and the calculated second bit length to obtain a code bit that is an addition value of the bit lengths of the first codeword and the second codeword. The length is calculated, and the calculated code bit length is output to first bit stream cutout section 102.

The second bit length determining section 107 determines the calculated second bit length and the detected second codeword by a second decoding section 108.
Output to The process of detecting one codeword from a bit string is well known and will not be described in detail. 1.1.7 Second Decoding Unit 108 The second decoding unit 108 has the same configuration as the first decoding unit 104.

The second decoding unit 108 receives the second bit length and the second codeword from the second bit length determination unit 107, decodes the second codeword in the same manner as the first decoding unit 104,
Generate a second run and a second level corresponding to the second codeword. The second decoding unit 108 outputs the second run to the first address calculation unit 105 and the second address calculation unit 109,
The level is output to second inverse quantization section 121. 1.1.8 First Address Calculation Unit 105 The first address calculation unit 105 receives a first run from the first decoding unit 104 and a second run from the second decoding unit 108.

The first address calculation unit 105 stores all of the received first and second runs together with the order in which they were received during decoding within one block. The first address calculation unit 105 calculates the received first
A coordinate value T indicating a position where the first level generated as a pair with the run is placed in one block is calculated. The first address calculation unit 105 outputs the calculated coordinate value as a first address to the first inverse quantization unit 120 and the second buffer controller 122.

Here, one block is a group of a total of 64 elements including eight elements in the horizontal direction and eight elements in the vertical direction. The coordinate value of the position where each element of one block is placed is, in order from left to right, for the first eight horizontal elements of one block, and then the second eight horizontal elements of one block. Are counted in the same order from left to right in the following order, the coordinate value of the upper left position of one block is set to 0, and 1 is added to the immediately preceding coordinate value in the above order. The value obtained is the coordinate value of the position.

[0026]

(Equation 1)

Here, T is a coordinate value indicating a position where the first level is placed in the block. Zig ()
Indicates the order by zigzag scan from the left to right,
This is a function to convert from top to bottom. R _i is the first run or the second run received by the first address calculation unit 105 at the time of the i-th decoding by the first decoding unit 104 or the second decoding unit 108 in decoding within one block. n
In the decoding within one block, the first decoding unit 104 or the second decoding unit 108 until the last first run is received.
Is the cumulative number of times of decoding.

FIG. 4 shows the order of the zigzag scan. In this figure, 64 circle marks indicate elements for one block. The numbers attached to the lower right of the circle and the arrows in the figure indicate the order of the zigzag scan. The zigzag scan, as shown by the arrow in this figure,
DC, AC1, AC8, AC16, AC9,..., A
C61, AC54, AC47, AC55, AC62, A
It is repeated in the order of C63.

FIG. 5 shows an element number j of an element of one block.
6 is a table showing a correspondence between a zigzag function Zig (j) that returns a number in the zigzag scan order for an element number j.
Here, the element number j is based on the order from left to right and top to bottom. In FIG. 6, table 610 contains:
As an example, in decoding in one block, seven codewords are decoded by the first decoding unit 104 or the second decoding unit 108, and the generated seven sets of runs and levels are shown.

In this figure, Table 650 contains 1
This is a coordinate value at which an element is placed in the block, and indicates a coordinate value in the order from left to right and top to bottom. Table 640 shows the coordinate values at which the elements are placed in one block, which are in the order of the zigzag scan. In this figure,
Table 620 shows that for each of the seven generated levels, Equation 1
Shows the coordinate values calculated using.

Further, in this figure, Table 630 includes:
The generated seven levels and a plurality of “0” values are 1
Fig. 3 shows an example arranged on a block. In Table 630, it can be seen that the values of the levels shown in Table 620 are arranged at the positions indicated by the corresponding coordinate values. 1.1.9 Second Address Calculation Unit 109 The second address calculation unit 109 receives the first run from the first decoding unit 104 and receives the second run from the second decoding unit 108.

Similarly to the first address calculation unit 105, the second address calculation unit 109 uses Equation 1 to generate the second level generated as one set with the received second run by one block. Calculates the coordinate value indicating the position where it is placed inside. The second address calculation unit 109 outputs the calculated coordinate value as a second address to the second inverse quantization unit 121 and the second buffer controller 122. 1.1.10 First Dequantization Unit 120 The first dequantization unit 120 calculates the first level output from the first decoding unit 104 and the first address output from the first address calculation unit 105. receive.

The first inverse quantization section 120 has a quantization table 700 shown in FIG. Quantization table 700
Is a total of 64 in the horizontal direction and 8 in the vertical direction.
It is a set of coefficients Q _uv . First inverse quantization unit 120
Extracts the coefficient Q _uv located at the position indicated by the first address from the quantization table 700, and calculates the first DCT coefficient using Expression 2. (Equation 2) (first DCT coefficient) = (first level) × (first DCT coefficient)
The coefficient Q _{uv at the} position indicated by the address) The first inverse quantization unit 120 calculates the calculated first DCT coefficient as
Output to the second buffer controller 122.

Here, DCT is a type of orthogonal transform. 1.1.11 Second Dequantization Unit 121 The second dequantization unit 121 calculates the second level output from the second decoding unit 108 and the second address output from the second address calculation unit 109. receive. Second inverse quantization unit 12
1 has a quantization table 700 shown in FIG. 7 similarly to the first inverse quantization unit 120.

The second inverse quantization unit 121 extracts the coefficient Q _uv located at the position indicated by the second address from the quantization table 700, and calculates the second DCT coefficient using Expression 3. (Equation 3) (second DCT coefficient) = (second level) × (second DCT coefficient)
The coefficient Q _{uv at the} position indicated by the address) The second inverse quantization unit 121 calculates the calculated second DCT coefficient as
Output to the second buffer controller 122.

Note that the second inverse quantization section 121 may not include a quantization table and use the quantization table of the first inverse quantization section 120. 1.1.12 Second Buffer 123 The second buffer 123 has a first buffer address and DCT
This is a data storage buffer having a maximum of 64 areas for storing sets of coefficients.

The area for storing the first buffer address is
The area for storing the DCT coefficient is composed of 64 bytes.
Since it is composed of 6 bytes, the second buffer 123 has a total storage capacity of 160 bytes. 1.1.13 Second Buffer Controller 122 The second buffer controller 122 receives the first address from the first address calculation unit 105 and receives the first DCT coefficient from the first inverse quantization unit 120. The second buffer controller 122 receives the first address from the first address calculation unit 105, and receives the first address from the first inverse quantization unit 120.
When the DCT coefficient is received, the set of the first address and the first DCT coefficient is stored in the second buffer 123 from the head of the unwritten area in the first buffer address and the DCT coefficient.
Write as T coefficient.

The second buffer controller 122
Receives the second address from the second address calculation unit 109 and the second DCT coefficient from the second inverse quantization unit 121. When the second buffer controller 122 receives the second address from the second address calculation unit 109 and receives the second DCT coefficient from the second inverse quantization unit 121, the second buffer controller 122 stores the set of the second address and the second DCT coefficient in the second buffer. 123
In this case, the first buffer address and the DCT coefficient are written from the head of the unwritten area.

The second buffer controller 122 has the first
In response to an instruction from the buffer controller 118, all sets of first buffer addresses and DCT coefficients stored in the second buffer 123 are sequentially read from the head position of the second buffer 123, and the read first buffer addresses and The first buffer controller 11
8 is output.

The second buffer controller 122 has a second
When the reading of all sets of the first buffer address and the DCT coefficient stored in the buffer 123 and the output to the first buffer controller 118 are completed, all the contents stored in the second buffer 123 are deleted. . Second
The buffer controller 122 stores the first address and the first D
The CT coefficient, the second address and the second DCT coefficient can be received at the same time. Therefore, the first inverse quantization unit 120
Does not wait for the completion of the output of the second inverse quantization unit 121,
The DCT coefficient can be output to the second buffer controller 122. The same applies to the second inverse quantization unit 121. 1.1.14 First Buffer 119 The first buffer 119 has 6 areas for storing DCT coefficients.
This is a data storage buffer having four.

Since one DCT coefficient consists of 12 bits, the first buffer 119 has a total storage capacity of 96 bytes. The first buffer 119 is connected to an external connection device. The external connection device reads the DCT coefficient stored in the first buffer 119. 1.1.15 First Buffer Controller 118 The first buffer controller 118 starts the processing of the image information for one block after the external connection device has read all the values of the first buffer 119. , 0 is written to the entire area of the first buffer 119.

Thereafter, the first buffer controller 11
8 outputs to the second buffer controller 122 an instruction to output a set of the first buffer address and the DCT coefficient.
The first buffer controller 118 stores a set of the first buffer address and the DCT coefficient in the second buffer controller 1.
22 and sequentially writes the same set of DCT coefficients as the first buffer address in the area of the first buffer 119 indicated by the first buffer address for each set of the received first buffer address and DCT coefficient. 1.2 Operation of Variable Length Code Decoding Device 10 The operation of the variable length code decoding device 10 will be described. 1.2.1 Overall Operation of Variable-Length Code Decoding Apparatus 10 FIG.
This will be described with reference to the flowchart shown in FIG.

In the variable length code decoding apparatus 10, the first
Bit stream cutout unit 102, first bit length determination unit 1
03, a first decryption unit 104, a first address calculation unit 105,
The operation by the first inverse quantization unit 120 is collectively referred to as a first system operation for convenience, and the second bit stream extraction unit 10
6. The operations performed by the second bit length determination unit 107, the second decoding unit 108, the second address calculation unit 109, and the second inverse quantization unit 121 are collectively referred to as a second system operation for convenience. (1) Operation of First System The first bit stream cutout unit 102 extracts a bit sequence of 48 bits from the bit position indicated by the data read position in the first bit stream buffer 101 to obtain a first bit sequence, and extracts the bit sequence. The first bit sequence is output to the first bit length determination unit 103 (step S70).
1) Output the extracted first bit string to the second bit stream cutout unit 106 (step S706).

The first bit length determining section 103 receives the 48-bit first bit string from the first bit stream cutout section 102, and detects one codeword from the head of the received first bit string as the first codeword. , The bit length of the detected first codeword is calculated as the first bit length, and the calculated first
The bit length is output to first decoding section 104, and the detected first codeword is output to first decoding section 104 (step S7).
02), outputs the calculated first bit length to the second bit stream cutout unit 106 (step S707), and outputs the calculated first bit length to the second bit length determination unit 107 (step S708).

The first decoding control unit 151 of the first decoding unit 104
Receives the first bit length and the first codeword from the first bit length determination unit 103, decodes the first run and the first level using the first bit length and the first codeword, The first run is performed by the first address calculator 105 and the second address calculator 109.
And the first level is output to the first inverse quantization unit 120 (step S703).

The first address calculation unit 105 determines that the first level generated as a set with the received first run is
A coordinate value indicating a position placed in one block is calculated as a first address and output to the first inverse quantization unit 120 and the second buffer controller 122 (step S70).
4). The first inverse quantization unit 120 receives the first level and the first address, calculates a first DCT coefficient using the quantization table 700 (step S705), and stores the calculated first DCT coefficient in the second buffer controller. 122 (step S709). (2) Operation of Second System The second bit stream cutout unit 106 receives the 48-bit first bit string from the first bit stream cutout unit 102 (step S706), and receives the first bit length determination unit 10.
3 is received (step S707).
From the beginning of the received 48-bit first bit string,
The remaining bit strings from which the received bit strings of the first bit length have been removed are output as second bit strings to the second bit length determining unit 107 (step S721).

The second bit length determining unit 107 receives the first bit length from the first bit length determining unit 103 (step S708), receives the second bit string from the second bit stream cutout unit 106, and One code word from the head of the bit string is detected as a second code word, the bit length of the detected second code word is calculated as a second bit length, and the calculated second bit length and the detected second code word are calculated. The output to the second decoding unit 108 (step S722), the second bit length determination unit 107 calculates the code bit length, outputs the calculated code bit length to the first bit stream cutout unit 102, and outputs the first bit The stream cutout unit 102 receives the code bit length from the second bit length determination unit 107, adds the received code bit length and the stored data read position, and newly It is stored as data read position (step S726).

The second decoding unit 108 receives the second bit length and the second codeword from the second bit length determination unit 107, decodes the second codeword, and executes a second run corresponding to the second codeword. And the second level are generated, the second run is output to the first address calculator 105 and the second address calculator 109, and the second level is output to the second inverse quantizer 121 (step S7).
23).

The second address calculation unit 109 receives the first run from the first decoding unit 104, receives the second run from the second decoding unit 108, and is generated as a set with the received second run. The second level calculates a coordinate value indicating a position to be placed in one block as a second address,
Inverse quantization section 121 and second buffer controller 122
(Step S724).

The second inverse quantization section 121 is configured to output the second
8 and the second address calculation unit 1
09, the second DCT coefficient is calculated using the quantization table 700 (step S725), and the calculated second DCT coefficient is output to the second buffer controller 122 (step S72).
7). (3) Operation of Second Buffer Controller 122 The second buffer controller 122 receives the first address from the first address calculation unit 105 and the first DCT coefficient from the first inverse quantization unit 120 (Step S70).
9) Also, the second buffer controller 122
The second address is received from the address calculation unit 109, the second DCT coefficient is received from the second inverse quantization unit 121 (step S727), and the set of the first address and the first DCT coefficient is written in the second buffer 123 in the second buffer 123. From the head of the unwritten area, the first buffer address and the DCT coefficient are written as the first buffer address, and the set of the second address and the second DCT coefficient is written in the second buffer 123 from the head of the unwritten area to the first buffer. The address and the DCT coefficient are written (step S741).

The second buffer controller 122
Receives the instruction from the first buffer controller 118 (step S765), and starts all the first buffers stored in the second buffer 123 from the head position of the second buffer 123.
The set of the buffer address and the DCT coefficient is sequentially read (step S742), and the read set of the first buffer address and the DCT coefficient is read into the first buffer controller 11.
8 (step S743). The second buffer controller 122 receives all first buffer addresses and DC
Reading of a set with T coefficient and first buffer controller 1
The reading and the output are repeated until the output to 18 ends (step S744).

Further, the second buffer controller 122
When the reading of all sets of the first buffer address and the DCT coefficient stored in the second buffer 123 is completed, all the contents stored in the second buffer 123 are deleted (step S745). (4) Operation of the first buffer controller 118 The first buffer controller 118 executes the first buffer controller 118 after the external connection device has finished reading all the values of the first buffer 119 and at the beginning of the processing for one block. Buffer 11
0 is written in all areas of No. 9 (step S761).

Thereafter, the first buffer controller 11
8 outputs an instruction to output a set of the first buffer address and the DCT coefficient to the second buffer controller 122 (step S762). First buffer controller 11
8 is a combination of the first buffer address and the DCT coefficient in the second
The received first buffer address and DC are sequentially received from the buffer controller 122 (step S743).
The same set of DCT coefficients is written to the area of the first buffer 119 indicated by the first buffer address for each set of T coefficients (step S763).

The first buffer controller 118 has a first
Until the reception of the set of the buffer address and the DCT coefficient is completed, the reception and the writing of the set of the first buffer address and the DCT coefficient are repeated (step S764). 1.2.2 Operation of First Bitstream Extraction Unit 102 The operation of the first bitstream extraction unit 102 will be described with reference to the flowchart shown in FIG.

The first bit stream cutout unit 102 sets the initial value of the data read position to 0 (step S90).
1). The first bit stream cutout unit 102 extracts a 48-bit bit string from the bit position indicated by the data read position out of the partial compressed data stored in the first bit stream buffer 101, and
The extracted first bit sequence is output to the first bit length determination unit 103 and the second bit stream cutout unit 106 (step S903).

The first bit stream extracting unit 102
Receives the code bit length from the second bit length determination unit 107 (step S904), adds the received code bit length to the stored data read position, and stores the addition result as a new data read position. (Step S9
05). The first bit stream cutout unit 102 stores the 409 data stored in the first bit stream buffer 101.
The extraction of the bit string of 48 bits is repeated until the extraction of all the 6-byte partial compressed data is completed (step S906). 1.2.3 Operation of First Bit Length Determination Unit 103 The operation of the first bit length determination unit 103 will be described with reference to the flowchart shown in FIG.

The first bit length determining section 103 receives the 48-bit first bit string from the first bit stream cutout section 102 (step S921), and assigns one codeword from the head of the received first bit string to the first code string. (Step S922), the bit length of the detected first code word is calculated as the first bit length (step S923), and the calculated first bit length is extracted from the first decoding unit 104 and the second bit stream. And outputs the detected first codeword to the first decoding unit 104.
(Step S924). 1.2.4 First Decoding Control Unit 151 of First Decoding Unit 104
Operation of the first decoding control section 151 of the first decoding section 104 will be described with reference to the flowchart shown in FIG.

First decoding control section 151 of first decoding section 104
Receives the first bit length and the first codeword from the first bit length determining unit 103 (step S941), and determines whether the received first bit length is smaller than 8, equal to 8, or Is larger than the first received
When it is determined that the bit length is smaller than or equal to 8 (step S942), the received first codeword is regarded as the address 160 of the fixed table 152, and
The set of the run 161 and the level 162 stored in the area indicated by the address 160 of the fixed table 152 is extracted (step S943), and the extracted run 1
61 is set as the first run, and is output to the first address calculation unit 105 and the second address calculation unit 109, and the extracted level 162 is output to the first inverse quantization unit 120 as the first level (step S944).

The first decryption control section 151 receives the received first
When it is determined that the bit length is larger than 8 (step S942), the received first codeword is stored in the first table 1
The address 164 stored in the area indicated by the address 163 of the first table 154 is extracted (step S945), and the extracted address 164 is regarded as the address 165 of the second table 155. Then, a set of the run 166 and the level 167 stored in the area indicated by the address 165 of the second table 155 is taken out (step S9).
46), taking the run 166 taken out as the first run,
The data is output to the address calculator 105 and the second address calculator 109, and the extracted level 167 is output as the first level to the first inverse quantization unit 120 (step S947). 1.2.5 Operation of First Address Calculator 105 The operation of the first address calculator 105 will be described with reference to the flowchart shown in FIG.

The first address calculation unit 105 receives the first run from the first decoding unit 104, receives the second run from the second decoding unit 108 (step S961), and receives the first run in the decoding within one block. The run and the second run are all stored together with the order in which they were received (step S962), and the first address calculation unit 105 is generated using Expression 1 as one set with the received first run. A coordinate value indicating a position where the first level is placed in one block is calculated as a first address (step S963),
The first address is output to the first inverse quantization unit 120 and the second buffer controller 122 (Step S964). 1.2.6 Operation of First Inverse Quantization Unit 120 The operation of the first inverse quantization unit 120 will be described with reference to the flowchart shown in FIG.

[0061] The first inverse quantization unit 120 is configured to
4 and the first address calculation unit 1
05 (step S981), the coefficient Q _uv located at the position indicated by the first address is extracted from the quantization table 700 (step S982), and One DCT coefficient is calculated (step S983), and the calculated first DCT coefficient is output to the second buffer controller 122 (step S984). 1.2.7 Operations of Other Components The second bit stream cutout unit 106, the second bit length determination unit 107, the second decoding unit 108, the second address calculation unit 10
9. Regarding each operation of the second inverse quantization unit 121, the first bit stream cutout unit 102, the first bit length determination unit 10
3, the operations are the same as those of the first decoding unit 104, the first address calculation unit 105, and the first inverse quantization unit 120, and a description thereof will be omitted. 1.3 Transition with Time of Variable-Length Code Decoding Apparatus 10 Transition of processing of each component with time in variable-length code decoding apparatus 10 for decoding for each codeword is shown in the time chart of FIG. It will be described using FIG.

In this time chart, in the vertical direction,
A first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103,
Decoding section 104, first address calculation section 105, first inverse quantization section 120, second bit stream cutout section 106, second
Each of the bit length determination unit 107, the second decoding unit 108, the second address calculation unit 109, the second inverse quantization unit 121, the second buffer controller 122, the second buffer 123, the first buffer controller 118, and the first buffer 119 The processing units are listed, and the processing of each processing unit over time is shown in the horizontal direction.

In this time chart, processing C50
Reference numeral 1 denotes processing by the first bit stream buffer 101. The processes C502 to C508 are respectively performed by the first bit stream cutout unit 102, the first bit length determination unit 103, the first decoding unit 104, and the first address calculation unit 10.
5 shows processing by the first inverse quantization unit 120, the second buffer controller 122, and the second buffer 123.
The same applies to processes C521 to C527 and processes C541 to C547. The processes C511 to C517 are respectively performed by the second bit stream cutout unit 106, the second bit length determination unit 107, the second decoding unit 108, the second address calculation unit 109, the second inverse quantization unit 121, and the second buffer controller 122. , The processing by the second buffer 123. Processing C531-C537 and Processing C551-C55
7 is the same. Processes C561 and C562 are:
The processing by the first buffer controller 118 and the first buffer 119 is shown, respectively.

It should be noted that in this time chart, the horizontal direction indicates the passage of time, but does not indicate an absolute time. As shown in this time chart, after the processing C501 ends, the processing C502
To C508 operate in this order. Processing C503
After the end, the processes C511 to C517 operate in this order. Next, after the end of the process C512, the processes C521 to C52
7 operate in this order. The following is the same. When the last process C557 ends, C561 and C562 operate in this order. 1.4 Conclusion According to the embodiment shown here, since there are two systems of “decoding unit, address calculating unit, and inverse quantization unit”, one system of the variable length code in the bit stream is used. In this case, it is possible to decode more variable-length codes per fixed time than when decoding, address calculation, and inverse quantization. This is effective when processing a large image.

Since the variable length code decoding tables of the first decoding unit and the second decoding unit have a two-stage structure of a fixed table and an associative memory, the variable length code decoding table is realized by one table. As compared with the case, the size of the table can be reduced. Further, since the second buffer controller 122 and the second buffer 123 are provided, the second buffer controller 122
Address, first DCT coefficient, second address, second DCT
And the T coefficient can be received at the same time. Therefore, the first
The inverse quantization unit 120 can output the first DCT coefficient to the second buffer controller 122 without waiting for the output completion of the second inverse quantization unit 121. The same applies to the second inverse quantization unit 121.

Further, since the first buffer controller 118 and the first buffer 119 are provided, the variable length code can be used regardless of the processing speed of the external device and without depending on the processing timing of the external device. The DCT coefficients decoded by the decoding device can be written to the first buffer 119. 2. Embodiment 2 A variable-length code decoding device 20 as another embodiment according to the present invention will be described. 2.1 Configuration of Variable Length Code Decoding Device 20 The configuration of the variable length code decoding device 20 will be described with reference to block diagrams shown in FIGS.

The variable length code decoding device 20 includes a first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103, and a first decoding unit 10.
4, a first address calculation unit 105, a second bit stream cutout unit 106, a second bit length determination unit 107, a second decoding unit 108, a second address calculation unit 109, a first buffer controller 118, a first buffer 119, First inverse quantizer 120, second inverse quantizer 121, second buffer controller 122, second buffer 123, second bit stream buffer 110, first bit length selector 111, bit stream selector 112, second Bit length selection unit 113,
First constant generator 114, third bit length selector 115, second constant generator 116, third constant generator 124, first position information selector 125, second position information selector 117, first buffer selector 126, the second buffer selector 127, the fourth
Buffer controller 128, fourth buffer 131, third buffer controller 129, third buffer 130,
It comprises a selection receiving unit 141 and a state storage unit 142.

The components denoted by the same reference numerals as those of the variable-length code decoding device 10 are the same components.
Hereinafter, newly added components will be described. Also, with respect to components having the same reference numerals as the components of the variable-length code decoding device 10, portions different from the components of the variable-length code decoding device 10 will be described. The variable-length code decoding device 20 has one of two states in advance. The first state is a state in which one bit stream is decoded, similarly to the variable-length code decoding device 10. The second state is a state where two different bit streams are respectively decoded. 2.1.1 Selection Receiving Unit 141, State Storage Unit 142 The selection receiving unit 141 receives a selection of the first state or the second state from the user, and outputs the received selection to the state storage unit 142.

The state storage unit 142 receives the selection of the first state or the second state from the selection receiving unit 141, and stores one of the states. 2.1.2 Second Bitstream Buffer 110 The second bitstream buffer 110 reads and stores a moving image bitstream different from the moving image bitstream read and stored by the first bitstream buffer 101. are doing. For others,
The description is omitted because it is the same as the bit stream buffer 101. 2.1.3 First bit stream cutout unit 102 The first bit stream cutout unit 102 receives the code bit length from the second bit length determination unit 107,
The code bit length or the first bit length is received from the bit length selection unit 111, the received code bit length or the first bit length is added to the stored data read position, and the addition result is newly set as the data read position. Remember. 2.1.4 First Bit Length Determining Unit 103 The first bit length determining unit 103 converts the calculated first bit length into a first decoding unit 104 and a second bit stream cutout unit 106.
Instead of outputting the calculated first bit length to the first decoding unit 104, the first bit length selection unit 111, the second bit length selection unit 113, and the third bit length selection unit 115 and output. 2.1.5 First Decoding Control Unit 151 of First Decoding Unit 104 The first decoding control unit 151 of the first decoding unit 104 outputs the second run to the second address calculation unit 109 instead of outputting the first run to the second address calculation unit 109.
Output to position information selection section 117. 2.1.6 Second Bitstream Extraction Unit 106 The second bitstream extraction unit 106 receives the first bit string of 48 bits from the bitstream selection unit 112 in the case of the first state, and has a second bit length. The first bit length is received from the selection unit 113.

In the first state, the second bit stream cutout unit 106 removes, from the beginning of the received 48-bit first bit sequence, the remaining bit sequence obtained by removing the received bit sequence of the first bit length. Is output to the second bit length determination unit 107 as a second bit sequence. The second bit stream cutout unit 106 stores a second data read position. The second data read position indicates the bit position from the head of the partially compressed data stored in the second bit stream buffer 110 by the number of bits.

In the second state, in the second state, the second bit stream cutout unit 106 outputs the second bit stream among the partial compressed data stored in the second bit stream A bit sequence of 24 bits is extracted from the bit position indicated by the data read position, and the extracted bit sequence is output to the second bit length determination unit 107 as a second bit sequence.

In the second state, the second bit stream cutout unit 106
Until the extraction of all the bit strings from the partial compressed data of 4096 bytes stored in is completed, the extraction of the bit strings of 24 bits is repeated. Here, the bit length of the extracted bit string is set to the maximum length of the variable length code so as to include at least one code word. The maximum length of the variable length code is 24 bits. Therefore,
The bit string has a length equal to the length of the maximum length variable length code, and its length is 24 bits.

The initial value of the second data read position is 0, indicating the head position of the partially compressed data stored in the second bit stream buffer 110. In the second state, the second bit stream cutout unit 106
The code bit length is received from the bit length selection unit 113, the received code bit length is added to the stored second data read position, and the addition result is newly stored as the second data read position. 2.1.7 Second Bit Length Determination Unit 107 The second bit length determination unit 107
3, instead of receiving the constant 0 or the first bit length from the third bit length selection unit 115,
The received constant 0 or the first bit length is added to the calculated second bit length to calculate a code bit length which is an added value of the bit lengths of the first code word and the second code word. 2.1.8 Second Decoding Unit 108 The second decoding unit 108 converts the second run into the first address calculation unit 1
The second run is output to the first position information selector 125 and the second address calculator 109 instead of being output to the second address calculator 105 and the second address calculator 109. 2.1.9 First Bit Length Selection Unit 111 The first bit length selection unit 111 reads the first state or the second state stored in the state storage unit 142.

In the first state, the first bit length selecting section 111 receives the code bit length output from the second bit length determining section 107 and outputs the first bit stream
Output to 2. In the case of the second state, the first bit length output from the first bit length determination unit 103 is received and output to the first bit stream cutout unit 102. 2.1.10 Bitstream Selection Unit 112 The bitstream selection unit 112 reads the first state or the second state stored in the state storage unit 142.

In the first state, the bit stream selection unit 112 receives the first bit string from the first bit stream extraction unit 102, and
06. In the second state, receiving a bit stream from the second bit stream buffer 110,
Output to the second bit stream cutout unit 106. 2.1.11 Second Bit Length Selection Unit 113 The second bit length selection unit 113 reads the first state or the second state stored in the state storage unit 142.

In the first state, the second bit length selection section 113 outputs the first bit length output from the first bit length determination section 103.
Receiving the bit length, and extracting the second bit stream
Output to 6. In the case of the second state, the code bit length output from second bit length determining section 107 is output to second bit stream cutout section 106. 2.1.12 First Constant Generation Unit 114 The first constant generation unit 114 outputs the constant 0 to the third bit length selection unit 115. 2.1.13 Third Bit Length Selection Unit 115 The third bit length selection unit 115 reads the first state or the second state stored in the state storage unit 142.

In the first state, the third bit length selecting section 115 outputs the first bit length output from the first bit length determining section 103.
The bit length is output to second bit length determining section 107. Second
In this case, the constant 0 output from the first constant generation unit 114 is output to the second bit length determination unit 107. 2.1.14 Second Constant Generation Unit 116 The second constant generation unit 116 outputs the constant 0 to the second position information selection unit 117. 2.1.15 Second Position Information Selection Unit 117 The second position information selection unit 117 reads the first state or the second state stored in the state storage unit 142.

In the first state, second position information selecting section 117 outputs the first run output from first decoding section 104 to second address calculating section 109. In the case of the second state, the constant 0 output from the second constant
Output to the address calculation unit 109. 2.1.16 Third Constant Generation Unit 124 The third constant generation unit 124 outputs the constant 0 to the first position information selection unit 125. 2.1.17 First Position Information Selection Unit 125 The first position information selection unit 125 reads the first state or the second state stored in the state storage unit 142.

In the first state, first position information selecting section 125 outputs the second run output from second decoding section 108 to first address calculating section 105. In the case of the second state, the constant 0 output from the third constant generator 124 is set to the first constant.
Output to the address calculation unit 105. 2.1.18 First Buffer Selection Unit 126 The first buffer selection unit 126 reads the first state or the second state stored in the state storage unit 142.

In the first state, the first buffer selecting section 126 outputs the second buffer output from the second address calculating section 109.
The address is output to the second buffer controller 122. In the case of the second state, the second address output from the second address calculation unit 109 is stored in the fourth buffer controller 1
28. 2.1.19 Second Buffer Selection Unit 127 The second buffer selection unit 127 reads the first state or the second state stored in the state storage unit 142.

In the first state, the second buffer selecting section 127 outputs the second DC signal output from the second inverse quantizing section 121.
The T coefficient is output to the second buffer controller 122.
In the case of the second state, the second DCT coefficient output from the second inverse quantization unit 121 is output to the fourth buffer controller 122. 2.1.20 Fourth Buffer 131 The fourth buffer 131 stores the third buffer address and DCT
This is a data storage buffer having a maximum of 64 areas for storing sets of coefficients.

The area for storing the third buffer address is
The area for storing the DCT coefficient is composed of 64 bytes.
Since it is composed of 6 bytes, the fourth buffer 131 has a total storage capacity of 160 bytes. 2.1.21 Fourth Buffer Controller 128 In the second state, the fourth buffer controller 128 receives the second address from the first buffer selector 126 and the second DCT coefficient from the second buffer selector 127. In the case of the second state, the fourth buffer controller 128 receives the second address from the first buffer selecting unit 126, and receives the second DC from the second buffer selecting unit 127.
When the T coefficient is received, a set of the second address and the second DCT coefficient is written as the third buffer address and the DCT coefficient from the head of the unwritten area in the fourth buffer 131.

The fourth buffer controller 128
In the case of the state, the fourth buffer 131 receives the instruction from the third buffer controller 129, and
All the sets of the third buffer address and the DCT coefficient stored in the buffer 131 are sequentially read, and the read set of the third buffer address and the DCT coefficient is output to the third buffer controller 129.

The fourth buffer controller 128 controls the second
When the reading of all the sets of the third buffer addresses and the DCT coefficients stored in the fourth buffer 131 is completed, all the contents stored in the fourth buffer 131 are erased. 2.1.22 Third Buffer 130 The third buffer 130 stores 6 areas for storing DCT coefficients.
This is a data storage buffer having four.

Since one DCT coefficient consists of 12 bits, the third buffer 130 has a total storage capacity of 96 bytes. The third buffer 130 is connected to an external connection device. The external connection device reads the DCT coefficient stored in the third buffer 130. 2.1.23 Third Buffer Controller 129 The third buffer controller 129 controls the third buffer controller 129 after the external connection device has finished reading all the values of the third buffer 130 and at the beginning of the processing for one block. Buffer 13
Write 0 to all 0 areas.

Thereafter, the third buffer controller 12
9 outputs an instruction to output a set of the third buffer address and the DCT coefficient to the fourth buffer controller 128.
The third buffer controller 129 stores a set of the third buffer address and the DCT coefficient in the fourth buffer controller 1.
28, the same set of DCT coefficients is written in the area of the third buffer 130 indicated by the third buffer address for each set of the received third buffer address and DCT coefficient. 2.2 Operation of Variable Length Code Decoding Device 20 The overall operation of the variable length code decoding device 20 will be described below.

The operation of each component of the variable-length code decoding device 20 is the same as that of the variable-length code decoding device 10, and a description thereof will be omitted. In the first state, the variable-length code decoding device 20 operates similarly to the variable-length code decoding device 10. The overall operation of the variable-length code decoding device 20 in the second state will be described with reference to the flowcharts shown in FIGS. In addition,
Here, description will be made focusing on differences from the flowchart shown in FIG. (1) First System Operation In the first system operation, step S706 shown in FIG.
Instead of Steps S708 to S708, in step S710, the first bit length determination unit 103 outputs the calculated first bit length to the first bit stream cutout unit 102 via the first bit length selection unit 111. (2) Operation of Second System In the operation of the second system, S706 to S70 shown in FIG.
8. In place of step S721, in step S730, the second bit stream cutout unit 106 outputs the partial compressed data stored in the second bit stream buffer 110 via the bit stream selection unit 112. A bit sequence of 24 bits is extracted from the bit position indicated by the second data read position, and the extracted bit sequence is used as a second bit sequence in the second bit length determination unit 1.
07.

Further, instead of S726 shown in FIG. 8, in step S731, the second bit length determination unit 107
Calculates the code bit length, outputs the calculated code bit length to the second bit stream cutout unit 106 via the second bit length selection unit 113, and the second bit stream cutout unit 106 The code bit length is received from the 2-bit length determination unit 107, the received code bit length is added to the stored second data read position, and the addition result is newly added to the second data read position.
(3) Operation of second buffer controller 122 The second buffer controller 122 performs the operation of S72 shown in FIG.
The operation shown in FIG. 7 is not performed. In step S741, a set of a first address and a first DCT coefficient is written as a first buffer address and a DCT coefficient from the head of an unwritten area in the second buffer 123. The second buffer controller 122 stores a set of the second address and the second DCT coefficient in the second buffer 123,
The operation of writing as the first buffer address and the DCT coefficient is not performed from the head of the unwritten area. (4) Operation of the Fourth Buffer Controller 128 The fourth buffer controller 122 sends the second buffer controller 122 from the second address calculator 109 via the first buffer selector 126 to the second
An address is received, a second DCT coefficient is received from the second inverse quantization unit 121 via the second buffer selection unit 127 (step S727), and a set of the second address and the second DCT coefficient is stored in the fourth buffer 131. From the head of the unwritten area, the third buffer address and DC
Writing is performed as a T coefficient (step S781).

The fourth buffer controller 128
Receives the instruction from the third buffer controller 129 (step S773), and starts from all the third buffers stored in the fourth buffer 131 from the head position of the fourth buffer 131.
The set of the buffer address and the DCT coefficient is sequentially read (step S782), and the read set of the third buffer address and the DCT coefficient is read into the third buffer controller 12.
9 (step S783). The fourth buffer controller 128 stores all third buffer addresses and DC
Reading of a set with T coefficient and third buffer controller 1
Reading and outputting are repeated until the output to 29 ends (step S784).

Further, the fourth buffer controller 128
When the reading of all the sets of the third buffer address and the DCT coefficient stored in the fourth buffer 131 is completed, all the contents stored in the fourth buffer 131 are deleted (step S785). (5) Operation of Third Buffer Controller 129 The third buffer controller 129 performs the third buffer controller 129 at the beginning of the processing for one block after the external connection device has finished reading all the values of the third buffer 130. Buffer 13
“0” is written in all the “0” areas (step S771).

Thereafter, the third buffer controller 12
No. 9 outputs an instruction to output a set of the third buffer address and the DCT coefficient to the fourth buffer controller 128 (step S772). Third buffer controller 12
9 is a combination of the third buffer address and the DCT coefficient in the fourth buffer address.
The received third buffer address and DC are sequentially received from the buffer controller 128 (step S783).
The same set of DCT coefficients is written in the area of the third buffer 130 indicated by the third buffer address for each set of T coefficients (step S775).

The third buffer controller 129 has a third
Until the reception of the set of the buffer address and the DCT coefficient is completed, the reception and the writing of the set of the third buffer address and the DCT coefficient are repeated (step S774). 2.3 Transition with Time of Variable-Length Code Decoding Apparatus 20 Transition with time in the decoding of each variable by the variable-length code decoding apparatus 20 will be described with reference to a time chart shown in FIG.

In this time chart, in the vertical direction,
A first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103,
Decoding section 104, first address calculation section 105, first inverse quantization section 120, second buffer controller 122, second buffer 123, first buffer controller 118, first
Buffer 119, second bit stream buffer 11
0, second bit stream cutout section 106, second bit length determination section 107, second decoding section 108, second address calculation section 109, second inverse quantization section 121, fourth buffer controller 128, fourth buffer 131 , And the processing units of the third buffer controller 129 and the third buffer 130 are listed, and the processing of each processing unit over time is shown in the horizontal direction. In addition, each selection unit and each constant generation unit are omitted.

In this time chart, processing C60
0 indicates processing by the first bit stream buffer 101. Processing C601 to C607, C611, C
612 are the first bit stream cutout units 10
2, the first bit length determination unit 103, the first decoding unit 104, the first address calculation unit 105, the first inverse quantization unit 120, the second
The processing by the buffer controller 122, the second buffer 123, the first buffer controller 118, and the first buffer 119 is shown.

Process C620 indicates a process performed by the second bit stream buffer 110. Processing C6
21 to C627, C631, and C632 are the second
Bit stream cutout unit 106, second bit length determination unit 1
07, the second decoding unit 108, the second address calculation unit 109,
Second inverse quantization section 121, fourth buffer controller 12
8, fourth buffer 131, third buffer controller 1
29, processing by the third buffer 130.

In this time chart, processing C60
0 and C620 start processing at the same time. 2.4 Conclusion According to the embodiment shown here, one system of bit stream buffer is added, and each selection unit and each constant generation unit are added.
It is possible to switch between decoding of a bit stream composed of two moving pictures and decoding of a bit stream composed of two different moving pictures. 3. Third Embodiment A variable-length code decoding device 30 as another embodiment according to the present invention will be described. 3.1 Configuration of Variable Length Code Decoding Device 30 The configuration of the variable length code decoding device 30 will be described with reference to the block diagram shown in FIG.

The variable length code decoding device 30 includes a first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103, and a first decoding unit 14.
0, first address calculator 105, second address calculator 1
09, a first buffer controller 118, a first buffer 119, a first inverse quantizer 120, a second inverse quantizer 12
1, second buffer controller 122, second buffer 1
23.

The components denoted by the same reference numerals as the components of the variable-length code decoding device 10 are the same components.
Hereinafter, newly added components will be described. Also, with respect to components having the same reference numerals as the components of the variable-length code decoding device 10, portions different from the components of the variable-length code decoding device 10 will be described. 3.1.1 First Bitstream Cutout Unit 102 The first bitstream cutout unit 102 is configured to start from the bit position indicated by the data read position in the partial compressed data stored in the first bitstream buffer 101. , 24 bits are extracted as a first bit string, and the extracted first bit string is output to the first bit length determination unit 103.

The first bit stream cutout unit 102 stores the four bit streams stored in the first bit stream buffer 101.
Until the extraction of all the bit strings from the partially compressed data of 096 bytes is completed, the extraction of the bit strings of 24 bits is repeated. Here, the bit length of the first bit string to be extracted is set to the maximum length of the variable-length code so as to include at least one codeword. The maximum length of the variable length code is 24 bits. Therefore, the length of the first bit string is 24 bits.

The first bit stream cutout unit 102 receives the first bit length or the first bit length and the second bit length from the first bit length determination unit 103. The first bit stream cutout unit 102 adds the received first bit length and the stored data read position. When receiving the second bit length, the second bit length is further added. The first bit stream cutout unit 102 newly stores the addition result as a data read position. 3.1.2 First Bit Length Determination Unit 103 The first bit length determination unit 103 receives a 24-bit first bit string from the first bit stream cutout unit 102.

The first bit length determining section 103 detects one codeword from the beginning of the received first bit string as the first codeword, and calculates the bit length of the detected first codeword as the first bit length. . If the calculated first bit length is 5 bits or less, the first bit length determination unit 103
A second code word having a length of 5 bits or less is detected from a position following the code word, and when the second code word is detected, the bit length of the detected second code word is calculated as the second bit length. .

First bit length determining section 103 outputs the calculated first bit length to first bit stream cutout section 102 and outputs the detected first codeword to first decoding section 140. When detecting the second codeword, the first bit length determining unit 103 outputs the calculated second bitlength to the first bitstream cutout unit 102, and outputs the detected second codeword to the first bitstream. Output to decoding section 140.

The process of detecting one codeword from a bit string is well known and will not be described in detail. 3.1.3 First Decoding Unit 140 The first decoding unit 140 includes a first decoding control unit 156, a third table 157, and a fourth table 158, as shown in FIG.
Consists of (1) Third table 157 As shown in FIG.
72, level A173, run B174 and level B175
6 is a data table having a plurality of areas for storing sets. Each area has a variable length code 171 as an address.

The variable length code 171 is formed by combining a first variable length code and a second variable length code. The first variable length code corresponds to a combination of a run A 172 and a level A 173. , The second variable length code is a run B174 and a level B1
75 corresponds to the set. A first variable length code and a second
Are variable-length codes each having 5 bits or less.

For example, the variable length code 171 shown in FIG.
“1100110” is formed by combining the first variable-length code “110” and the second variable-length code “0110”. The run-level pair 179a corresponds to the first variable-length code “110”, and the run-level pair 1
79b corresponds to the second variable length code “0110”. (2) Fourth Table 158 As shown in FIG.
7 is a data table having a plurality of areas for storing a set of 7 and level 178. The variable length code 176 is an address of each area.

The variable length code 176 corresponds to a combination of a run 177 and a level 178. In this figure,
“S” of the last bit of the variable length code 176 takes a value of “0” or “1”. When "s" is "0", the level 178 indicates a positive value, and when "s" is "1", the level 178 indicates a negative value. Also, the variable length code “1s” is the DC within one block.
The variable length code “11s” is used for the coefficient, and is used for the AC coefficient in one block. (3) First Decoding Control Unit 156 The first decoding control unit 156 receives the first codeword or the first and second codewords output from the first bit length determination unit 103.

First decoding control section 156 determines whether or not the second codeword has been received. First decryption control unit 156
When the second codeword is received, the first codeword and the second codeword are combined, and the run A172 stored in the area having the combination result as an address from the third table 157 is stored.
, Level A173, run B174, and level B175. The first decoding control unit 156 calculates the obtained run A172
As the first run to the first address calculation unit 105 and the second address calculation unit 109, and the obtained level A173
Is output to the first inverse quantization unit 120 as a first level, the obtained run B174 is output as a second run to the first address calculation unit 105 and the second address calculation unit 109, and the obtained level B175 is The second level is output to the second inverse quantization unit 121.

When the first decoding control unit 156 does not receive the second code word, the first decoding control unit 156 reads the run 177 stored in the area having the first code word as an address from the fourth table 158.
And a level 178 are obtained. First decryption control unit 156
Outputs the obtained run 177 as a first run to the first address calculator 105 and the second address calculator 109,
The obtained level 178 is output to the first inverse quantization unit 120 as the first level. 3.2 Operation of Variable Length Code Decoding Device 30 The operation of the variable length code decoding device 30 will be described. 3.2.1 Overall Operation of Variable-Length Code Decoding Apparatus 30 FIG.
This will be described with reference to the flowchart shown in FIG. In this figure, steps denoted by the same reference numerals as those in the flowchart of FIG. 8 are steps that operate in the same manner. In the following, newly added steps will be described. Steps denoted by the same reference numerals as the steps in the flowchart in FIG. 8 will be described focusing on the differences from the steps in the flowchart in FIG.

In the variable length code decoding apparatus 30, the first
The operation of the system is a summary of the operations of the first bit stream cutout unit 102, the first bit length determination unit 103, the first decoding unit 140, the first address calculation unit 105, and the first inverse quantization unit 120. , The operation of the second system is a summary of the operations of the second address calculation unit 109 and the second inverse quantization unit 121.

Step S7 of the flowchart shown in FIG.
06, S707, S708, S703, S721, S7
Instead of 22, S726 and S723, S793 and S794 are newly provided in the flowchart shown in FIG. In step S701, the first bit stream cutout unit 102 extracts a first bit sequence of 24 bits from the first bit stream buffer 101,
Output to first bit length determination section 103.

In step S 702, first bit length determining section 103 receives the first 24-bit bit string from first bit stream cutout section 102, detects the first bit string from the first bit string as the first codeword, and determines the first bit length. Is calculated. When the calculated first bit length is 5 bits or less, the second codeword is detected, and when the second codeword is detected, the second bit length is calculated. Next, the first bit length or the first bit length and the second bit length are output to the first bit stream cutout unit 102, and the first codeword or the first and second codewords are output to the first decoding unit 140. Output to

At step S793, the first decoding unit 1
Forty first decoding control unit 156 decodes the first run or the first run and the second run, decodes the first level or the first and second levels, and sets the first run and the first level to the first run, respectively. One address calculation unit 105 outputs the result to the first inverse quantization unit 120. In step S794, when the second run and the second level are decoded, the second run and the second level are output to the second address calculation unit 109 and the second inverse quantization unit 121, respectively. 3.2.2 First decoding control section 156 of first decoding section 140
The operation of the first decoding control unit 156 of the first decoding unit 140 will be described with reference to the flowchart shown in FIG.

The first decoding control unit 156 receives the first codeword or the first and second codewords output from the first bit length determination unit 103 (step S801), and determines whether the second codeword has been received. (Step S80)
2). Upon receiving the second codeword (step S802), the first decoding control unit 156 combines the first codeword and the second codeword (step S803), and outputs the third table 1
57, the run A172, the level A173, the run B174, and the level B175 stored in the area having the combined result as the address are obtained (step S804).
And the second address calculation section 109, and outputs the obtained level A173 as the first level to the first inverse quantization section 120, and the obtained run B174 as the second run and outputs the first run to the first address calculation section 105. The second level is output to the second address calculation unit 109, and the obtained level B175 is set as the second level.
Output to the inverse quantization unit 121 (step S805).

When the first decoding control unit 156 does not receive the second code word (step S802), the first decoding control unit 156 determines from the fourth table 158 the run 177 stored in the area having the first code word as an address and the level 178 (step S806), and the obtained run 177 is set as the first run,
The output to the address calculation unit 105 and the second address calculation unit 109 is performed.
The output is output to the inverse quantization unit 120 (step S807). 3.3 Transition with Time of Variable-Length Code Decoding Apparatus 30 Transition with time in variable-length code decoding apparatus 30 for each codeword will be described with reference to a time chart shown in FIG.

In this time chart, in the vertical direction,
A first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103,
Decoding section 140, first address calculation section 105, first inverse quantization section 120, second address calculation section 109, second inverse quantization section 121, second buffer controller 122, second buffer 123, first buffer controller 118 , The respective processing units of the first buffer 119 are listed, and the processing of each processing unit over time is shown in the horizontal direction.

This time chart shows a case where the first decoding unit 140 decodes the first codeword and the second codeword. In this time chart, processes C701 to C708 and C713 to C714 are respectively performed by a first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103,
First decoding section 140, first address calculation section 105, first inverse quantization section 120, second address calculation section 109, second inverse quantization section 121, first buffer controller 118, first
The processing by the buffer 119 is shown. Processing C
709 and C711 are the second buffer controller 122
The processing C710 and C712 are performed by
The processing by the second buffer 123 is shown.

The processes C701 to C704 are performed in this order. Process C705 and process C707 are started simultaneously. 3.4 Summary According to the embodiment shown here, when code words with a high appearance probability and short code lengths are consecutive, the first decoding unit that decodes two code words at the same time is provided. Two decodings can be performed simultaneously, and then the address calculation and dequantization of the two codewords can be performed in parallel. 4. Other Modifications Although the present invention has been described based on the above embodiment, it is needless to say that the present invention is not limited to the above embodiment. That is, the following cases are also included in the present invention. (1) It is assumed that the second decoding unit has only a variable length code decoding table relating only to a variable length code whose run length becomes 0 when decoded, and decodes the variable length code using this variable length code decoding table. Is also good. Further, in this case, the second bit length determination unit has a variable length code decoding table for a variable length code whose run length becomes 0 when decoded, and when the decode is performed using this variable length code decoding table, the run length becomes 0. Is detected as a second codeword, and when the second bit length determination unit detects a variable length code having a run length other than 0, the received first bit length is used as a code bit length. ,
The second bit length and the second codeword are not output to the second decoding unit.

The variable length code decoding table has a plurality of areas. The address of each area is a variable-length code whose run length becomes 0 when decoded. A level corresponding to the variable-length code is stored in an area indicated by the variable-length code as an address. The size of the variable-length code decoding table is (level size) × (the number of variable-length codes included in the variable-length code decoding table).

With this configuration, it is possible to decode two code words in which a first code word composed of an arbitrary variable length code and a second code word composed of a variable length code having a run length of 0 are continuous.
The variable-length code decoding table has no information about the run length for the variable-length code having a run length of 0, and does not relate to the variable-length code having a run length other than 0.
The size of the table included in the decoding unit can be reduced. (2) The second decoding unit may have only a variable length code decoding table having only variable length codes of a predetermined length or less. Here, the predetermined length is, for example, 10 bits.
The second decoding unit decodes the variable-length code using the variable-length code decoding table having only the variable-length code of a predetermined length or less. Further, in this case, the second bit length determination unit detects only a variable length code having the predetermined length or less as the second codeword,
When the second bit length determining unit detects a variable length code larger than the predetermined length, the received first bit length is used as the code bit length.

The variable length code decoding table has a plurality of areas. The address of each area is a variable length code of a predetermined length or less. A run length and a level corresponding to the variable length code are stored in an area indicated by the variable length code as an address. The size of the variable length decoding table is (run length size + level size) ×
(The number of variable length codes included in the variable length code decoding table).

With this configuration, when decoding two code words in which an arbitrary variable length code and a variable length code of a predetermined length or less are continuous, the variable length code can be decoded. Since the code decoding table does not relate to a variable length code larger than the predetermined length, the size of the table included in the second decoding unit can be reduced. (3) The first decoding unit and the second decoding unit may share a variable-length code decoding table.

With this configuration, the table size can be reduced as a whole. (4) A JPEG variable-length code decoding table that can freely set a variable-length code for each application may be set in the associative memory of the first decoding unit and the second decoding unit. This is because the associative memory is composed of the second table for storing data and the first table for storing the address of the second table. In addition, the fixed table of the first decoding unit and the second decoding unit stores MPEG A that does not change for each application.
The variable length code of the C coefficient may be stored. (5) The second decoding unit has only the variable length code decoding table for decoding the variable length code of the AC coefficient of MPEG, and
The variable length code decoding table for decoding the variable length code of the DC coefficient of G may not be provided. Because the DC coefficient is at the head of one block, it is included in the first codeword and not included in the second codeword. (6) The variable-length code decoding apparatus described in each of the above embodiments further reads the DCT coefficients stored in the first buffer or the first and third buffers for each block, and Inverse DC to DCT coefficient of block
An inverse DCT unit that performs T and generates one block of image, and an image storage buffer that stores the generated one block of image may be provided. (7) Although the first bit stream buffer reads the bit stream of the moving image, the first bit stream buffer may read the bit stream of the still image. (8) In the variable-length code decoding device 20, the selection accepting unit 141 accepts the selection of a state from the user. However, the state storage unit 142 normally stores the first state, and the second bit stream When the buffer 110 detects that the optical disk medium is mounted on the optical disk device, the selection receiving unit 141 may select the second state, or may select the second state.
When 0 receives a bit stream as a digital broadcast wave, the selection receiving unit 141 may select the second state.

In the variable-length code decoding device 20, the selection receiving unit 141 is not provided, and the state storage unit 142
The first state or the second state may be stored in advance. (9) As shown in FIG. 27, the variable length code decoding device 40 includes a first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 103,
First decoding section 104, first address calculation section 105, second bit stream cutout section 106, second bit length determination section 10
7, the second decoding unit 108, the second address calculation unit 109, the first buffer controller 118, and the first buffer 119.

Here, in the variable length code decoding device 40, the components having the same codes as those of the variable length code decoding device 10 are the same as those of the variable length code decoding device except for the first buffer controller 118 and the first buffer 119. It is the same as the component of the chemical conversion device 10. First buffer controller 118
After the external connection device has finished reading all the values in the first buffer, at the beginning of the processing for one block, 0 is written to the entire area of the first buffer 119. Next, the first
The buffer controller 118 receives the first level output from the first decoding unit 104, receives the first address output from the first address calculation unit 105, and receives the second level output from the second decoding unit 108 , Second
The second address output from the address calculator 109 is received. Next, the first buffer controller 118 writes the first level in the area on the first buffer indicated by the first address, and writes the second level in the area on the first buffer indicated by the second address.

The first buffer 119 is a data storage buffer having a capacity for storing 64 levels. Since one level consists of 12 bits, the first buffer 11
9 has a total storage capacity of 96 bytes. The first buffer 119 is connected to an external connection device, and the external connection device reads a level stored in the first buffer 119. (10) As shown in FIG. 28, the variable length code decoding device 50 includes a first bit stream buffer 101, a first bit stream cutout unit 102, a first bit length determination unit 10
3, first decoding section 104, first address calculation section 105, second bit stream cutout section 106, second bit length determination section 107, second decoding section 108, second address calculation section 10
9, a first inverse quantization unit 120, a second inverse quantization unit 121, a first buffer controller 118, and a first buffer 119.

Here, in the variable-length code decoding device 50, components having the same codes as those of the variable-length code decoding device 10 are the same as those of the variable-length code decoding device except for the first buffer controller 118 and the first buffer 119. It is the same as the component of the chemical conversion device 10. First buffer controller 118
After the external connection device has finished reading all the values in the first buffer, at the beginning of the processing for one block, 0 is written to the entire area of the first buffer 119. Next, the first
The buffer controller 118 includes a first inverse quantization unit 120
, The first DCT coefficient output from the first address calculation unit 105, the second DCT coefficient output from the second inverse quantization unit 121, and the second address calculation unit 109 The output second address is received. Next, the first buffer controller 118 writes the first DCT coefficient in the area on the first buffer indicated by the first address, and writes the second DCT coefficient in the area on the first buffer indicated by the second address.

The first buffer 119 stores a DCT coefficient of 64
This is a data storage buffer having a capacity to store the data. 1
Since the DCT coefficients have 12 bits, the first buffer 119 has a total storage capacity of 96 bytes. The first buffer 119 is connected to an external connection device, and the external connection device reads out the DCT coefficient stored in the first buffer 119. (11) The second buffer 12 of the variable-length code decoding device 10
3 may have a maximum of 64 first data areas for storing a set of a write flag, a first buffer address, and a DCT coefficient. In this case, the second buffer controller 122 finishes reading all sets of the first buffer address and the DCT coefficient stored in the second buffer 123, and deletes all the contents stored in the second buffer 123. When erasing, all the write flags of the second buffer 123 are turned off. In addition, the second buffer controller 122 writes the address and the DCT coefficient in the first data area including the OFF write flag and the first data area including the ON write flag. Is determined to have been written. When writing the set of the first buffer address and the DCT coefficient into the second buffer 123, the second buffer controller 122 stores the set of the first buffer address and the DCT coefficient in the first data area including the OFF write flag. Is written, and the OFF write flag included in the first data area is turned ON.

[0128] The second buffer controller 122
From the head position of the buffer 123, of the sets of all the first buffer addresses and the DCT coefficients stored in the second buffer 123, all the sets whose write flag is ON are sequentially read. In this way, it is possible to reduce the number of bits for clearing the contents of each area to 0. (12) First buffer 11 of variable-length code decoding device 10
No. 9 may have 64 second data areas for storing sets of write flags and DCT coefficients.

In this case, the first buffer controller 11
8 is after the external connection device has read all the values of the first buffer, and at the beginning of the processing for one block,
Instead of writing 0 to all the second data areas of the first buffer 119, all the write flags of the first buffer 119 are set to O.
Set to FF. The first buffer controller 118 controls the first
When writing the same set of DCT coefficients in the second data area of the first buffer 119 indicated by the first buffer address for each set of buffer address and DCT coefficient, the write flag of the second data area is turned on. To

The external connection device includes a first buffer 119
When the DCT coefficient stored in the second data area is read, the DCT coefficient is regarded as 0 and the value of 0 is read for the second data area whose write flag is OFF. In this way, it is possible to reduce the number of bits for clearing the contents of each area to 0. (13) The variable-length code decoding device 10 includes a first buffer 119 which is a data storage buffer having 64 areas for storing DCT coefficients. Here, these 64
These areas are called first block areas. You may comprise as follows.

The first buffer 119 further has 64 areas for storing DCT coefficients. These 64 areas are referred to as a second block area. The first buffer controller 118 writes DCT coefficients for one block in the first block area, and when the writing is completed, the inverse DCT unit applies inverse DCT to the plurality of DCT coefficients written in the first block area. Also, the first buffer controller 118 writes the DCT coefficient of the next one block to the second block area at the same time as the completion of the writing to the first block area, and when the writing is completed, the inverse DCT unit Performs inverse DCT on a plurality of DCT coefficients written in.

As described above, the first buffer controller 1
Reference numeral 18 alternately writes DCT coefficients for one block in the first block area and the second block area, and the inverse DCT section performs inverse DCT alternately. (14) The variable-length code decoding device 10a according to another embodiment may decode header information in addition to decoding image data.

The information compressed and encoded according to the MPEG standard includes compression-encoded screen data obtained by compressing and encoding screen data and header information. The header information is control information for decoding required when decoding image data.
The header information includes encoded control information and unencoded control information. An example of encoded control information is
MBT (macroblock type, Macroblock
Type), MHC (Motion Horizont)
al Code), DH (DMV Horizonta)
l), MVC (Motion Vertical Co.)
de) and SEF (slice extension flag).

Here, MBT indicates the MB encoding mode, MHC indicates the difference between the horizontal component of the MB motion vector and the previous vector, and DH indicates the horizontal difference vector in the case of dual prime prediction. And MVC is MB
5 shows a difference between the vertical component of the motion vector of the motion vector and the previous vector. The SEF includes a flag having a value of “0” or a flag having a value of “1” and a variable length code. If the SEF is a flag having a value of “0”, it indicates a fixed value of the SEF stored in advance by the variable-length code decoding device 10a, and if the SEF includes a flag of a value of “1”, , And control information indicated by a variable length code following the flag. It should be noted that these pieces of control information are publicly known, and thus further description will be omitted.

These information MBT, MHC, DH,...
The MVC and the SEF are arranged in the order specified by the MPEG (some information is omitted). Note that the control information standardized by MPEG includes not only the MBT, MHC, DH, MVC, and SEF described above, but also other control information. However, for the sake of simplicity, it is assumed here that the control information consists only of MBT, MHC, DH, MVC and SEF.

For the sake of simplicity, the information compressed and coded according to the MPEG standard contains header information (M
BT, MHC, DH, MVC, and SEF) and compression-coded screen data are included in a plurality, and are arranged in this order. (Configuration of Variable Length Code Decoding Device 10a) As shown in FIG. 30, the variable length code decoding device 10a has the same configuration as the variable length code decoding device 10 (indicated by reference numeral 10 in FIG. 30) It comprises a control unit 191 and an information storage unit 192.

The information storage unit 192 is, as an example, shown in FIG.
As shown in (1), "MB QUANT", "MB forward prediction", "MB backward prediction", "MB pattern", "MB intra", and the like, which are control information for decoding image data, are stored. These pieces of information indicate the coding mode of the MB, and are control information obtained by decoding the MBT. Since these pieces of information are known,
Description is omitted.

The variable-length code decoding device 10a has a first decoding unit 104a instead of the first decoding unit 104 included in the variable-length code decoding device 10. First decoding unit 10
4a, as shown in FIG. 32, the first decoding control unit 151
a, first pointer 831, address table 800, M
BT table 811, MHC table 812, DH table 813,..., MVC table 814, SEF table 815, fixed value table 815, associative memory 15
3 and SEF fixed value information 821.

Fixed value table 152 and associative memory 15
3 is the same as the fixed value table 152 and the associative memory 153 included in the first decoding unit 104 of the variable-length code decoding device 10. The first pointer 831 is an address indicating the position of any area in the address table 800.

The address table 800 includes an MBT table 811, an MHC table 812, and a DH table 81.
3,..., The MBT table address 801 and the MHC table address 80 which are the addresses of the head positions of the MVC table 814 and the SEF table 815, respectively.
2, the DH table address 803,..., The MVC table address 804, and the SEF table address 805 are stored in advance.

An MBT table address 801, an MHC table address 802, a DH table address 803,
,..., MVC table address 804 and SEF table address 805 are control information MBT, MHC, DH,.
The address table 800 corresponds to the order of the EFs.
Above, they are stored side by side.

MBT table 811, MHC table 8
12, DH table 813,..., MVC table 8
14 are MBT, MHC, DH,..., MV, respectively.
6 is a code table for decoding C. FIG. 33 shows an example of the MBT table 811. As shown in this figure,
The MBT table 811 stores an MB type variable length code (V
LC), MBQUANT, MB forward prediction, MB reverse prediction, MB pattern, and MB intra.

MHC table 812, DH table 81
3,..., The MVC table 814 and the SEF table 815 also have sets of variable-length codes and decoded control information, like the MBT table 811. S
The EF fixed value information 821 is a fixed value of the SEF. The first decoding control unit 151a controls decoding of image data in the same manner as the first decoding control unit 151. Details will be described later mainly on the differences from the first decoding control unit 151.

The variable-length code decoding device 10a has a second decoding unit 108a instead of the second decoding unit 108 included in the variable-length code decoding device 10. The second decoding unit 108a has a second pointer, a second decoding control unit, an address table, other code tables, and the like, like the first decoding unit 104a. (Operation of Variable Length Code Decoding Apparatus 10a) The overall operation of the variable length code decoding apparatus 10a will be described with reference to the flowchart shown in FIG.

The control unit 191 sets the “information type” indicating the encoding target to “MB” located at the head of the header information.
"T" is set as an initial value (step S101). Next, the control unit 191 determines whether to initialize the first pointer 831. Here, when the decoding of the compression-encoded image data is completed and the MBT that is the header information is read out next, the control unit 191 sets the first pointer 831
Is determined to be initialized. When it is determined that the first pointer 831 is to be initialized (step S102), the first pointer 831 is set to “MBT table address 801-2” as an initial value (step S103). Next, the control unit 191 determines whether the “information type” is any of the header information or “image data”, and when determining that the “information type” is the header information (step S10).
4) The header information is decoded (step S10).
5) If the entire decoding process is completed (step S10)
6), the variable-length code decoding device 10a ends the operation. Note that the completion of the entire decoding process is determined based on completion information (not described above) included in the header information.
If the entire decryption process is not completed (step S106)
The control unit 191 sets the information to be decoded next to “information type” (step S109), and proceeds to step S102.
Return control to

When the “information type” is “image data” (step S104), the control unit 191 performs the decoding process of the image data shown in FIG. 8 (step S107).
Until the decoding process of the image data is completed, step S10
7 is repeated, and upon completion (step S108), the control moves to step S109. (Operation for Decoding Header Information) Step S10 in FIG.
Details of the decoding process of the header information shown in FIG.
This will be described with reference to the flowchart shown in FIG.

In the variable-length code decoding device 10a, similarly to the variable-length code decoding device 10, the first bit stream cutout unit 102, the first bit length determination unit 103, the first decoding unit 104a, the first address calculation The operations performed by the unit 105 and the first inverse quantization unit 120 are collectively referred to as a first system operation for convenience, and the second bit stream cutout unit 106, the second bit length determination unit 107, the second decoding unit 108a, The operations performed by the two-address calculation unit 109 and the second inverse quantization unit 121 are collectively referred to as a second-system operation for convenience. (A) Operation of First System The first bit stream cutout unit 102 extracts a 48-bit bit sequence from the bit position indicated by the data read position in the first bit stream buffer 101 to obtain a first bit sequence. The first bit string is output to the first bit length determination unit 103 (step S12).
1) Output the extracted first bit string to the second bit stream cutout unit 106 (step S126).

The first bit length determining section 103 receives the 48-bit first bit string from the first bit stream cutout section 102, and detects one codeword from the head of the received first bit string as the first codeword. , The bit length of the detected first codeword is calculated as the first bit length, and the calculated first
The bit length is output to the first decoding unit 104a, the detected first codeword is output to the first decoding unit 104a (Step S122), and the calculated first bit length is output to the second bit stream cutout unit 106. The first bit length is output to the second bit length determining unit 107 (step S127).

The control unit 191 sets the first pointer 831 to 2
Are added (step S123). Next, the first decoding control unit 151a of the first decoding unit 104a receives the first bit length and the first codeword from the first bit length determination unit 103, extracts the first pointer 831, and extracts the first pointer 831
A table address stored in an area in the address table 800 indicated by 31 is extracted, and the received first codeword is decoded using the code table indicated by the extracted table address to generate a first decoded word ( Step S124), the control unit 191 generates the first
The decoded word is written in a predetermined area in the information storage unit 192 (Step S125). (B) Operation of Second System The second bit stream cutout unit 106 receives the 48-bit first bit string from the first bit stream cutout unit 102 (step S126), and the first bit length determination unit 10
3 (step S127),
From the beginning of the received 48-bit first bit string,
The remaining bit strings from which the received bit strings of the first bit length have been removed are output as second bit strings to the second bit length determining unit 107 (step S131).

The second bit length determination section 107 receives the first bit length from the first bit length determination section 103 (step S128), receives the second bit string from the second bit stream cutout section 106, and receives the received second bit string. One code word from the head of the bit string is detected as a second code word, the bit length of the detected second code word is calculated as a second bit length, and the calculated second bit length and the detected second code word are calculated. The output to the second decoding unit 108a (step S132), the second bit length determination unit 107 calculates the code bit length, outputs the calculated code bit length to the first bit stream cutout unit 102, and The stream cutout unit 102 receives the code bit length from the second bit length determination unit 107, adds the received code bit length to the stored data read position, and updates the addition result to a new value. It is stored as data read position (step S136).

The control section 191 has the first pointers 831 and 1
And the result of the addition is set as the value of the second pointer (step S133). Next, the second decoding unit 108a
The second bit length and the second code word are received from the second bit length determination unit 107, the second pointer is extracted, the table address stored in the area in the address table indicated by the second pointer is extracted, and the extracted table is extracted. Using the code table indicated by the address, the received second codeword is decoded to generate a second decoded word (step S134), and the control unit 191 stores the generated second decoded word in the information storage unit 192. Write to a predetermined area (step S
135). (Processing operation of first decoding control section 151a) Details of the decoding processing of the first decoded word by the first decoding control section 151a in step S124 of FIG. 35 will be described with reference to the flowchart shown in FIG.

The first decryption control section 151a includes a control section 191
(Step S151). If the received information type is image data (step S1
52), the first decoding control unit 151a performs the process shown in FIG. 11 (Step S153). The received information type is
If it is header information and control information without decoding (step S152), the first decoding control unit 151a sets the first codeword as it is as the first decoded word (step S15).
4).

If the received information type is header information and the SEF flag is 0 (step S15)
2), the first decryption control unit 151a sets the SEF fixed value information 8
21 as the first decoded word as it is (step S15
5). The received information type is header information, and SE
If the flag of F is 1 (step S152), the first
The decoding control unit 151a removes the first bit (which is a flag) of the first codeword, extracts the first pointer 831 (Step S157), and stores the first pointer 831 in the area in the address table 800 indicated by the first pointer 831. The table address is extracted (step S158), and the first codeword is decoded using the code table indicated by the extracted table address to generate a first decoded word (step S159).

If the received information type is header information and the information type is otherwise (step S152), the first decoding control unit 151a transfers control to step S157. (Summary) As described above, the variable-length code decoding device 10a decodes header information in addition to decoding image data. The control information included in the header information includes control information encoded using different encoding tables, and the variable-length code decoding device 10a performs decoding to decode these encoded control information. It has a plurality of tables and switches the decoding table according to the encoded control information to decode the decoded control information.
In addition, the two adjacent control information are respectively transmitted to the first decoding unit 1.
04a and the second decoding unit 108a perform decoding in the same time zone.

The first decoding unit 104a and the second decoding unit 108a respectively include an address table, an MBT table, an MHC table, a DH table,.
Table, an SEF table, a fixed value table, an associative memory, and SEF fixed value information, but only one of them has the first decoding unit 104a and the second decoding unit 108a. May be used.

Note that the control information may be decoded only by first decoding section 104a. In this case, the first pointer 831 is advanced by one. (15) A digital broadcast receiving apparatus which decodes a compressed code string included in a received digital broadcast wave and reproduces image information, which is a typical application example of the variable length code decoding apparatus described above. 901 will be described with reference to the block diagram shown in FIG.

[0157] The antenna 911 receives digital broadcast waves. The digital broadcast wave includes a compressed code string in which image information is encoded. Digital broadcast receiving device 901
Is a tuner 912 for selecting a signal of a designated channel from the received digital broadcast waves, a demodulator 913 for demodulating and performing error correction, generating a transport stream (TS), and descrambling, and a transport stream (TS). TD for separating program information, audio stream, and video stream (including a compressed code string) from TS)
(Transport stream decoder) 914, an audio processing unit 915 that decodes the separated audio stream to generate an audio signal, and outputs the generated audio signal to a speaker 922, and decodes the separated video stream to generate a video signal. And a video processing unit 916 for generating the output to the monitor 923. The speaker 922 is
The sound is output, and the monitor 923 displays an image.

The video processing unit 916 is composed of the above-described variable-length code decoding device, and decodes a video stream to generate DCT coefficients.
7. IDCT section 918 that applies inverse DCT to the generated DCT coefficient, and MC (Motion Co.) that performs motion compensation processing.
The image processing unit 910 includes a video output unit 920 that generates a video signal, and a memory unit 921 that stores a plurality of frame images.

With such a configuration, digital broadcast receiving apparatus 901 can reproduce video and audio from the received digital broadcast wave. (16) A DVD reproducing device 9 that decodes a compressed code string recorded on a DVD and reproduces image information, which is another typical application example of the variable-length code decoding device described above.
31 will be described with reference to the block diagram shown in FIG.

[0160] The DVD stores a compressed code string in which image information is encoded. The DVD playback device 931
A DVD reading unit 941 for reading data from the VD, an error correcting unit 942 for performing error correction, a separating unit 943 for separating an audio stream and a video stream (including a compressed code string), and decoding the separated audio stream to output audio. A signal is generated, and the generated audio signal is transmitted to the speaker 9.
The audio processing unit 945 outputs the video signal to the monitor 47. The audio processing unit 945 outputs the video signal to the monitor 946.
The video processing unit 944 has the same configuration as the video processing unit 916 of the digital broadcast receiving device 901. The video processing unit 944 includes a variable-length code decoding unit including the variable-length code decoding device described above.

With this configuration, the DVD reproducing device 931 can reproduce video and audio from a DVD. (17) The plurality of embodiments and the modifications described above may be combined.

[0162]

As described above, the present invention relates to a variable-length code decoding apparatus for decoding variable-length codes simultaneously or sequentially . Code extraction means for extracting a code word, and the compressed code string is configured from a sequence of a plurality of code words, the code word,
A parallel decoding means for decoding the two codewords in parallel, which is a variable length code.

According to this configuration, two codewords are cut out from the compressed code string, and the two cutout codewords are decoded in parallel, so that more variable length codes can be decoded per fixed time. It has the effect of becoming. Here, the compressed code sequence includes at least two codewords generated by quantizing a signal and further performing entropy coding, and the signal is generated by performing orthogonal transform on a plurality of pieces of image information,
The code extracting unit extracts two codewords generated from the image information, the two codewords are adjacent to each other, and the parallel decoding unit performs entropy processing of the two codewords in parallel. Code decoding means for generating two sets of coefficients by decoding, and a signal for generating two sets of signals in parallel by performing inverse quantization based on the two sets of generated coefficients. It is configured to include a recovery unit
It is.

According to this configuration, two codewords are cut out from a compressed code string including a codeword in which a signal generated from image information is coded, and the cutout two codewords are subjected to entropy decoding in parallel. Since the signal before encoding can be decoded, more variable length codes can be decoded per fixed time. Here, the codeword is generated by encoding a set of a run and a level, wherein the run indicates the number of signals having a value of 0 included in the quantized signal, and the level indicates the quantum. The code extracting means for indicating a 1 signal having a non-zero value included in the converted signal and extracting a first code word and a second code word as two adjacent code words; The position information, which is stored in the compressed code string, is the first position information.
Position storage means for indicating the position where the code word is arranged, and from the compressed code string, a first code word arranged from the position indicated by the position information is detected, and the length of the detected first code word is detected. And a second extracting means for calculating a first code length indicating a first code length, and a second extracting means arranged from a position indicated by an added value obtained by adding the first code length to the position information from the compressed code string. A second extracting means for detecting a code word, wherein the code decoding means for generating a first set and a second set comprising a run and a level as the two sets of coefficients, First decoding means for generating a first set consisting of a run and a level by entropy decoding the detected first code word; and entropy decoding the detected second code word to generate a run. Second set consisting of and level And a second decoding means for generating,
The signal restoring means is configured to generate the first set and the second set.
May be configured to generate two sets of signals based on the set.

According to this configuration, from the compressed code string,
It is possible to sequentially cut out two codewords that are arranged consecutively, and there is an effect that two sets of runs and levels can be respectively entropy-decoded from these two codewords. Here, the first decoding means includes: a first table having a plurality of areas having addresses equal to or less than a first predetermined number, wherein each area stores a set of a run and a level; Is a code word generated by entropy-encoding the run and the level stored in the area, and a second table having a plurality of areas having addresses larger than the first predetermined number; A different value is stored in each area, and a third table having the same number of areas as the number of areas included in the second table, wherein each area is provided in each area included in the second table. Correspondingly, each of the areas has, as an address, a value stored in each of the corresponding areas of the second table, and a set of a run and a level is stored in each of the areas. Has The address of each of the regions that,
A codeword generated by entropy-encoding the run and the level stored in the corresponding area in the third table, wherein the calculated first code length is the first code length.
If the number is equal to or less than a predetermined number, a first set of run and level is generated by reading a set of run and level stored in an area having the first codeword as an address from the first table. When the calculated first code length is greater than the first predetermined number, a value stored in an area having the first codeword as an address is read from the second table, and the third table is read. And a first decoding control means for generating a first set of run and level by reading a set of run and level stored in an area having the read value as an address. Is also good.

According to this configuration, the variable-length code decoding table of the first decoding means is divided into a fixed table (first table) and an associative memory (second table and third table).
With the configuration of stages, there is an effect that the size of the table can be reduced as compared with the case where the variable length code decoding table is realized by one table. The second decoding means includes a fourth table having a plurality of areas having addresses equal to or less than a first predetermined number, wherein each area stores a set of a run and a level. Is a codeword generated by entropy-encoding the run and the level stored in the area,
A fifth table having a plurality of areas having addresses larger than the first predetermined number, wherein each area stores different values, and has the same number of areas as the fourth table has; The sixth table and where
Each of the areas corresponds to each of the areas of the fourth table. Each of the areas has a value stored in each of the corresponding areas of the fourth table as an address. A pair with a level is stored.
The address of each area of the table is a codeword generated by entropy-encoding the run and level stored in the corresponding area of the sixth table,
When the detected second codeword is equal to or less than the first predetermined number, reading a set of a run and a level stored in an area having the second codeword as an address from the fourth table. Generates a second set of run and level, and if the detected second codeword is greater than the first predetermined number, is stored in an area having the second codeword as an address. A second set of run and level is generated by reading a value from the fifth table and reading a set of run and level stored in an area having the read value of the sixth table as an address. The second decoding control means may be included.

According to this configuration, the variable-length code decoding table of the second decoding means is divided into a fixed table (fourth table) and an associative memory (fifth and sixth tables).
With the configuration of stages, there is an effect that the size of the table can be reduced as compared with the case where the variable length code decoding table is realized by one table. Here, the second extracting unit detects a second codeword including a codeword whose run becomes 0 when decoded, and the second decoding unit includes a seventh table having a plurality of regions, here,
Each area stores a level that is decoded together with a run that is 0 from a codeword, and each area has an address with the corresponding codeword as an address and an area with the detected second codeword as an address. Reading the stored level from the seventh table and generating a run having a value of 0 to include a second decoding control means for generating a second set of the run and the level; Is also good.

According to this configuration, since the second decoding means has the variable length code decoding table (seventh table) relating only to the variable length code whose run becomes 0 when decoded, the two codes read from the compressed code sequence When the second code word is a variable-length code with a run of 0, the second decoding means can be used and the size of the decoding table of the second decoding means can be reduced. is there.

Here, the second extracting means detects a second code word having a code length equal to or less than the second predetermined number, and the second decoding means detects an area having an address equal to or less than the second predetermined number. And an eighth table having a plurality of the above, wherein the run and the level are stored in each area, and the address of each area is generated by entropy coding the run and the level stored in the area. A second set of runs and levels by reading from the eighth table a set of runs and levels stored in an area having the detected second codeword as an address. And a second decoding control unit that generates

According to this configuration, the second decoding means has the variable-length code decoding table (eighth table) relating only to variable-length codes having a short code length (less than or equal to the second predetermined length).
When the second codeword of the two codewords read from the compressed code string is a variable length code having a short code length, the second decoding means can be used, and the size of the decoding table of the second decoding means can be reduced. There is an effect that can be.

Here, the signal restoring means, based on the generated first set of run and level, indicates a first position indicating a position at which a level included in the set is arranged in a block.
First address calculating means for calculating the address of the first run, and calculating a second address indicating a position at which the level included in the run is arranged in the block, based on the generated second run and level set Using the second address calculation means for calculating the first address and the calculated first address.
Using the first inverse quantization means for inversely quantizing the levels included in the set and generating the first coefficient, and using the calculated second address, the level included in the generated second set is calculated. A second inverse quantization means for performing inverse quantization to generate a second coefficient; and two sets using the generated set of the first address and the first coefficient and the set of the second address and the second coefficient. And a sub-signal restoring means for restoring the above signal.

According to this configuration, the address calculation and the inverse quantization operation can be performed in parallel for the two sets of runs and levels generated from the cut-out two codewords. There is an effect that quantization operation can be performed. Here, the sub-signal restoring unit includes: a coefficient storage unit; and a set of the generated first address and the first coefficient and a set of the second address and the second coefficient as a set of the address and the coefficient. A coefficient writing unit for writing to the coefficient storage unit, a block storage unit having a plurality of areas indicated by addresses, and a set of an address and a coefficient repeatedly read from the coefficient storage unit, and using the address in the block storage unit. A block writing means for writing the coefficient in the indicated area, and a signal generation for generating two sets of signals by reading out the coefficients stored in a plurality of areas of the block storage means as two sets of signals. Means may be included.

According to this configuration, there is an effect that the signal decoded by the variable-length code decoding device can be written to the buffer without depending on the processing of the external device that reads out the generated signal. Here, the coefficient storage means has a plurality of first data areas, and the coefficient writing means further includes a set of an address and a coefficient,
An ON flag having an ON value is written in a first data area of the coefficient storage unit in which the ON flag is not written, and the block writing unit writes the ON flag of the coefficient storage unit.
A set of an address and a coefficient is repeatedly read out from each first data area in which a flag is written, and when the reading is completed, an ON flag is written in each first data area of the coefficient storage means in which an ON flag is written. OFF with value
You may comprise so that a flag may be written.

The block writing means writes an ON flag having an ON value together with the coefficient in an area indicated by the address, and the signal generation means writes the ON flag after the signal generation is completed. The configuration may be such that an OFF flag having a value other than ON is written in each of the areas. According to this configuration, there is an effect that the number of bits for clearing the contents of each area to 0 can be reduced.

Here, the variable-length code decoding apparatus further includes selection accepting means for accepting selection of one of the decoding of the first compressed code sequence or the decoding of the first and second compressed code sequences, Here, the first compression code string is the compression code string, the second compression code string is another compression code string,
Consists of a sequence of multiple codewords, the signal is quantized,
In addition, the signal includes at least two code words generated by entropy coding, the signal is generated by performing orthogonal transform on a plurality of pieces of image information, and the code cutout means selects decoding of the first compressed code string. Is received, two adjacent codewords are cut out from the first compression code string, and when the selection of decoding the first and second compression code strings is received,
One code word may be cut out from each of the first and second compressed code strings, and the code decoding means may be configured to perform entropy decoding on the cut out two code words in parallel.

According to this configuration, there is an effect that one variable-length code decoding apparatus can select one of decoding one compressed code string or decoding two compressed code strings. When one compressed code string is decoded into a set of signals before encoding, two code words are cut out from the compressed code string, and the two cut out code words are entropy-decoded in parallel. Since the signal before encoding can be decoded, more variable length codes can be decoded per fixed time.

Here, the first and second codewords are cut out as two codewords from the first compression code string, or the first and second codewords are respectively extracted as two codewords from the first and second compression code strings. The code extracting means for extracting a code word is a position storing means for storing first position information and second position information, wherein the first position information is a first compressed code string in a first compressed code string. The second position information indicates a position where the second codeword is disposed in the second compression code string, and the second position information indicates the position where the second codeword is disposed in the second compression code string.
A first extraction unit configured to detect a first codeword arranged from a position indicated by the position information and calculate a first code length indicating a length of the detected first codeword; When decoding is selected, a second codeword located from a position indicated by an added value obtained by adding the first code length to the first position information is detected from the first compressed code string. Then, when decoding of the first and second compressed code strings is selected, a second code word arranged from the position indicated by the second position information is detected from the second compressed code string. Clipping means, wherein when the decoding of the first compressed code string is selected, the detected first
Using the codeword and the second codeword to generate two sets of coefficients,
Generating a set of coefficients using the detected first codeword when decoding of the first and second compressed code strings is selected;
Another set of coefficients may be generated using the detected second codeword.

According to this configuration, when decoding one external compressed code string into a set of signals before encoding, two code words that are continuously arranged are sequentially cut out from the compressed code string. In addition, when decoding two external compressed code strings into two sets of signals before encoding, one compressed code string
There is an effect that each code word can be cut out.

Here, the code word is generated by encoding a set of a run and a level, and the run indicates the number of signals having a value of 0 included in the quantized signal.
The level indicates a 1 signal having a non-zero value included in the quantized signal, and when decoding of the first compressed code string is selected, the first set of the run and the level as two sets of coefficients A set and a second set are generated, and when decoding of the first and second compressed code strings is selected, a first set of a run and a level is generated as one set of coefficients, and another set of The code decoding means for generating a second set of run and level as coefficients is a first decoding means for generating a first set of run and level by entropy decoding the detected first codeword. And second decoding means for generating a second set of run and level by entropy decoding the detected second codeword, wherein the signal decompression means decodes the first compressed code sequence. If selected, a first set and a second set of the generated runs and levels With bets, to restore the two sets of signals, when the decoding of the first and second compression code string is selected by using the first set of said generated run and level,
The signal may be reconstructed, and another signal may be reconstructed using the generated second set of runs and levels.

According to this configuration, when decoding one compressed code string into a set of signals before encoding, the sets of runs and levels generated from the two cut-out codewords are processed in parallel. Since the signal before encoding can be decoded by entropy decoding, more variable-length codes can be decoded per fixed time. Further, when decoding two external compressed code strings into two sets of signals before encoding,
There is an effect that a set of a run and a level generated from each cutout codeword can be independently entropy-decoded to decode a signal before encoding.

Here, the signal restoring means calculates a first address indicating a position where a level included in the set is arranged in a block, based on the generated first set of run and level. First address calculating means, and second address calculating means for calculating, based on the generated second set of runs and levels, a second address indicating a position where a level included in the set is arranged in a block. A first coefficient for dequantizing a level included in the generated first set using the calculated first address to generate a first coefficient;
Inverse quantization means, second inverse quantization means for inversely quantizing the level included in the generated second set using the calculated second address to generate a second coefficient, When the decoding of the compression code string is selected, two sets of signals are restored using the generated first address, first coefficient, second address, and second coefficient, and the first and second compression are performed. When decoding of a code string is selected, a signal is restored using the generated first address and the first coefficient, and another signal is restored using the generated second address and the second coefficient. And a sub-signal restoring unit for restoring a signal.

According to this configuration, when one external compressed code string is decoded into a set of signals before encoding, the two codewords cut out are subjected to address calculation and inverse quantization in parallel. Since the calculation can be performed, there is an effect that more inverse quantization calculation can be performed per fixed time. Further, when decoding two external compressed code strings into two sets of signals before encoding, there is an effect that address calculation and inverse quantization operation can be independently performed for each codeword.

Here, the sub-signal restoring means includes a first coefficient storing means, a second coefficient storing means, and a decoding means which, when decoding of the first compression code string is selected, stores the generated first address and the first address. The set of the first coefficient, the set of the second address and the second coefficient are
When a combination of an address and a coefficient is written in the first coefficient storage unit and decoding of the first and second compressed code strings is selected, the generated set of the first address and the first coefficient is written as: A coefficient to be written to the first coefficient storage means as a set of an address and a coefficient, and the generated set of the second address and the second coefficient to be written to the second coefficient storage means as a set of an address and a coefficient Writing means, first block storage means having a plurality of areas indicated by the address, second block storage means having a plurality of areas indicated by the address, and decoding of the first compression code string is selected. A set of an address and a coefficient is repeatedly read out from the first coefficient storage means, and the coefficient is written to an area indicated by the address in the first block storage means;
And when the decoding of the second compressed code string is selected, a set of an address and a coefficient is repeatedly read out from the first coefficient storage means, and the area of the first block storage means indicated by the address is stored in the area indicated by the address. Is written, and a pair of an address and a coefficient is repeatedly read from the second coefficient storage means,
A block writing unit that writes the coefficient in an area indicated by the address in the second block storage unit;
When the decoding of the compressed code string is selected, two sets of signals are generated by reading out the coefficients stored in the plurality of areas of the first block storage means as two sets of signals. And when decoding of the second compressed code string is selected, a signal is generated by reading out coefficients stored in a plurality of areas of the first block storage means as a signal, and the second block storage is generated. It may be configured to include a signal generation unit that generates another signal by reading out a coefficient stored in a plurality of areas included in the unit as a signal.

According to this configuration, even when one set of signals before encoding is decoded from one compressed code string, two sets of signals before encoding are decoded from two compressed code strings. Also in this case, there is an effect that the signal decoded by the variable-length code decoding device can be written to the buffer without depending on the processing of the external device that reads out the generated signal.

Here, the compressed code string includes at least two codewords generated by quantizing a signal and further entropy coding, and generating the signal by performing orthogonal transform on a plurality of pieces of image information. The code extracting means cuts out two code words generated from the image information,
Codewords are adjacent to each other and each have a code length equal to or less than a third predetermined value, and the parallel decoding means performs entropy decoding on the two codewords using one decoding table, Code decoding means for generating two sets of coefficients, and signal restoring means for generating two sets of signals in parallel by performing inverse quantization based on the two sets of generated coefficients. It may be configured as follows.

According to this configuration, when a single compressed code string including a code word obtained by coding a signal generated from image information is decoded into a set of signals before coding, the code length is short ( (3rd predetermined value or less) When two codewords are continuous, the two codewords are cut out from the compressed code string, and the two cutout codewords are decoded in parallel to obtain a signal before encoding. Can be generated, so that it is possible to decode more variable-length codes per fixed time.

Here, the code word is generated by encoding a set consisting of a run and a level. The run indicates the number of signals having a value of 0 included in the signal. A signal of 1 having a non-zero value contained in
The code extracting means for extracting the first code word and the second code as two adjacent code words includes: a position storage means for storing one piece of position information; ,
In the compression code string, a position where a first code word is stored is indicated, and the first code word arranged from a position indicated by the position information is detected from the compression code string, and the detected A first code length indicating the length of one code word is calculated, and the second code word arranged from a position indicated by an addition value obtained by adding the first code length to the read position is detected. The code decoding means for generating a first set and a second set consisting of a run and a level as two sets of coefficients, the third code word having a third predetermined number or less. A ninth table having a plurality of areas each having an address of a code word formed by combining the first code word and a fourth code word equal to or less than a third predetermined number, wherein each area has a first run and a first level; A set of the second run and the second level is stored, and the third codeword is the first codeword. A code word generated the emissions and the first level in the entropy coding, the fourth codeword, the second
A codeword generated by entropy-encoding the run and the second level, and is stored in an area where an address is a codeword obtained by combining the detected first and second codewords. First run, first level, second run, and second
By reading the level from the ninth table, the first
A first set having a run and a first level as a run and a level;
Decoding control means for generating a second set having a second run and a second level as a run and a level, wherein the signal restoring means comprises a first set of the generated run and level, or It may be configured to include restoring two sets of signals based on the first and second sets of runs and levels.

According to this configuration, from the compressed code string,
It is possible to read out two codewords that are consecutively arranged and each have a short code length, and decodes the two readout codewords in parallel using one decoding table (ninth table). There is an effect that a signal before encoding can be generated.
Here, the signal restoring means calculates a first address indicating a position where a level included in the first set is arranged in a block, based on the generated first set of runs and levels. First address calculating means for calculating a second address indicating a position where a level included in the second set is arranged in a block, based on the generated second set of run and level. A second address calculating means, a first dequantizing means for dequantizing a level included in the first set using the calculated first address to generate a first coefficient, A second inverse quantization means for inversely quantizing levels included in the second set using the second address to generate a second coefficient, and a set of the first coefficient and the first address; Using a set of the second coefficient and the second address, It may be configured to include a sub-signal restoration means for restoring the set of signals.

According to this configuration, the address calculation and the inverse quantization operation can be performed in parallel on the set of the run and the level generated from the two read codewords.
There is an effect that more inverse quantization operations can be performed per fixed time. Here, the sub-signal restoring unit includes: a coefficient storage unit; and a set of the first address and the first coefficient and a set of the second address and the second coefficient as a set of the address and the coefficient. Coefficient writing means for writing to the coefficient storage means, block storage means having a plurality of areas indicated by addresses, and a set of addresses and coefficients repeatedly read out from the coefficient storage means, A block writing means for writing the coefficient in the indicated area, and a signal generation for generating two sets of signals by reading out the coefficients stored in a plurality of areas of the block storage means as two sets of signals. Means may be included.

According to this configuration, there is an effect that the signal decoded by the variable-length code decoding device can be written into the buffer without depending on the processing of the external device that reads out the generated signal. Here, the compressed code sequence includes the same number of types of encoded control information in which at least two types of control information are respectively entropy-coded, and the control information is used to control decoding of image data, The code cutout means includes, as the two codewords,
Two pieces of adjacent coding control information are cut out from the compressed code string, and the parallel decoding unit performs entropy decoding on the two pieces of coding control information in parallel, thereby respectively converting two pieces of control information. You may comprise so that the code | cord decoding means which produces | generates may be included.

According to this configuration, at least two types of control information are respectively encoded, and two pieces of encoded control information are extracted from a compressed code string including the same number of types of encoded control information. Since the control information before encoding can be decoded by entropy decoding the encoded control information in parallel, more variable-length codes can be generated per fixed time.

Here, the code extracting means for extracting the first code word and the second code word as two pieces of encoding control information includes: a position storage means storing one piece of position information; In the position information, the compressed code string indicates a position where the first code word is arranged, and the first code word arranged from the position indicated by the position information is determined from the compressed code string. First extraction means for detecting and calculating a first code length indicating the length of the detected first code word, and addition obtained by adding the first code length to the position information from the compressed code sequence And a second cutout means for detecting a second codeword arranged from a position indicated by the value, wherein the code decoding means performs entropy decoding on the detected first codeword, thereby obtaining one codeword. First decoding means for generating control information; The by 2 to entropy decode the codeword, it may be configured to include a second decoding means for generating the other one of the control information.

According to this configuration, from the compressed code string,
It is possible to sequentially cut out two pieces of encoding control information that are continuously arranged, and there is an effect that control information can be entropy-decoded in parallel from the two pieces of encoding control information. Here, the first decoding means stores a first control information table storing a first codeword and control information in association with each other, and an address at which the first control information table is arranged. Reading a first address table having a first address area, first pointer storage means storing a first pointer indicating an address where the first address area is located, and reading the first pointer;
A first address located at an address indicated by the first pointer
An address area is specified, an address stored in the first address area is read, the first control information table located at the read address is specified, and a first code word is read from the first control information table. And a first decoding control unit that generates one piece of control information by detecting the control information corresponding to.

The second decoding means stores a second control information table storing a second codeword and control information in association with each other, and an address at which the second control information table is arranged. A second address table having a second address area, a second pointer storage unit storing a second pointer indicating an address where the second address area is located, and reading the second pointer. A second address area located at the address indicated by the second pointer is specified, an address stored in the second address area is read, and the second control information table located at the read address is specified. A second decoding control means for generating another piece of control information by detecting control information corresponding to a second codeword from the second control information table; It may be configured to include.

According to this configuration, there is an effect that a decoding signal table (first and second control information tables) for decoding the encoding control information can be specified by the value of the pointer. The present invention also relates to a digital broadcast receiving apparatus for reproducing image information by decoding a compressed code string included in a received digital broadcast wave, and comprising two compressed adjacent code strings from one compressed code string. Code extracting means for extracting code words simultaneously or sequentially, and the compressed code string is composed of a sequence of a plurality of code words, the code word is a variable length code, and the two code words are Parallel decoding means for decoding in parallel.

According to this configuration, in a digital broadcast receiving apparatus that decodes and reproduces coded image information contained in a received digital broadcast wave, two digital codewords from a compressed code string contained in the digital broadcast wave are used. Cut out the code word of
Since the two cut-out codewords are decoded in parallel, it is possible to decode more variable-length codes per fixed time.

The present invention also relates to a DVD reproducing apparatus for reproducing image information by decoding a compressed code string recorded on a DVD, and comprising two adjacent code words from one compressed code string. And the compression code string is composed of a sequence of a plurality of code words, the code word is a variable length code, and the two code words are processed in parallel. and a parallel decoding means for decoding Te, the compression
In the code sequence, the signal is quantized, and the entropy code
Including at least two codewords generated by
The signal is generated by performing orthogonal transformation on a plurality of pieces of image information,
The code extracting means includes two codes generated from image information.
Excised issue words, the two codewords are adjacent, before
The parallel decoding means inputs the two codewords in parallel.
Two sets of coefficients are generated by Ropy decoding
Coding / decoding means for performing coding and decoding based on the generated two sets of coefficients.
Then, by performing inverse quantization, two sets of signals are obtained.
And a signal restoring means for generating the data in parallel.

According to this configuration, in a DVD reproducing apparatus that decodes and reproduces encoded image information recorded on a DVD, two codewords are cut out from a compressed code string recorded on the DVD, and cut out. Since the two codewords are decoded in parallel, more variable-length codes can be decoded per fixed time.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a variable-length code decoding device as one embodiment according to the present invention.

FIG. 2 is a block diagram of a first decoding unit of the variable length code decoding device shown in FIG.

FIG. 3 shows a configuration of a table of a first decoding unit of the variable-length code decoding device shown in FIG.

FIG. 4 shows a scan order of each element in one block.

FIG. 5 is a conversion table of a scan order of each element in one block.

FIG. 6 shows an example of a decoded run and level.

FIG. 7 shows an example of a quantization table.

8 is a flowchart showing the overall operation of the variable length code decoding device shown in FIG.

9 is a flowchart showing an operation of a first bit stream cutout unit of the variable length code decoding device shown in FIG.

10 is a flowchart showing an operation of a first bit length determination unit of the variable length code decoding device shown in FIG.

11 is a flowchart showing an operation of a first decoding control unit of the variable length code decoding device shown in FIG.

FIG. 12 is a flowchart showing an operation of a first address calculation unit of the variable length code decoding device shown in FIG.

13 is a flowchart showing an operation of a first inverse quantization unit of the variable length code decoding device shown in FIG.

FIG. 14 is a time chart showing a transition of an operation by each component over time of the variable length code decoding device shown in FIG. 1;

FIG. 15 shows a block diagram of a variable-length code decoding device as another embodiment according to the present invention. FIG.
followed by.

FIG. 16 shows a block diagram of a variable-length code decoding device as another embodiment according to the present invention. FIG.
It is a continuation from

17 is a flowchart showing an overall operation of the variable length code decoding device shown in FIG. It continues to FIG.

FIG. 18 is a flowchart showing an overall operation of the variable-length code decoding device shown in FIG. It is a continuation from FIG.

FIG. 19 is a time chart showing transition of the operation of each component with time of the variable length code decoding device shown in FIG. 15;

FIG. 20 shows a block diagram of a variable-length code decoding device as another embodiment according to the present invention.

21 is a block diagram of a first decoding unit of the variable-length code decoding device shown in FIG.

FIG. 22 shows a configuration of a third table of the first decoding unit of the variable-length code decoding device shown in FIG.

23 shows a configuration of a fourth table of the first decoding unit of the variable length code decoding device shown in FIG.

24 is a flowchart illustrating an overall operation of the variable-length code decoding device illustrated in FIG.

25 is a flowchart showing an operation of a first decoding control unit of the variable length code decoding device shown in FIG.

26 is a time chart showing transition of the operation of each component over time of the variable-length code decoding device shown in FIG.

FIG. 27 is a block diagram showing a variable-length code decoding device according to another embodiment of the present invention.

FIG. 28 shows a block diagram of a variable-length code decoding device as still another embodiment according to the present invention.

FIG. 29 shows a block diagram of a conventional variable-length code decoding device.

FIG. 30 shows a block diagram of a variable-length code decoding device as still another embodiment according to the present invention.

FIG. 31 shows an example of an information storage section of the variable-length code decoding device shown in FIG.

FIG. 32 is a block diagram of a first decoding unit of the variable-length code decoding device shown in FIG.

FIG. 33 shows an example of an MBT table of a first decoding unit of the variable length code decoding device shown in FIG.

34 is a flowchart showing the operation of the decoding process of the variable length code decoding device shown in FIG.

FIG. 35 is a flowchart showing the operation of the header information decoding process of the variable length code decoding device shown in FIG.

36 is a flowchart illustrating an operation of a process of a first decoding control unit of the variable-length code decoding device illustrated in FIG. 30.

FIG. 37 is a block diagram of a digital broadcast receiving device as one application example of the variable-length code decoding device of the present invention.

FIG. 38 is a block diagram of a DVD playback device as one application example of the variable-length code decoding device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Variable-length code decoding device 101 1st bit stream buffer 102 1st bit stream extraction part 103 1st bit length determination part 104 1st decoding part 105 1st address calculation part 106 2nd bit stream extraction part 107 2nd Bit length determination unit 108 Second decoding unit 109 Second address calculation unit 118 First buffer controller 119 First buffer 120 First inverse quantization unit 121 Second inverse quantization unit 122 Second buffer controller 123 Second buffer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-104767 (JP, A) JP-A-7-212242 (JP, A) JP-A-61-84125 (JP, A) JP-A-63- 299520 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/40 G11B 20/10 341 H04N 5/92 H04N 7/24

Claims (25)

(57) [Claims] 1. A variable-length code decoder for decoding a variable-length code.
Apparatus, wherein two adjacent code words from one compressed code sequence are simultaneously
Or a code extracting means for sequentially extracting the compressed code string,
Cage, wherein the code word is a variable length code, and a parallel decoding means for decoding in parallel the two codewords
The compressed code sequence includes at least two code words generated by quantizing a signal and further performing entropy coding, and the signal is generated by performing orthogonal transform on a plurality of pieces of image information, The extracting unit extracts two codewords generated from the image information, the two codewords are adjacent to each other, and the parallel decoding unit performs entropy decoding on the two codewords in parallel. Code decoding means for generating two sets of coefficients, and signal restoration means for generating two sets of signals in parallel by performing inverse quantization based on the two sets of generated coefficients. DOO variable-length code decoding device you comprising a. 2. The codeword is generated by encoding a set of a run and a level, wherein the run indicates the number of signals having a value of 0 included in the quantized signal, and the level is a level. , A 1 signal having a non-zero value included in the quantized signal, and the code extracting means for extracting a first code word and a second code word as two adjacent code words, The position information, which stores one piece of position information, includes: a position storage unit that indicates a position where a first codeword is arranged in the compressed code string; A first codeword located from the position shown is detected, and the detected first codeword is detected.
First extracting means for calculating a first code length indicating a length of a code word; and an arrangement from a position indicated by an added value obtained by adding the first code length to the position information from the compressed code string. And a second cutout means for detecting a second codeword that has been processed, wherein the code decoding generates a first set and a second set composed of a run and a level as the two sets of coefficients. Means for entropy decoding the detected first codeword to generate a first set consisting of a run and a level; and entropy decoding the detected second codeword. And a second decoding means for generating a second set composed of a run and a level, wherein the signal restoring means includes the first set and the second set.
Based on the set, the variable length code decoding apparatus according to claim 1, characterized in that to produce the two sets of signals. 3. The first decoding means includes: a first table having a plurality of areas having addresses equal to or less than a first predetermined number, wherein each area stores a set of a run and a level; The address of each area is a codeword generated by entropy-encoding the run and the level stored in the area, a second table having a plurality of areas having addresses larger than the first predetermined number, Here, different values are stored in the respective areas, a third table having the same number of areas as the number of areas in the second table, and each of the areas is Corresponding to an area, each of the areas has a value stored in the corresponding area of the second table as an address, and in each of the areas, a set of a run and a level is stored;
The address of each area included in the second table is a codeword generated by entropy-encoding the run and the level stored in the corresponding area included in the third table, and If the one code length is equal to or less than the first predetermined number, the run and level are read out from the first table by reading the set of run and level stored in the area having the first codeword as an address. When the calculated first code length is greater than the first predetermined number, a value stored in an area having the first codeword as an address is converted to the second set. By reading from the table and reading out a set of run and level stored in an area having the read value of the third table as an address,
The variable length code decoding apparatus according to claim 2 , further comprising: first decoding control means for generating a first set of a run and a level. 4. The second decoding means comprises: a fourth table having a plurality of areas having addresses equal to or less than a first predetermined number, wherein each area stores a set of run and level; The address of each area is a codeword generated by entropy-encoding the run and the level stored in the area, a fifth table having a plurality of areas having addresses larger than the first predetermined number, Here, different values are stored in the respective areas, and a sixth table having the same number of areas as the number of the areas in the fourth table; Corresponding to an area, each of the areas has a value stored in the corresponding area of the fourth table as an address, and in each of the areas, a set of a run and a level is stored;
The address of each area included in the fifth table is a codeword generated by entropy-encoding the run and the level stored in the corresponding area included in the sixth table, and the detected When the two codewords are equal to or less than the first predetermined number, the run and level are read out from the fourth table by reading the set of run and level stored in the area addressed to the second codeword. When the detected second codeword is larger than the first predetermined number, a value stored in an area having the second codeword as an address is set to the fifth set. By reading from the table and reading a set of run and level stored in an area having the read value of the sixth table as an address,
4. The variable-length code decoding apparatus according to claim 3 , further comprising: a second decoding control unit that generates a second set of runs and levels. 5. The second extraction means detects a second codeword consisting of codewords whose run becomes 0 when decoded, wherein the second decoding means comprises a seventh table having a plurality of regions. Here, each area stores a level to be decoded together with a run that is 0 from the codeword, and each area has a corresponding codeword as an address, and the detected second codeword is The level stored in the area to be the address is read from the seventh table,
4. The variable-length code decoding apparatus according to claim 3 , further comprising: a second decoding control unit configured to generate a second set of the run and the level by generating a run having the following value: 6. The second extracting means detects a second codeword having a code length equal to or less than the second predetermined number, and the second decoding means detects an area having an address equal to or less than a second predetermined number. An eighth table having a plurality of tables, wherein runs and levels are stored in each area, and addresses of the areas are generated by entropy encoding the runs and levels stored in the areas. A second set of runs and levels by reading from the eighth table a set of runs and levels stored in an area having the detected second codeword as an address. And a second decryption control means for generating.
3. The variable-length code decoding device according to 3. 7. The signal restoring means, based on the first set of the generated run and level,
A first address calculating means for calculating a first address indicating a position at which a level included in the set is arranged in a block; and a second set of the generated run and level,
Second address calculating means for calculating a second address indicating a position at which the level included in the set is arranged in the block; and using the calculated first address to be included in the generated first set. A first inverse quantizer for inversely quantizing a level to be generated to generate a first coefficient, and inversely quantizing a level included in the generated second set using the calculated second address. , A second inverse quantization means for generating a second coefficient, a set of the generated first address and the first coefficient, and a second
Using a set of the address and a second coefficient, claim, characterized in that it comprises a sub-signal restoration means for restoring the two sets of signals 4
7. The variable length code decoding device according to any one of claims 6 to 6 . 8. The sub-signal restoring means comprises: coefficient storage means; a set of the generated first address and first coefficient;
Coefficient writing means for writing a set of an address and a second coefficient as a set of an address and a coefficient in the coefficient storage means; a block storage means having a plurality of areas indicated by the address; A block writing unit that repeatedly reads a set of a coefficient and a coefficient and writes the coefficient in an area indicated by the address in the block storage unit; and a coefficient stored in a plurality of areas of the block storage unit. By reading as two sets of signals,
The variable-length code decoding apparatus according to claim 7 , further comprising a signal generation unit configured to generate a set of signals. 9. The coefficient storage means includes a plurality of first data areas, and the coefficient writing means includes a set of an address and a coefficient,
Further, an ON flag having an ON value is written in the first data area of the coefficient storage unit in which the ON flag is not written, and the block writing unit writes each of the ON flags of the coefficient storage unit in which the ON flag is written. A set of an address and a coefficient is repeatedly read from the first data area, and when the reading is completed, an OFF flag having a value other than ON is written into each first data area of the coefficient storage means in which the ON flag is written. 9. The variable-length code decoding device according to claim 8 , wherein: 10. The block writing means writes an ON flag having an ON value together with a coefficient into an area indicated by the address, and the signal generation means writes the ON flag after the signal generation is completed. OF with values other than ON in each area
9. The variable-length code decoding device according to claim 8 , wherein an F flag is written. 11. The variable-length code decoding device further includes a selection receiving unit that receives selection of one of decoding of a first compressed code sequence or decoding of first and second compressed code sequences. Wherein the first compression code sequence is the compression code sequence, and the second compression code sequence is another compression code sequence, which is composed of a sequence of a plurality of code words, the signal is quantized, and the entropy code The generated codewords to at least 2
And the signal is generated by performing orthogonal transformation on a plurality of pieces of image information, and the code extracting unit is configured to, when a selection of decoding the first compressed code string is received, receive the signal from the first compressed code string. Two adjacent code words are cut out, and when the selection of decoding the first and second compressed code strings is accepted, one code word is cut out from each of the first and second compressed code strings, The said code decoding means performs entropy decoding of the two cut-out codewords in parallel.
2. The variable-length code decoding device according to 1. 12. The first and second codewords are cut out from the first compression code string as two codewords, or the first and second codewords are respectively extracted from the first and second compression code strings as two codewords.
The code extracting means for extracting a code word comprises: a position storing means for storing first position information and second position information; wherein the first position information is:
The first codeword indicates a position where the first codeword is arranged, and the second position information indicates a position where the second codeword is arranged in the second compression code string. A first code word arranged from a position indicated by the one position information, and a first code length indicating a length of the detected first code word is calculated;
Extracting means; and a position indicated by an added value obtained by adding the first code length to the first position information from the first compressed code string when decoding of the first compressed code string is selected. , And when decoding of the first and second compressed code strings is selected, the second code word is arranged from the position indicated by the second position information from the second compressed code string. And a second extracting unit that detects a second code word that is present, wherein the decoding unit decodes the detected first code word and the second code when decoding of the first compressed code string is selected. A set of coefficients is generated using the detected first codeword, when decoding of the first and second compressed code strings is selected using the word,
Using said detected second codeword, the variable-length code decoding device according to claim 1 1, characterized in that to generate another set of coefficients. 13. The codeword is generated by encoding a set of a run and a level, where the run indicates the number of signals having a value of 0 included in the quantized signal, and the level is a level. , A 1 signal having a non-zero value included in the quantized signal, and when the decoding of the first compressed code string is selected, the first set of run and level as two sets of coefficients. Generate a second set and
When decoding of the first and second compressed code strings is selected, 1
The code decoding means for generating a first set of a run and a level as a set of coefficients, and generating a second set of a run and a level as another set of coefficients, comprises: First decoding means for generating a first set of run and level by entropy decoding of the following, and generating a second set of run and level by entropy decoding of the detected second codeword A second decoding unit, wherein when the decoding of the first compressed code string is selected, the signal restoring unit uses the first and second sets of the generated runs and levels to generate 2 Reconstructing a set of signals and, if decoding of the first and second compressed code strings is selected, reconstructing a signal using the first set of the generated runs and levels, And restoring another signal using a second set of and level. Variable-length code decoding device according to claim 1 2. 14. The signal restoring means calculates a first address indicating a position where a level included in the set is arranged in a block based on the generated first set of runs and levels. (1) address calculating means; and second address calculating means for calculating, based on the generated second set of runs and levels, a second address indicating a position where a level included in the set is arranged in a block. Using the calculated first address, dequantize a level included in the generated first set to generate a first coefficient; and the calculated second address. A second dequantizing means for dequantizing the level included in the generated second set to generate a second coefficient, and when decoding of the first compressed code string is selected, Generated first address and first coefficient Two sets of signals are restored using the second address and the second coefficient, and when the decoding of the first and second compressed code strings is selected, the generated first address and the first coefficient are converted. used to restore the signal, by using the second address and the second coefficient the generated variable according to claim 1 3, characterized in that it comprises a sub-signal restoration means for restoring the other signal Long code decoding device. 15. The first signal storage means, the second coefficient storage means, and when the decoding of the first compressed code string is selected, the generated first address and the first When a set of coefficients, a set of second addresses, and a set of second coefficients are written to the first coefficient storage means as a set of addresses and coefficients, and decoding of the first and second compressed code strings is selected. Then, the set of the generated first address and the first coefficient is written to the first coefficient storage means as the set of the address and the coefficient, and the set of the generated second address and the second coefficient is written. ,
Coefficient writing means for writing to the second coefficient storage means as a set of addresses and coefficients; first block storage means having a plurality of areas indicated by addresses; second block having a plurality of areas indicated by addresses; A storage unit, when decoding of the first compression code string is selected, a set of an address and a coefficient is repeatedly read out from the first coefficient storage unit, and stored in an area indicated by the address in the first block storage unit. Writing the coefficients, and when the decoding of the first and second compressed code strings is selected, a set of an address and a coefficient is repeatedly read out from the first coefficient storage means, and the address in the first block storage means is read out. The coefficient is written in an area indicated by, and a set of an address and a coefficient is repeatedly read out from the second coefficient storage means. A block writing means for writing the coefficient in an area indicated by the address, and a plurality of areas stored in the first block storage means when decoding of the first compression code string is selected. By reading out the coefficients as two sets of signals, two sets of signals are generated and stored in a plurality of areas of the first block storage means when decoding of the first and second compressed code strings is selected. Signal generating means for generating a signal by reading out the set coefficient as a signal and reading out the coefficient stored in a plurality of areas of the second block storage means as a signal to generate another signal variable-length code decoding device according to claim 1 4, characterized in that it comprises and. 16. Variable length code decoding for decoding a variable length code.
A compression apparatus for simultaneously converting two adjacent codewords from one compressed code sequence.
Or a code extracting means for sequentially extracting the compressed code string,
Cage, wherein the code word is a variable length code, and a parallel decoding means for decoding in parallel the two codewords
The compressed code sequence includes at least two code words generated by quantizing a signal and further performing entropy coding, wherein the signal is generated by performing orthogonal transform on a plurality of pieces of image information, The cutout unit cuts out two codewords generated from the image information, the two codewords are adjacent to each other and each have a code length equal to or less than a third predetermined value, Code decoding means for generating two sets of coefficients by entropy decoding the two code words using one decoding table; and performing inverse quantization based on the generated two sets of coefficients. by subjecting each variable length code decoding device you; and a signal restoring means for generating in parallel two sets of signals. 17. The codeword is generated by encoding a set of a run and a level, wherein the run indicates the number of signals having a value of 0 included in the signal, and the level indicates the number of signals included in the signal. The code extracting means for indicating a signal of 1 having a value other than 0 included therein, and extracting the first code word and the second code as two adjacent code words, stores one position information, Position storage means, wherein the position information is within the compression code string,
The position where the first code word is stored is detected. The first code word arranged from the position indicated by the position information is detected from the compressed code string, and the length of the detected first code word is calculated. Sub-cutout means for calculating a first code length shown and detecting the second code word arranged from a position indicated by an added value obtained by adding the first code length to the read position. The code decoding means for generating a first set and a second set comprising a run and a level as two sets of coefficients includes: a third code word equal to or less than a third predetermined number and a third code word equal to or less than a third predetermined number. A ninth table having a plurality of regions each having an address of a code word formed by combining the fourth code word, wherein each region has a first run and a first level, a second run and a second level, And the third codeword encodes the first run and the first level. The fourth codeword is a codeword generated by entropy coding the second run and the second level, and the fourth codeword is a codeword generated by entropy coding the second run and the second level. By reading the first run, the first level, the second run, and the second level stored in an area whose address is a code word obtained by combining the first and second words from the ninth table, Decoding control means for generating a first set having one level as a run and a level and a second set having a second run and a second level as a run and a level; 2. The method of claim 1, further comprising restoring two sets of signals based on the generated first set of runs and levels, or the first and second sets of runs and levels. 7. The variable length code decoding device according to item 6 . 18. The signal restoration means according to claim 1, wherein:
A first address calculating means for calculating a first address indicating a position where a level included in the first set is arranged in a block; and a second set of the generated run and level,
A second address calculating means for calculating a second address indicating a position at which a level included in the second set is arranged in the block; and a second address calculated using the calculated first address. A first inverse quantization means for inversely quantizing the level to be generated to generate a first coefficient; and a second level by dequantizing the level included in the second set using the calculated second address A second inverse quantizer for generating a coefficient; and a sub-signal for restoring two sets of signals using a set of the first coefficient and the first address and a set of the second coefficient and the second address. The variable length code decoding apparatus according to claim 17 , further comprising a restoration unit. 19. The sub-signal restoring unit includes: a coefficient storage unit; a set of the first address and the first coefficient and a set of the second address and the second coefficient; A coefficient writing means for writing to the coefficient storage means, a block storage means having a plurality of areas indicated by addresses, and a set of an address and a coefficient repeatedly read out from the coefficient storage means, A block writing means for writing the coefficient in an area indicated by an address; and a coefficient stored in a plurality of areas of the block storage means being read as two sets of signals,
19. The variable-length code decoding apparatus according to claim 18 , further comprising: signal generation means for generating a set of signals. 20. Variable length code decoding for decoding a variable length code
A compression apparatus for simultaneously converting two adjacent codewords from one compressed code sequence.
Or a code extracting means for sequentially extracting the compressed code string,
Cage, wherein the code word is a variable length code, and a parallel decoding means for decoding in parallel the two codewords
The compressed code sequence includes the same number of types of encoded control information in which at least two types of control information are respectively entropy-encoded, and the control information is used for controlling decoding of image data; The cutout means cuts out adjacent two pieces of encoding control information from the compressed code string as the two codewords, and the parallel decoding means executes the two pieces of encoding control information in parallel. It further includes code decoding means for generating two pieces of control information by performing entropy decoding.
That variable-length code decoding device. 21. A code extracting means for extracting a first codeword and a second codeword as two pieces of encoding control information, a position storage means storing one piece of position information; , The position information is within the compression code string,
The first codeword indicates a position where the first codeword is arranged, and the first codeword arranged from the position indicated by the position information is detected from the compressed code string, and the detected first codeword is detected.
First extracting means for calculating a first code length indicating a length of a code word; and an arrangement from a position indicated by an added value obtained by adding the first code length to the position information from the compressed code string. A second cutout unit that detects a second codeword that has been processed, and the code decoding unit performs entropy decoding on the detected first codeword to generate one piece of control information. and decoding means, by entropy decoding a second codeword said detected variable length according to claim 2 0, characterized in that it comprises a second decoding means for generating the other one of the control information Code decoding device. 22. The first decoding means, wherein a first codeword and control information are stored in association with each other.
A control information table, a first address table having a first address area storing an address where the first control information table is located, and a first pointer indicating an address where the first address area is located First pointer storage means for storing the first pointer, reading the first pointer, specifying a first address area located at an address indicated by the first pointer,
An address stored in the first address area is read, and the first address located at the read address is read.
A first decoding control unit for generating one piece of control information by specifying a control information table and detecting control information corresponding to a first codeword from the first control information table. variable-length code decoding device according to claim 2 1. 23. The second decoding means, wherein a second code word and a control information are stored in association with each other.
A control information table, a second address table having a second address area storing an address where the second control information table is located, and a second pointer indicating an address where the second address area is located A second pointer storage means for storing the second pointer, reading the second pointer, identifying a second address area located at an address indicated by the second pointer,
An address stored in the second address area is read, and the second address located at the read address is read.
A second decoding control means for specifying a control information table and detecting control information corresponding to a second codeword from the second control information table to generate another piece of control information. variable-length code decoding device according to claim 2 2,. 24. A digital broadcast receiving apparatus for decoding a compressed code sequence included in a received digital broadcast wave to reproduce image information, wherein two codes adjacent to each other from one compressed code sequence Code extracting means for extracting words simultaneously or sequentially; the compressed code string is composed of a sequence of a plurality of code words; the code words are variable-length codes; And a parallel decoding means for decoding the compressed code string , wherein the compressed
Include at least two codewords generated by
The signal is obtained by performing orthogonal transformation on a plurality of pieces of image information.
And the code extracting means includes two codes generated from the image information.
Codewords, the two codewords are adjacent to each other, and the parallel decoding means performs entropy decoding of the two codewords in parallel.
Code decoding means for generating two sets of coefficients by
And performs inverse quantization based on the generated two sets of coefficients.
Thus, two sets of signals are generated in parallel.
Digital broadcast receiving apparatus according to claim Rukoto a No. restoring means. 25. A DVD reproducing apparatus for reproducing image information by decoding a compressed code string recorded on a DVD, wherein two adjacent codewords are simultaneously or sequentially read from one compressed code string. A code extracting unit for extracting the compressed code string from a plurality of code words, the code word being a variable length code, and a parallel decoding method for decoding the two code words in parallel. Decoding means , wherein the compressed code string is obtained by quantizing a signal,
Include at least two codewords generated by
The signal is obtained by performing orthogonal transformation on a plurality of pieces of image information.
And the code extracting means includes two codes generated from the image information.
Codewords, the two codewords are adjacent to each other, and the parallel decoding means performs entropy decoding of the two codewords in parallel.
Code decoding means for generating two sets of coefficients by
And performs inverse quantization based on the generated two sets of coefficients.
Thus, two sets of signals are generated in parallel.
DVD playback apparatus according to claim Rukoto a No. restoring means.