JP3285153B2 - DC level shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIG. 4) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 3) Action Embodiment (FIGS. 1 to 3) (1) First Embodiment Example (FIG. 1) (2) Second Embodiment (FIG. 2) (3) Other Embodiment (FIG. 3) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC level shift circuit, and is suitably applied to, for example, a clamp circuit used in a luminance adjustment circuit.

[0003]

2. Description of the Related Art Conventionally, in a television receiver,
Extracting luminance signals from the television signal output from the video detection circuit and supplies it to a video amplifier circuit 1, the input luminance signal V _in in the video amplifier circuit 1
The pedestal level and contrast are adjusted to drive a cathode ray tube 2 (hereinafter referred to as a CRT (cathode ray tube)) (FIG. 4).

[0004] That video amplifier circuit 1, the luminance signal V _in
Was supplied to the contrast adjustment circuit 4 via an input resistor R _IN connected to the output terminal and input to the amplifier 3 via the capacitor C1, the power amplifier 5 to the amplified luminance signal V _in in the contrast adjustment circuit 4 The CRT 2 is supplied via the CRT 2.

[0005] Video amplifier circuit 1 is adapted to enter the pedestal level of the luminance signal V _in is amplified by the contrast adjustment circuit 4 to the differential amplifier 6 at the timing of the clamp pulse CLP.

[0006] Here, the other end of the differential amplifier 6 have been made so that the reference voltage E _BRT is inputted through the buffer amplifier 7, a pedestal level reference voltage by connexion luminance signal V _in the temperature characteristic E _BRT The feedback control is performed so as not to deviate.

The contrast adjusting circuit 4 is composed of a pair of differential pairs 4A and 4B cascaded with each other. The luminance signal V is applied to a common emitter of the transistors Q1 and Q2 to which the reference voltage E3 and the bias voltage ΔE _CONT are applied. It has been made to enter _in.

The contrast adjusting circuit 4 is adapted to adjust the bias voltage ΔE _CONT by means of a contrast adjusting volume. The contrast adjusting circuit 4 adjusts the collector current I _C flowing into the current source 8 from a load resistor _RL connected to the collector of the transistor Q1. The amount of current is controlled, and the gain G (R _L / (R
_IN + r _e)) are adapted to adjust the.

[0009]

However, in the case of the video amplifying circuit 1, the output signal V1 of the contrast adjusting circuit 4 is supplied to the CRT 2 via the power amplifier 5, so that the pedestal level of the output signal V1 is reduced. possibility that the clamp level of the luminance signal V2 inputted to Yotsute CRT2 the influence of the temperature characteristics of the power amplifier 5 also coincides with the reference voltage E _BRT shifts has been made.

Further, the video amplifier circuit 1 outputs a broadband luminance signal V.
When entering _in, but must be small input resistance R _IN and the load resistor R _L in order to stretch the high frequency band, the accompanying emitter resistor r _e of the transistor Q1 which with respect to the input resistor R _IN Can no longer be ignored and the reference voltage E
_{When the} input bias changes with the adjustment of the _BRT , the output gain of the contrast adjustment circuit 4 fluctuates.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above points, and eliminates the temperature characteristics of a DC level and also adjusts the DC level of a wideband input signal so that the output gain does not fluctuate with the adjustment. This is to propose a shift circuit.

[0012]

According to the present invention, there is provided a pair of grounded base-type differential pairs 4A and 4B cascaded with each other. amplifies the input signal input and the preamplifier 3 and 4 to the collector output to the emitter, a main amplifier unit 5 for power-amplifying an input signal V _in is amplified by the preamplifier 3 and 4, the output from the main amplifier section 5 DC level of output signal V2 and reference DC level E _BRT
Is input to the differential output terminal, and the differential output is fed back to the midpoint of connection between the common emitters of the preamplifiers 3 and 4 and the predetermined current sources 8 and 9 so that the current to the current sources 8 and 9 is fed back. By controlling the amount, the preamplifier unit 3,
DC voltage control means 6 for controlling the DC level of the output signal V2 to be constant by clamping the input bias voltage of the output signal V4 to a predetermined value, and making the output potential of the preamplifier section always constant with respect to the reference DC level. Power supply voltage setting means E for fixing the output dynamic ranges of the third and fourth constants
0 is provided.

[0013]

The output signal V2 output from the main amplifier section 5
Common emitter and a predetermined current source 8, 9 of the differential output of the DC level and a reference DC level E _BRT preamplifier 3 and 4
A feedback point is provided at the midpoint of connection with the current sources 8 and 9 to control the amount of current to the current sources 8 and 9.
By clamping the input bias voltage to a predetermined value, the DC level can be matched with the reference DC level _EBRT without temperature characteristics.

Each differential pair 4A of the preamplifiers 3, 4
4B common grounded second and third transistors Q21, Q22 connected between the common emitter of 4B and the current sources 8, 9.
The input bias voltage of the preamplifiers 3 and 4 is clamped to a predetermined value by controlling the emitter potentials of the preamplifiers 3 and 4 to be equal to each other, thereby effectively avoiding the possibility that the gain fluctuates even when the reference DC level _EBRT is varied. can do.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) First Embodiment In FIG. 1 in which parts corresponding to those in FIG. 5 are assigned the same reference numerals, reference numeral 10 denotes a video amplification circuit as a whole, and a video amplification circuit 10 Output luminance signal V1
, The drive V2 input to the CRT 2 is connected to the attenuator 1
1 to the inverting input terminal of the differential amplifier 6.

[0017] Thus the video amplifier circuit 10 can be fed back controls the input clamping level as the pedestal level of the luminance signal V2 is equal to the reference voltage E _BRT, as the pedestal level does not by connexion vary the temperature characteristic It has been done.

The video amplifying circuit 10 _applies a constant voltage E _BRT to the reference voltage _EBRT input to the non-inverting input terminal of the differential amplifier 6.
0 is supplied to the other end of the load resistor _{RL in place} of the power supply voltage V _CC , and the output dynamic range is adjusted to a constant voltage E0.
Is fixed so that the clamp does not come off when the luminance level fluctuates.

In the above configuration, the video amplification circuit 10
Changes the pedestal level of the input luminance signal V _IN according to the input bias voltage of the amplifier 3 when the input luminance signal V _IN is input to the amplifier 3 via the capacitor C 1, and drives the CRT 2 through the power amplifier 5 to drive the CRT 2 Drive at V2.

The video amplifier 10 in this case, the pedestal level of the drive signal V2 supplied to CRT2 through the power amplifier 5 when incorporated into the differential amplifier 6 at the timing of the clamp pulse is compared with a reference voltage E _BRT, The input bias voltage of the amplifier 3 is increased or decreased based on the differential output.

That is, when the pedestal level is equal to the reference voltage E
If the pedestal level is higher than the _BRT , the differential amplifier 6 raises the input bias voltage of the amplifier 3 to flow the current i from the amplifier 3 into the constant current source 8 and reduces the collector current flowing through the load resistor _RL , thereby lowering the pedestal level. Set.

When the pedestal level is equal to the reference voltage E _BRT
If it is lower , the differential amplifier 6 lowers the input bias voltage of the amplifier 3 and supplies the current i to the amplifier 3 via the input resistor R _IN.
, The pedestal level is set high by increasing the collector current flowing through the load resistance _RL .

With this feedback control, the video amplifier circuit 10 can eliminate the temperature dependence of the pedestal level.

The video amplifying circuit 10 can control the reference voltage E when adjusting the brightness of the entire screen displayed on the CRT 2.
By adjusting the voltage of the _BRT , the brightness of the screen can be adjusted.

[0025] That is by increasing the voltage value of the reference voltage E _BRT from the current value only Delta] E, totally dark pedestal level Delta] E content greater Do connexion screen drive signal V2
Ku can, if small as Delta] E, overall the pedestal level Delta] E min small and connexion screen drive signal V2 bright
Can torque can be adjusted to a desired brightness.

In the case of the video amplifier circuit 10, the potential difference between the load resistors _RL for outputting the drive signal V2 is always fixed to a constant voltage E0 even if the voltage value of the reference voltage V _BRT is increased or decreased in order to adjust the luminance. Input clamp does not come off during adjustment.

This is because the power supply potential applied to the load resistor R _L also increases or decreases by ΔE in accordance with the increase or decrease (ΔE) of the reference voltage V _BRT.

[0028] that is, the power supply potential supplied to the load resistor R _L is a is fixed to the reference power supply V _CC, it is set to the maximum of the pedestal level V _PDH which the potential of the output terminal P0 can be adjusted by the reference voltage E _BRT, amplifier 3, the current i1 flows into the current source 8 and the input bias voltage V
_{Between INH} and pedestal level V _PDH ,

(Equation 1) Holds.

When the potential of the output terminal P0 is set to the minimum pedestal level V _PDL that can be adjusted by the reference voltage V _BRT , the current i2 flows from the input resistor R _IN into the amplifier 3, and the input bias voltage V _{INL of the} amplifier 3 and between the pedestal level V _PDL of that time, the following equation

(Equation 2) And the following equation holds between the two pedestal levels:

(Equation 3) As shown in FIG. 5, both input bias voltages V
_A voltage difference also occurs between _INH and V _INL .

On the other hand, in the case of the video amplifier circuit 10, the pedestal level is set to the maximum value V _PDH and the minimum value V _PDH, respectively.
_Assuming that the reference voltages for _PDL are V _MAX and V _MIN , both the reference voltages V _MAX and V _MIN and the pedestal level V
It is between _PDH and V _PDL, the following equation

(Equation 4)

(Equation 5) Holds.

In the equations (4) and (5), α
Indicates an amplification degree and an attenuation amount, and can be represented by a change amount between both the amplification degree, the attenuation amount and the reference voltage, and can be set to an arbitrary value.

At this time, the following equation is provided between the voltage difference between the two voltages and the input bias voltage.

(Equation 6) When the constant α is set to 1 and the left side becomes 0, the input bias voltages V _INH and V _INH are set.
_There is no difference between _INLs .

As described above, in the case of the video amplifier circuit 10, the input bias voltage does not change even if the reference voltage V _BRT is increased or decreased to adjust the luminance, and the input voltage difference of the differential amplifier 6 hardly changes. It settles to a steady state, and it turns out that an input clamp is hard to come off.

In addition, as a result of the input clamp being less likely to come off, the currents i1 and i2 input / output to / from the amplifier 3 may be small, the power consumption is much smaller than in the prior art, and the driving capability of the transistor Q1 is low. Can be used.

[0035] According to the above configuration, by well as fed back controlled to match the pedestal level of the drive signal V2 at the input terminal of CRT2 the reference voltage V _BRT, fixes the output dynamic range to a constant voltage E0, The temperature characteristics of the pedestal level can be eliminated, and the possibility that the input clamp will come off even if the luminance is adjusted by increasing or decreasing the reference voltage V _BRT can be effectively eliminated.

(2) Second Embodiment In FIG. 2, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, reference numeral 20 denotes a video amplifier circuit as a whole, and a luminance signal having a wide frequency band of an input signal is input. In such a case, the output dynamic range is not fluctuated during the brightness adjustment.

In the case of this embodiment, a transistor Q20 cascode-connected to the transistor Q1 is connected between the load resistor _RL and the transistor Q1, and a differential point is connected to the transistor Q20 and the midpoint P20 between the transistor Q20 and Q1. The output terminal of the amplifier 6 is connected.

[0038] Thus the video amplifier circuit 20 fed back controls the collector current I _C flowing through the by connexion load resistor R _L to the differential amplifier 6 is adapted to control the pedestal level constant.

A common base transistor Q2 is connected between the common emitters of the differential pairs 4A and 4B and the constant current sources 8 and 9.
1 and Q22 are connected.

Here, the input terminal of the amplifier 21 is connected to the midpoint P22 between the amplifier 3 and the input resistor R _IN and the transistor Q22.
And the connection point P23 between the constant current source 9 and
Emitter resistance r _e of the base-grounded transistor Q21 are made the input bias voltage of the amplifier 3 by the amplifier 21 to be constant at all times so as to fed back controlled to be constant.

In this embodiment, the constant voltage E0 controls the hold voltage of the capacitor C20 for supplying the hold voltage to the differential amplifier 6 to be constant regardless of the fluctuation of the reference voltage.

In the above configuration, the video amplifying circuit 20
Is compared with the reference voltage V _BRT Incorporating a drive signal V2 to the differential amplifier 3 at the timing of a clamp pulse, controls the collector current I _C flowing in the load resistor R _L as the pedestal level of the drive signal V2 is constant I do.

At this time, the amplifier 21 compares the potentials of the connection midpoints P22 and P23 at the timing of the clamp pulse, and controls the two voltages so that they match (ie, almost no current flows through the input resistor R _IN). Control the input bias to be constant,
The gain does not fluctuate during the brightness adjustment.

For example, in order to input an input luminance signal V _{IN in} a wide frequency band, the resistance values of the input resistor R _IN and the additional resistor _RL must be reduced because the frequency band needs to be widened. While emitter resistance r _e of can not be ignored with respect to the input resistor R _iN, the amplifier 21
Gain does not vary be varied luminance for Yotsute emitter resistance r _e is controlled to be constant to.

According to the above configuration, the video amplifying circuit 20
By clamping the input bias voltage at the input stage of the common base amplifier, the gain can be stabilized regardless of the luminance adjustment, and the temperature characteristics of the pedestal level can be eliminated.

(3) Other Embodiments In the above-described embodiment, the case where the output dynamic range is fixed to the constant voltage E0 and the bias voltage is clamped at the input stage of the common base amplifier circuit has been described. The present invention is not limited to this, and can be widely applied to the case where the bias voltage at the input stage of the grounded base amplifier circuit is clamped at the timing of the clamp pulse as shown in FIG.

Thus, the video amplifier circuit 30 can secure a wide output dynamic range even when the power supply voltage V _CC is low, and can obtain the same effects as described above.

In the above-described embodiment, the luminance of the video is adjusted by controlling the pedestal level of the drive signal V2 output from the power amplifier 5 to a predetermined potential by using the video amplifier circuits 10, 20, and 30. Although the case has been described, the present invention is not limited to this, and may be applied to a case where the grid voltage of the CRT 2 is controlled to a predetermined potential.

Further, in the above-described embodiment, the case where the constant α is set to 1 has been described. However, the present invention is not limited to this. If the constant α is 0.5 or more, it is more preferable to fix the output dynamic range. , The input bias voltage can be reduced.

This corresponds to the difference voltages (V _PDH -V _PDL ) and (V
_MAX− V _MIN ) is approximately equal, so that when the constant α is set to 0.5 or more, the value can be obtained by making the left side of the equation (6) smaller than the left side of the equation (3).

Further, in the above-described embodiment, the case where the present invention is used for clamping the pedestal level has been described. However, the present invention is not limited to this, and is widely applied to other circuits that shift while maintaining the DC level at a fixed price. Applicable.

[0052]

As described above, according to the present invention, the differential output between the DC level of the output signal output from the main amplifier section and the reference DC level is connected to the common emitter of the preamplifier section and a predetermined current source. By feeding back to the middle point to control the amount of current to the current source and clamping the input bias voltage of the preamplifier to a predetermined value, the DC level can be matched with the reference DC level without temperature characteristics. Even when the reference DC level is varied, it is possible to effectively avoid the possibility that the gain at which the input clamp is deviated fluctuates.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a first embodiment of a DC level shift circuit according to the present invention.

FIG. 2 is an equivalent circuit diagram showing a second embodiment of the DC level shift circuit according to the present invention.

FIG. 3 is an equivalent circuit diagram showing another embodiment.

FIG. 4 is an equivalent circuit diagram showing a conventional DC level shift circuit.

[Explanation of symbols]

1, 10, 20, 30 ... video amplification circuit, 2 ... CR
T, 3, 5, 6, 7 , 21 ... an amplifier, 4 ... a contrast adjustment circuit , 11 ... an attenuator .

Claims (3)

(57) [Claims] A pair of bases cascaded together.
It consists of a grounded differential pair, and the common emitter of each differential pair
Amplifies the input signal and a pre <br/> amplifier unit for collector output which is input to a main amplifier section for power-amplifying the amplified the input signal by the preamplifier, an output which is output from the main amplifier section The DC level of the signal and the reference DC level are input to a differential output terminal, and the differential output is supplied to the common emitter of the preamplifier section at a predetermined voltage.
The so as to fed back to the connection point between current sources
By controlling the amount of current for the current source, the pre
DC level control means for controlling the DC level of the output signal to be constant by clamping the input bias voltage of the amplifier section to a predetermined value, and always keeping the output potential of the preamplifier section constant with respect to the reference DC level, A DC level shift circuit, comprising: a power supply voltage setting unit for fixing an output dynamic range of a preamplifier unit to a constant value. 2. A pair of bases cascaded together.
It consists of a grounded differential pair, and the common emitter of each differential pair
Amplifies the input signal and a pre <br/> amplifier unit for collector output which is input to a main amplifier section for power-amplifying the amplified the input signal by the preamplifier, an output which is output from the main amplifier section The DC level of the signal and the reference DC level are input to a differential output terminal, and the differential output is cascaded to the output stage of the preamplifier unit and the output stage.
Connection with the emitter of the first transistor which is connected to the gate
The first transformer is fed back to the middle point.
DC level control means for controlling the DC level of the output signal to be constant by controlling the collector current of the transistor; and a common emitter and a current for each of the differential pairs of the preamplifier section.
The grounded second and third transistors are connected to the source.
Connected to the emitters of the second and third transistors
A DC level shift circuit comprising: a clamp means for controlling input potentials of the preamplifier section to be constant by controlling the potentials to be equal to each other, and for controlling a gain of the preamplifier section to be constant. 3. A pair of bases cascaded together.
It consists of a grounded differential pair, and the common emitter of each differential pair
Amplifies the input signal and a pre <br/> amplifier unit for collector output which is input to a main amplifier section for power-amplifying the amplified the input signal by the preamplifier, an output which is output from the main amplifier section The DC level of the signal and the reference DC level are input to a differential input terminal, and the differential output is cascaded to the output stage of the preamplifier unit and the output stage.
Connection with the emitter of the first transistor which is connected to the gate
The first transformer is fed back to the middle point.
DC level control means for controlling the DC level of the output signal to be constant by controlling the collector current of the transistor; and a common emitter and a current for each of the differential pairs of the preamplifier section.
The grounded second and third transistors are connected to the source.
Connected to the emitters of the second and third transistors
Clamping means for controlling the input bias voltage of the preamplifier unit to be constant and controlling the gain of the preamplifier unit to be constant by controlling the potentials to be equal to each other, and setting the output potential of the preamplifier unit to the reference DC level. A power supply voltage setting means for setting the output dynamic range of the preamplifier unit to a constant potential at all times.