JP3279380B2 - Camera communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera communication system, and more particularly to a camera communication system in which communication between a camera CPU and an interface is improved.

[0002]

2. Description of the Related Art In recent years, various electronic circuit components have been used in cameras used by users. Among them, communication between the camera CPU and the interface circuit is, for example, 8-BIT SERIAL-IN / PAR.
ALLEL-OUT SHIFTREGISTER
(ΜPD74HC1164), 4-BIT UNIV
ERSAL SHIFT REGISTER (μPD
74HC195) or the like. And, by using these CMOS integrated circuits, the CPU
The interface and the interface circuit control and transmit various addresses / data.

[0003]

However, the above μ
Since the CMOS integrated circuit of the PD74HC1164 performs data processing by serial communication, a time lag called serial communication delay occurs during data transmission. Therefore, it is not suitable for control requiring high speed.

Further, the CMO of μPD74HC195 is
Since the S integrated circuit is a 4-bit input 4-bit output parallel communication, high-speed data transmission and control are ensured. However, there is a problem that many circuits cannot be controlled because of having only a 4-bit output.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to control a large number of circuit sources with a small number of communication lines, and to improve a communication time lag to perform high-speed data transmission and control by a camera. The purpose is to provide a system.

[0006]

That is, the present invention relates to a digital control circuit for outputting a digital control signal through a plurality of signal lines, and a digital camera which receives the digital control signal transmitted through the signal line and provides a plurality of cameras. A camera communication system including an interface circuit for transmitting a signal to any of the control means, wherein the interface circuit includes a register designated based on an address signal transmitted through the signal line; Latching the digital control signal transmitted via the signal line in synchronization with a latch signal, and transmitting a signal based on the latched digital control signal to a control means of a camera connected to the register; The digital control signal via the specified register and the camera connected to the register. The control means, and a second communication mode in which it transmits asynchronously with the latch signal,
A switching means for switching between the first communication mode and the second communication mode is provided.

[0007]

In the camera communication system of the present invention,
A digital control signal is output from the digital control circuit through a plurality of signal lines. Then, the digital control signal transmitted via the signal line is received by the interface circuit, and the signal is transmitted to any of the control units of the plurality of cameras. The interface circuit latches the digital control signal transmitted via the signal line in a register designated based on an address signal transmitted via the signal line in synchronization with a latch signal. A first communication mode for transmitting a signal based on the digital control signal to the control means of the camera connected to the register, and controlling the camera connected to the register via the specified register. The means has a second communication mode for transmitting the signal as it is asynchronously with the latch signal. Then, the communication mode is switched by the switching means.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an electric circuit of a camera communication system according to the present invention. In the figure, C
The PU 10 sequentially executes programs stored in its internal ROM and controls peripheral ICs and the like. The CPU 10 includes an AFIC 11 and an EEPROM.
12, a liquid crystal display panel 13, a data bag 14, a strobe unit 15, an interface IC 16, motor driver ICs 22 and 23, and various switches to be described later.

The AFIC 11 is an auto-focusing IC, and in the camera of the embodiment, AF uses a TTL phase difference detection method. The subject light passes through a photographing lens 17, an AF optical system 20 including a condenser lens 18, separator lenses 19 L and 19 R, an AFIC 1
Photo sensor arrays 21L and 21R arranged on one upper surface
Reached on. Then, processing such as light intensity integration and quantization is performed inside the AFIC 11. This distance measurement information is transferred from the AFIC 11 to the CPU 10.

If the characteristics of each element of the photosensor array vary, accurate distance measurement information cannot be obtained as it is. Therefore, the variation information of the photo sensor array is stored in advance in the EEPROM 12 which is a nonvolatile storage element, and the CPU 10 performs the correction calculation of the distance measurement information obtained from the AFIC 11. In addition, the EEPROM 12 stores various adjustment values such as mechanical variations and variations in electrical characteristics of various elements. These adjustments may be adjusted as necessary
It is sent to the PU 10 and various operations are performed. CPU1
The transfer of data among the 0, AFIC 11, and EEPROM 12 is performed by serial communication.

The liquid crystal display panel 13 displays the number of film frames, a photographing mode, a strobe mode, an aperture value, a remaining battery level, and the like according to a signal sent from the CPU 10. Further, the data bag 14 is controlled by a control signal from the CPU 10.
This is for imprinting the date on the film.
The light quantity of the imprinting lamp changes stepwise according to the ISO sensitivity of the film. Further, the strobe unit 15
During shooting or AF ranging, when the luminance of the subject is insufficient, the light emitting tube is caused to emit light to give the required luminance to the subject.
It is controlled by C16.

The above interface IC (hereinafter referred to as IFIC)
16) performs 4-bit parallel communication with the CPU 10 to measure the subject brightness, measure the temperature in the camera,
Waveform shaping or the output signal such as a photo interrupter, constant voltage drive control of the motor, the generation of various constant voltage such as the voltage of the temperature stability and temperature-proportional, remaining battery capacity check, the reception of the infrared light remote control, the motor driver IC 22, The control of the LED 23, the control of various light emitting diodes (LEDs) 24, the check of a power supply voltage, the control of a booster circuit, and the like are performed.

To check the remaining amount of the battery, a low resistance is connected to both ends of the battery, the voltage at both ends of the battery when a current flows is divided in the IFIC 16 and output to the CPU 10, and the CPU 10 performs A / D conversion. Perform the conversion and get the value to check.

A dedicated terminal is provided for the IFIC 16 for monitoring the low voltage of the power supply voltage. When the power supply voltage input here falls below a specified value, a reset signal is output from the IFIC 16 to the CPU 10. Thereby, the CPU 10
Runaway is prevented beforehand. The control of the booster circuit operates the booster circuit when the power supply voltage falls below a predetermined value.

The IFIC 16 has a two-part silicon photodiode (SPD) 2 for photometry of the subject luminance.
5 is connected. The light receiving surface of the SPD 25 is divided into two parts, such as a central part of the screen and a peripheral part thereof. There are two types, a spot metering that measures light only at a part of the center of the screen, and an average metering that measures light using the entire screen.
Street photometry can be performed. From the SPD 25, the current corresponding to the subject brightness
16 is output. In the IFIC 16, the SPD
The output from 25 is converted to a voltage and transferred to CPU 10.

The CPU 10 performs exposure calculation, backlight determination, and the like based on the converted voltage information. The measured value of the temperature in the camera is obtained by a circuit built in IFIC16.
A voltage proportional to the absolute temperature is output, and the signal is
It is obtained by performing A / D conversion at 10. The obtained temperature measurement value is used for correction of a mechanical member whose state changes depending on the temperature, an electric signal, and the like.

The IFIC 16 is also connected to a silicon photodiode 26 for receiving light. The silicon photodiode 26 is for receiving infrared light remote control, and the light emitting LE of the remote control transmission unit 27 is used.
The infrared light modulated and emitted from D28 is received. The output of the silicon photodiode 26 is IFIC1
Processing such as waveform shaping is performed inside 6 and transferred to the CPU 10.

Further, the AF distance measurement is completed in the IFIC 16,
An LED for display in a viewfinder for strobe light emission warning or the like or an LED used for a photo interrupter or the like is connected. The on / off of these LEDs and the control of the amount of emitted light are controlled by the CPU 10, the EEPROM 12, the IFIC
The communication between the ICs 16 is performed by the IFIC 16 directly. Also,
Various motors are connected to the IFI via the motor driver IC22.
Constant voltage control is performed by C16.

The motor driver IC 22 supplies a shutter charge (S) for feeding the film and charging the shutter.
C) Driving three motors, a motor 29, a lens driving (LD) motor 30 for focus adjustment, a ZM motor 31 for zooming the lens frame, driving a booster circuit, driving a self-timer operation display LED, and the like. I do. Then, these operation controls, for example, which device is to be driven, whether the motor is rotating normally or reversely, and whether to apply braking, are determined by the CPU.
10 signal is received by the IFIC 16 and the IFIC 16
Is performed by controlling the motor driver IC 22.

Whether the SC motor 29 is in the shutter charge, film winding or film rewinding state
It is detected by a shutter charge photo interrupter (SCPI) 32 using a photo interrupter and a clutch lever, and the information is output to the CPU 10.

The extension amount of the photographing lens 17 is as follows.
It is detected by a lens driving photointerrupter (LDPI) 33 attached to the LD motor 30. The output is subjected to waveform shaping by the IFIC 16 and then output to the CPU.
Sent to 10.

The extension amount of zooming of the lens frame is ZMPI.
(Photo interrupter for zooming) 34 and ZMPR
(Zooming photo reflector) 35. When the lens frame is between the telephoto end and the wide end, the ZMPR 35 is configured to detect the reflection of a silver seal (not shown) attached to the lens frame. The output of ZMPR35 is C
It is input to the PU 10 and the tele end and the wide end are detected. On the other hand, the ZMPI 34 is attached to the ZM motor 31, and its output is
It is input to U10, and the zooming amount from the telephoto end or the wide end is detected.

The motor driver IC 23 is a stepping motor for driving the aperture adjustment unit, and drives the AV motor 36 according to a control signal from the CPU 10. Also,
The output of the AVPI 37 is input to the CPU 10 after waveform shaping by the IFIC 16, and the aperture open position is detected.

The waveform shaping of the photo interrupter and the like is as follows.
The output photocurrent of a photo interrupter or a photoreflector is compared with a reference current,
16 is output. At this time, noise is removed by giving the reference current a hysteresis. Further, the IFIC 16 can change the reference current and the hysteresis characteristics by communicating with the CPU 10.
Various switches coupled to the CPU 10 are provided to perform the following operations.

The first release switch R 1 SW is
It is turned on when the release button is half-pressed, and performs a distance measurement operation. Also, the second release switch R2S
W is turned on when the release button is fully depressed, and performs a shooting operation based on various measured values.

The zoom-up switch ZUSW and the zoom-down switch ZDSW are switches for zooming the lens frame. When the zoom up switch ZUSW is turned on, the camera moves in the long focal direction, and the zoom down switch ZDSW
Zooms in the short focus direction when is turned on.

When the self-switch SELESW is turned on, the camera enters a self-timer photographing mode or a standby state of the remote controller. In this state, if the second release switch R2SW is turned on, self-timer shooting is performed,
When a photographing operation is performed by the remote control transmitting unit 27, photographing is performed by the remote control.

When the spot switch SPOTSW is turned on, a spot metering mode is set in which photometry is performed only at a part of the center of the photographing screen (this is metering by the AF sensor). In the case of normal photometry with the spot switch SPOTSW turned off, evaluation photometry is performed at the photometric spot 25.

Picture switches PCT1SW to PCT4
The SW and the program switch PSW are switches for switching a program photographing mode, and the photographer selects a mode according to photographing conditions.

When the picture switch PCT 1 SW is turned on, a portrait mode is set, and the aperture and shutter speed are determined so that the depth of field becomes shallow within an appropriate exposure range. When the picture switch PCT2SW is turned on, the night view mode is set, and the exposure is set one step lower than the value of the appropriate exposure during normal shooting. Picture switch PCT3S
When W is turned on, a landscape mode is set, and the values of the aperture and the shutter speed are determined so that the depth of field becomes as deep as possible within the appropriate exposure range. Picture switch PCT4S
When W is turned on, a macro mode is set. This mode is
Used during close-up photography. Picture switch PC
Two or more T1SW to PCT4SW cannot be selected at the same time.

The program switch PSW is a switch for a normal program photographing mode. By pressing this program switch PSW, the picture switch P
Reset of CTSW1 to PCT4SW, and A
The reset of the V priority program mode is performed.

When the AV priority switch AVSW is turned on,
The shooting mode becomes the AV priority program mode. In this mode, the AV value is determined by the photographer, and the shutter speed is determined by a program according to the AV value. In this mode, picture switches PCT2SW and PCT2
The T4SW does not have the above-described function, and serves as an AV value setting switch. That is, the picture switch PCT2S
W is a switch for increasing the AV value, and picture switch PCT4SW is a switch for decreasing the AV value.

The strobe switch STSW is a switch for switching the light emission mode of the strobe. That is, the normal automatic light emission mode (AUTO) and the red-eye reduction automatic light emission mode (A
A switch for switching between UTO-S), forced emission mode (FILL-IN), and strobe off mode.

The panorama switch PANSW is a switch for detecting whether the photographing state is panoramic photographing or normal photographing, and is turned on during panoramic photographing. When the photographing mode is panoramic photographing, a photometric correction calculation or the like is performed.
This is because the upper and lower portions of the photographing screen are masked during panoramic photographing, and a part of the photometric sensor is also masked accordingly, so that accurate photometry cannot be performed.

The back cover switch BKSW is a switch for detecting the state of the back cover of the camera, and is turned off when the back cover is closed. When the back cover switch BKSW changes from on to off, it means that film loading has started.

The power switch PWSW is a switch for turning on / off the power, and the shutter charge switch SCSW is a switch for detecting shutter charge. Mirror up switch MUSW
Is a switch for detecting mirror up, and is turned on when the mirror is up. Furthermore, DX switch DXSW
Is a switch for reading the DX code indicating the film sensitivity printed on the film cartridge and for detecting the presence or absence of the film loaded. The switch is composed of five switch groups (not shown). FIG. 2 shows a digital circuit block of the interface IC 16. In the figure, the communication input terminal of the input interface 100 represented by the equations (1) to (6) is C
Controlled by the PU 10.

[0038]

(Equation 1)

[0039]

(Equation 2)

[0040]

(Equation 3)

[0041]

(Equation 4)

[0042]

(Equation 5)

[0043]

(Equation 6)

The communication data of the above equations (1) to (4) is
Address latch 102 from input interface 100
Alternatively, the latch group 104 (A0 to A3, B0 to B3, C0
To C3). The input terminal of equation (5) is D0
D3 is an input terminal for a signal for designating whether data input to .about.D3 is set in the address latch 102 or the latch group 104. That is, when the input signal of the terminal of the equation (5) is "L (low level)", the operation is switched to the address latch 102, and when the input signal is "H (high level)", the operation is switched to the latch group 104. The input terminal of the expression (6) receives a signal for giving a timing for setting data to the address latch 102 or the latch group 104 (hereinafter, this signal is referred to as a latch signal).

The selector 101 outputs the timing signal of the input terminal of equation (6) to the address latch 102 or the address decoder 10 according to the input state of the terminal of equation (5).
3 to be selectively given. The address decode 103 receives the latch group 1 from any one of the signal lines CK0 to CK2 designated by the address latch 102.
04, the latch signal of the input terminal of the above-mentioned equation (6) is given.

The signal line CK0 is a 4-bit latch A
0 to A3, the signal line CK1 sends a latch signal to B0 to B3, and the signal line CK2 sends a latch signal to C0 to C3. The latch group 104 stores signals on BUS0 to BUS3 from the input interface 100. The outputs A0O to A3O, B0 of the latch group 104
O to B3O and C0O to C3O control a subsequent analog circuit. FIG. 3 is an equivalent circuit diagram of the above-described selector 101, address latch 102, and address decode 103.

As shown in FIG.
It is composed of two AND gates 111 and 112 which have the terminal output of the equation and the output LA as inputs. Of these, the terminal output of the equation (5) is input to the input side of the AND gate 112 via the inverter 113. Then, the output of the AND gate 111 is set to the address latch 102 as LA, and the output of the AND gate 112 is set to L.
D is supplied to the address decode 103.

The address latch 102 stores BUS0 and B
It comprises D-type latches 121 and 122 which output US1 as a D input, output LA from the above selector as a CK input and Q output to an address decoder 103.

The address decode 103 comprises D-type latches 121 and 122 via inverters 131 and 132.
And the AND gates 133, 134, and 135 to which the output LD of the AND gate 112 is input. And these AND gates 133, 13
4 and 135 are output as CK0, CK1, and CK2.
The data is supplied to the latch group 104. FIG. 4 shows an equivalent circuit of a D-type latch used in the address latch 102 and the latch group 104.

This D-type latch comprises inverters 141 and 142 and NAND gates 143, 144, 145 and 14
6. That is, the D input is connected to one input terminal of the NAND gate 143 via the inverter 141,
Then, the CK input is supplied to the NAND gate via the inverter 142.
The other input terminal of the gate 143 and one input terminal of the NAND gate 144 are input. The output of the NAND gate 143 is
The other input terminal of the NAND gate 143 and the NAND gate 1
45 is supplied to one input terminal. NAND Gate 146
The output of the inverter 142 is supplied to one input terminal, the output of the NAND gate 145 is supplied to the other input terminal, and the output is supplied to the other input terminal of the NAND gate 145.
The outputs of the NAND gates 145 and 146 are the output of equation (7) and the Q output, respectively.

[0051]

(Equation 7)

FIG. 5 is a truth table of the D-type latch. When CK = “H”, the previous state is stored, and CK =
When "L", Q = D and the state of equation (8) is established. That is, when CK = “L”, the D input signal is passed to the output Q or the output of equation (7).

[0053]

(Equation 8) FIG. 6 shows a time chart of each transmission mode.

FIG. 6A shows the address transmission mode, in which the address latch 102 stores 2-bit data "10".
Is set. FIG. 6B shows a data transmission mode in which 4-bit data “0101” is set in a 4-bit latch specified by the address latch 102.

FIG. 6C shows a data through mode. This is because when the value of equation (6) is in the “L” state, D0 to D0
The input state of D3 passes through for the 4-bit latch specified by the address latch 102. In this case, “0000” is shown in FIG.
1 "passes through.

FIG. 7 is a block diagram showing an analog circuit. Generally, in order to reduce the current consumption of the interface IC 16, only the circuit block used at that time is brought into the operating state.

A00 to A30 control the LDM (lens driving motor) 30 and are performed via the motor bridge interface 201. Also, B0O to B3
O is used to turn on / off the measurement circuit block 202, the remote control reception circuit block 203, the LED control block 204, and the PI (photo interrupter) control block 205.

The lens driving motor (LDM) 30
It is necessary to stop the photographing lens 17 with high accuracy at the target focus position, and fine control is required. Therefore, when a speed such as on / off of a circuit is required such as lens driving, real-time control can be performed using the data through mode shown in FIG. 6C. On the other hand, the data transmission mode of FIG. 6B is used for a circuit block that does not require a speed such as ON / OFF of the circuit. Note that this block diagram is only a small part of the interface IC 16 and, of course, actually controls more circuit blocks.

By configuring the interface IC in this manner, many circuit sources can be controlled by the N-bit communication port, and control requiring high speed can be performed without causing communication delay. It is possible to do.

[0060]

As described above, according to the present invention, a camera communication system capable of controlling many circuit sources with a small number of communication lines, improving communication time lag, and performing high-speed data transmission and control. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electric circuit of a communication system for a camera according to the present invention.

FIG. 2 is a diagram showing a digital circuit block of the interface IC 16 of FIG.

FIG. 3 shows a selector 101 and an address latch 102 shown in FIG.
And an equivalent circuit diagram of the address decode 103.

FIG. 4 is a diagram showing an address latch 102 and a latch group 104 shown in FIG. 2;
FIG. 4 is an equivalent circuit diagram of a D-type latch used in FIG.

FIG. 5 is a truth table of a D-type latch.

FIG. 6 shows a time chart of each transmission mode.
(A) is an address transmission mode, (b) is a data transmission mode, and (c) is a data through mode.

FIG. 7 is a block diagram of an analog circuit of the interface IC 16 of FIG. 1;

[Explanation of symbols]

10 CPU, 11 AFIC, 12 EEPROM,
13 liquid crystal display panel, 14 data bag, 15 strobe unit, 16 interface IC, 17
Shooting lens, 18 ... condenser lens, 19L, 19R
... Separator lens, 20 ... AF optical system, 21L, 21
R: Photosensor array, 22, 23: Motor driver IC, 24: Light emitting diode (LED), 25: Photometric silicon photodiode (SPD), 26: Light receiving silicon photodiode, 27: Remote control transmission unit, 28 ... Projection LED, 29 ... Shutter charge (S
C) Motor, 30 ... Lens driving (LD) motor, 31
... Zooming (ZM) motor, 32 ... Shutter charge photo interrupter (SCPI), 33 ... Lens driving photo interrupter (LDPI), 34 ... Zooming photo interrupter (ZMPI), 35 ... Zooming photo reflector (ZMPR), 36 ... AV Motor, 37
... AVPI.

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G03B 7/00

Claims (1)

(57) [Claims] A digital control circuit for outputting a digital control signal through a plurality of signal lines; receiving the digital control signal transmitted through the signal line, and transmitting the signal to any one of a plurality of camera control means. In the camera communication system having an interface circuit for transmitting the signal, the interface circuit transmits the signal via the signal line to a register designated based on the address signal transmitted via the signal line. A first communication mode in which the digital control signal is latched in synchronization with a latch signal, and a signal based on the latched digital control signal is transmitted to control means of a camera connected to the register; The digital control signal is transmitted through a register to the control means of the camera connected to the register, and the latch signal and Camera communication system, characterized by a second communication mode in which it transmits asynchronously, comprising a switching means for switching the first communication mode and the second communication mode.