JP3279276B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a trench wiring using a low dielectric constant film as an interlayer insulating film.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, fine multilayer wiring is indispensable for the configuration of semiconductor devices. In addition, as the operation of the semiconductor device is reduced in voltage and speed, it is necessary to lower the dielectric constant of the interlayer insulating film. In particular, in a logic-based semiconductor device, a rise in resistance and an increase in capacitance between wires due to fine wiring lead to a deterioration in the operation speed of the semiconductor device. Becomes required.

[0003] Miniaturization of the wiring width and the reduction of the wiring pitch not only increase the aspect ratio of the wiring itself, but also increase the aspect ratio of the wiring itself.
The aspect ratio of the space between the wirings is also increased, and as a result, a burden is imposed on the technology of forming fine and narrow wiring in the vertical direction and the technology of embedding the space between the fine wirings with an interlayer insulating film. And increase the number of processes at the same time.

Therefore, a trench wiring technique in which a wiring groove is formed in an interlayer insulating film and a wiring material is buried in the wiring groove by using a chemical mechanical polishing (CMP) method has attracted attention. However, in this technology, when an organic low dielectric constant is applied to the interlayer insulating film, the interlayer insulating film is polished and removed in the step of polishing the wiring material by the CMP method, or the surface of the interlayer insulating film is scratched. Occurs.

Therefore, as a simple method for solving such a problem, there is a technique described in Japanese Patent Application Laid-Open No. H10-112503.

The outline of the technology described in the above publication will be briefly described below. 7 and 8 are cross-sectional views in the order of manufacturing steps of a wiring structure for explaining this conventional technique.

As shown in FIG. 7A, an interlayer silicon oxide film 102 is formed on a silicon substrate 101 on which elements (not shown) are formed in advance. The silicon oxide film 102 for the interlayer is formed by a plasma enhanced chemical vapor deposition (plasma CVD) method.

Next, an organic low dielectric constant film 10 made of, for example, polytetrafluoroethylene is formed on the silicon oxide film 102.
3 is formed. Then, as shown in FIG. 7B, a silicon oxide film 104 is formed on the organic low dielectric constant film 103. When forming the silicon oxide film 104, the plasma C
The VD method is used.

Next, as shown in FIG. 7C, a resist pattern 105 for forming a wiring pattern is formed on the silicon oxide film 104 by a photolithography technique.

Next, for example, using a general magnetron type dry etching apparatus, the resist pattern 105 is used.
Is used as a mask to etch silicon oxide film 104. After that, the resist pattern 105 is removed. As a result, as shown in FIG. 7D, an opening 106 having the shape of the wiring pattern is formed.

Alternatively, for example, using a general magnetron type dry etching apparatus, the resist pattern 1
05 as a mask, the opening 106 of the silicon oxide film 104
Is selectively etched. Then, the resist pattern 105 is removed.

Here, the resist pattern 105 is removed by plasma etching using oxygen gas, that is, by a well-known plasma ashing method.

Through the steps described above, a wiring groove 107 having the same shape as the opening 106 of the silicon oxide film 104 is formed as shown in FIG.

Next, as shown in FIG. 8B, an Al alloy film 10 such as an Al—Cu alloy film is formed on the entire surface of the substrate by using a general sputtering apparatus for forming a metal film.
8 is formed as a wiring material. In this case, the substrate temperature at the time of this film formation is set close to the melting point of the Al alloy,
By performing reflow at a temperature near the melting point of the alloy, the wiring groove 107 is completely filled with the Al alloy film 108.

Next, using an ordinary CMP apparatus, the Al alloy film 108 is polished by a CMP method using the silicon oxide film 104 as a polishing stopper layer.
Unnecessary portions on the silicon oxide film 104 of 08 are removed. At this time, the silicon oxide film 1 having a very high hardness is used.
Since 04 is used as a polishing stopper layer, scratches and the like which occur when the organic low dielectric constant film 103 having extremely low hardness as compared with the silicon oxide film 104 or the like are polished by the direct CMP method are not generated. Can be prevented.

As described above, as shown in FIG. 8C, the interlayer silicon oxide film 1 on the silicon substrate 101 is formed.
02 of the organic low dielectric constant film 103 provided on
7 are formed by embedding groove wirings 109.

[0017]

However, in the conventional technique as described above, the silicon oxide film 104 used as a polishing stopper layer for the organic low dielectric constant film 103 is used.
An opening 106 is provided in a predetermined region by photolithography and dry etching. Then, the resist pattern 105 used as the opening forming mask
Is removed by a plasma ashing method, a resist stripping process in a stripping solution, or the like.

However, when the resist pattern is removed, the organic low dielectric constant film 10 exposed through the opening 106 is removed.
3 is exposed to oxygen plasma. Generally, an organic insulating film is etched when exposed to oxygen plasma. Here, the etching of the organic insulating film by oxygen plasma proceeds isotropically. For this reason, in the related art, the cross-sectional shape of the wiring groove is deteriorated. That is, large side etching occurs in the wiring groove due to the above isotropic etching.

The side etching of the wiring groove is as follows.
This makes it difficult to form fine trench wiring. Particularly, as the aspect ratio of the wiring itself increases with the miniaturization of the wiring width and the wiring pitch, and the aspect ratio of the space between the wirings increases, an organic low dielectric constant film is used as an interlayer insulating film. Further, it becomes impossible to form a trench wiring utilizing the CMP method.

Alternatively, it is not possible to form a trench wiring using an organic low dielectric constant film as an interlayer insulating film, and there is a limit in reducing the dielectric constant of the interlayer insulating film.

The main object of the present invention is to form a trench wiring when an organic low dielectric constant film is used as an interlayer insulating film.
An object of the present invention is to provide a method for forming a fine wiring, which makes it easy to apply the MP technology. Another object of the present invention is to make it possible to reduce the parasitic capacitance between trench wirings by a simple method. Still another object of the present invention is to provide a simple manufacturing method for preventing oxidation of a copper surface in forming a multi-layer trench wiring using copper as a wiring material.

[0022]

For this purpose, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an organic insulating film on a semiconductor substrate, and laminating two or more kinds of organic insulating films on the organic insulating film. Forming an opening in the mask layer and forming a wiring groove in the organic insulating film by dry etching using the mask layer as an etching mask. Including.

[0023] Then, after forming the trench interconnection, depositing a conductor film so as to fill the wiring groove, required of the conductive layer using the mask layer as a polishing protective film of the insulating film of the organic Removing the portion by chemical mechanical polishing and forming a groove wiring so as to be embedded in the wiring groove.

Here, the first mask layer and the second mask layer are laminated in this order to form the mask layer, and a predetermined pattern of the resist mask formed on the second mask layer is formed by the second mask layer. The resist mask is removed after the etching transfer to the second layer.
The opening is formed by etching the first mask layer using the mask layer as an etching mask.

Further , after the formation of the trench wiring, the mask layer is removed, and the relative dielectric constant of the silicon oxide film is reduced over the entire surface .
A small low dielectric constant insulating film is formed.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after forming a trench wiring below a multilayer wiring, a first wiring is formed on the entire surface.
Forming a through-hole mask layer in which a first mask layer and a second mask layer are laminated in this order on the first organic insulating film; and forming a through-hole in the second mask layer. A second organic insulating film is formed on the entire surface, and a wiring groove mask layer composed of two or more kinds of laminated inorganic insulating films is formed on the second organic insulating film. Forming an opening in the wiring groove mask layer; and forming a wiring groove in the second organic insulating film by dry etching using the wiring groove mask layer as an etching mask.

Then , after the formation of the wiring groove, the step of etching and transferring the opening for the through hole formed in the second mask layer to the first mask layer, and the step of forming the wiring of the lower layer through the opening for the through hole. Forming a through hole reaching the first organic insulating film.

Alternatively, the dielectric constant between the lower trench wiring and the first organic insulating film is smaller than that of the silicon oxide film.
An inorganic low dielectric constant insulating film is formed, and through holes are also formed in the inorganic low dielectric constant insulating film.

After the formation of the through hole, a step of depositing a conductive film so as to fill the wiring groove and the through hole, and the step of forming the wiring groove mask layer on the polishing protective film of the second organic insulating film. Removing unnecessary portions of the conductor film by chemical mechanical polishing, and forming an upper layer groove wiring so as to be embedded in the wiring grooves and the through holes.

Here, the conductive film is made of copper, and the first mask layer and the second mask layer are made of a silicon oxide film and a silicon nitride film, respectively.
The first organic insulating film and the second organic insulating film, full Tsu fluorinated amorphous carbon, and a benzylidene black butene or organic polysilazane.

As described above, according to the present invention, in forming a trench wiring, a mask composed of two or more kinds of inorganic insulating films laminated on a predetermined region of an interlayer insulating film composed of an organic low dielectric constant film. Form a layer. This mask layer is formed by the conductive film C
In the MP process, the organic low dielectric constant film is protected from polishing.
In addition, the lower layer of the two or more inorganic insulating films protects the organic low dielectric constant film from plasma ashing.

Therefore, it becomes easy to form a wiring groove having extremely high dimensional accuracy in the organic low dielectric constant film by forming the groove wiring. Then, the formation of the multilayer wiring structure by the fine groove wiring becomes easy. Further, in forming a trench wiring using copper as a wiring material, oxidation of the copper surface is completely prevented.

[0033]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views illustrating a trench wiring in a manufacturing process order according to a first embodiment of the present invention.

As shown in FIG. 1, a silicon oxide film 2 having a thickness of about 500 nm is formed on a silicon substrate 1 as described in the prior art.

Next, a low dielectric constant insulating film 3, which is an organic insulating film made of, for example, fluorinated amorphous carbon, is formed on the silicon oxide film 2. Here, the thickness of the low dielectric constant insulating film 3 is set to about 500 nm. The relative permittivity of the fluorinated amorphous carbon is about 2.4.

Next, as shown in FIG. 1B, a first mask layer 4 and a second mask layer 5 are formed on the low dielectric constant insulating film 3 by lamination. Here, the first mask layer 4 is made of plasma C
The second mask layer 5 is a silicon nitride film having a thickness of about 10 nm formed by a plasma CVD method.

Next, as shown in FIG. 1C, a resist mask 6 for forming a wiring pattern is formed on the second mask layer 5 by photolithography. Then, the second mask layer 5 is formed using the resist mask 6 as an etching mask.
Is dry-etched to form a first opening 7. In the dry etching of the second mask layer 5, a mixed gas of CF ₄ and O ₂ is used as a reaction gas, and the first mask layer 4
Is not removed by etching.

Thereafter, the resist mask 6 is removed by a plasma ashing method. The treatment is performed in an organic stripping solution or an acid solution such as sulfuric acid or nitric acid. Thereby, as shown in FIG. 2A, a first opening 7 having a wiring pattern shape is formed in a predetermined region of the second mask layer 5.

In the step of removing the resist mask 6 by the plasma ashing method, the low dielectric constant insulating film 3 is completely covered with the first mask layer 4. For this reason, the low dielectric constant insulating film 3 is completely prevented from being etched in the plasma ashing process as in the prior art.

Next, as shown in FIG. 2B, the first mask layer 4 is used with the second mask layer 5 as a dry etching mask.
Is dry-etched to form a second opening 8. In the dry etching of the first mask layer 4, a mixed gas of C ₄ F ₈ and CH ₂ F ₂ is used as a reaction gas. In such dry etching, the second mask layer 5 or the low dielectric constant insulating film 3 is hardly etched.

Next, as shown in FIG. 2C, using the first mask 4 and the second mask layer 5 as an etching mask, the low dielectric constant insulating film 3 is dry-etched to form a wiring groove 9. Here, dry etching of the low dielectric constant insulating film 3 is performed as follows.
Anisotropic dry etching is performed using a mixed gas of Cl ₂ and O ₂ as a reaction gas. Thus, the wiring groove 9 without side etching is formed.

Next, as shown in FIG. 3A, a barrier layer 10 which is a conductor film is formed on the entire surface of the substrate using a general sputtering apparatus for forming a metal film. Here, the barrier layer 10 is made of titanium nitride or the like having a thickness of about 50 nm. Then, a metal wiring film 11 which is another conductor film is formed so as to cover the barrier layer 10 and completely fill the wiring groove 9. Here, the metal wiring film 11 is made of copper.

Next, as shown in FIG. 3B, the metal wiring film 11 is formed using the second mask layer 5 as a polishing stopper layer.
The barrier layer 10 and the barrier layer 10 are polished by a CMP method, and unnecessary portions of the conductive material on the second mask layer 5 are removed. In this CMP process, the low dielectric constant insulating film 3 is completely protected from the CMP by the second mask layer 5 or the first mask layer 4. In this way, the groove wiring 12 in which the barrier layer and the metal wiring film are embedded is formed in the wiring groove 9 provided in the organic low dielectric constant insulating film 3 such as fluorinated amorphous carbon.

Next, the second mask layer 5 and the first mask layer 4 are sequentially removed by plasma etching. Here, a mixed gas of CHF ₃ and H ₂ is used as a reaction gas for plasma etching, and a gas containing oxygen is not used. Thus, the trench wiring 12 and the low dielectric constant insulating film 3 are prevented from being etched in this step.

Next, as shown in FIG. 3C, a coating insulating film 13 is formed on the entire surface. Here, the coating insulating film 13 is B
An organic coating film having a low dielectric constant and a thickness of about 200 nm, such as CB (benziccyclobutene), is used. The relative dielectric constant of such an organic coating film is 3 or less, which is considerably lower than the value 4 of the silicon oxide film. And plasma C
The interlayer insulating film 14 is formed on the entire surface by forming a silicon oxide film by the VD method.

As described above, as shown in FIG. 3C, the groove wiring 12 is buried in the wiring groove 9 provided in the organic low dielectric constant insulating film 3 on the silicon substrate 1. Form.

According to the method of the present invention, in forming the trench wiring, the application of the CMP technique when the organic low dielectric constant film is used as the interlayer insulating film becomes easy. Further, since the trench wiring is completely covered with the low dielectric constant insulating film, the parasitic capacitance between the trench wirings is greatly reduced. Further, in forming a trench wiring using copper as a wiring material, oxidation of the copper surface is completely prevented.

Next, a second embodiment of the present invention will be described with reference to FIGS. 4 to 6 are cross-sectional views in the order of the manufacturing process for explaining the formation of the multilayer trench wiring. Here, the same components as those in the first embodiment are denoted by the same reference numerals.

As in the first embodiment, FIG.
As shown in FIG. 1A, a groove wiring 12 is formed so as to be buried in a wiring groove 9 provided in an organic low dielectric constant insulating film 3 on a silicon oxide film 2 of a silicon substrate 1. This groove wiring 12
Becomes the lower layer wiring of the multilayer wiring. Then, a protective insulating film 15 is formed on the entire surface. Here, the protective insulating film 15 is an inorganic insulating film. For example, a 200 nm thick HSQ
(Hydrogen silsequiosan) is used. Here, the relative permittivity of HSQ is about 3, which is lower than the value 4 of the silicon oxide film.

Next, an organic low-dielectric-constant insulating film 3a made of fluorinated amorphous carbon and serving as a first organic insulating film is formed on the protective insulating film 15. Here, the thickness of the low dielectric constant insulating film 3a is set to about 300 nm.

Then, similarly to the first embodiment, the first mask layer 4a and the second mask layer 5 are formed on the low dielectric constant insulating film 3a.
a are laminated. Here, the first mask layer 4a is a silicon oxide film having a thickness of about 10 nm, and the second mask layer 5a is a silicon nitride film having a thickness of about 10 nm.

Next, a resist mask 6a for forming a through-hole pattern is formed on the second mask layer 5a by photolithography. Then, the resist mask 6
The second mask layer 5a is dry-etched using a as an etching mask to form a first opening 7a for a through hole.

After that, the resist mask 6a is removed by a plasma ashing method. In the step of removing the resist mask 6a by the plasma ashing method, the low dielectric constant insulating film 3a is completely covered with the first mask layer 4a. Therefore, the etching of the low dielectric constant insulating film 3a in the plasma ashing process is completely prevented.

Next, as shown in FIG. 4B, in order to form an upper trench wiring on the entire surface, an organic low dielectric constant insulating material made of fluorinated amorphous carbon and serving as a second organic insulating film is used. The film 3b is formed. Here, the low dielectric constant insulating film 3b
Is set to about 800 nm.

Then, the first mask layer 4b and the second mask layer 5b are formed on the low dielectric constant insulating film 3b by lamination. Here, the first mask layer 4b is a silicon oxide film having a thickness of about 20 nm, and the second mask layer 5a is a silicon nitride film having a thickness of about 10 nm.

Next, as shown in FIG. 4C, a resist mask 6b for forming a wiring pattern is formed on the second mask layer 5b by photolithography. And
The second mask layer 5b is dry-etched using the resist mask 6b as an etching mask to form a first opening 7b for an upper layer trench wiring. The dry etching of the second mask layer 5b is performed in the same manner as in the first embodiment.

After that, the resist mask 6b is removed by a plasma ashing method. As a result, as shown in FIG. 5A, a first opening 7b having a wiring pattern shape is formed in a predetermined region of the second mask layer 5b.

In the step of removing the resist mask 6 by the plasma ashing method, the low dielectric constant insulating film 3b is formed.
Are completely covered with the first mask layer 4b. Therefore, the low dielectric constant insulating film 3b is completely protected from etching by plasma ashing.

Next, as shown in FIG. 5B, the low dielectric constant insulating film 3b is dry-etched by using the second mask layer 5b and the first mask
a is formed. Here, as described in the first embodiment, the wiring groove 9a without side etching is formed.

Next, as shown in FIG. 5C, the first mask layer 4a is dry-etched using the second mask layers 5a and 5b as an etching mask. Thus, a second opening 8a for a through hole is formed.

Next, as shown in FIG. 6A, the low dielectric constant insulating film 3a is dry-etched using the first mask layer 4a and the second mask layer 5a as an etching mask. Thus, the through hole 16 is formed in the low dielectric constant insulating film 3a. In this step, the protective insulating film 15 is not etched. In the dry etching of the low dielectric constant insulating film 3a, a mixed gas of Cl ₂ and O ₂ is used as a reaction gas,
Anisotropic dry etching is performed.

Next, as shown in FIG. 6B, the protective insulating film 15 is dry-etched using the second mask layer 5a as an etching mask. In the dry etching of the protective insulating film 15, a mixed gas of C ₄ F ₈ and CH ₂ F ₂ is used as a reaction gas. Since such a dry etching does not include an oxygen-based gas, the surface of the lower trench wiring 12 is neither oxidized nor hardly etched.

Next, as shown in FIG. 6C, as described in the first embodiment, a barrier layer and a metal wiring film are formed, and unnecessary portions are removed by polishing by a CMP method. Is formed. In this way, a groove wiring having a two-layer structure, that is, a lower-layer groove wiring 12 and an upper-layer groove wiring 12a connected to each other through the through holes 16 are formed.

In the second embodiment, as in the first embodiment, an organic low-dielectric-constant film is used as the interlayer insulating film, and the formation of the trench wiring using the CMP technique is facilitated.
Further, even when copper is used as a wiring material in forming a multi-layer grooved wiring, oxidation of the copper surface is completely prevented.

In the above embodiment, the case where fluorinated amorphous carbon is used as the organic low dielectric constant insulating film has been described. In addition, as such a low dielectric constant insulating film, an organic polysilazane having a relative dielectric constant of about 2.6, a BCB having a relative dielectric constant of about 2.7, and a relative dielectric constant of 2.
About 6 Parylene F (registered trademark), fluorinated polyimide, plasma CF polymer, plasma CH polymer, and fluorinated polyallyl ether may be used. here,
In the formation of the multilayer trench wiring, different types of low dielectric constant insulating films may be used for different interlayer insulating films.

In the embodiment, the case where the silicon oxide film and the silicon nitride film, which are inorganic insulating films, are described as the mask layers to be laminated is described. However, any other inorganic insulating films having different etching rates may be used. The present invention can be similarly applied to the present invention. For example, a stacked film of a silicon oxide film and a silicon oxynitride film may be used. Alternatively, it should be noted that the insulating films of the first mask layer and the second mask layer may be exchanged.

Here, even with inorganic insulating films other than organic insulating films, inorganic insulating films such as HSQ which have low resistance to etching or the like with respect to a resist stripping solution used in a resist removing step. It should be noted that the method of the present invention as described in the above embodiment can be effectively applied when a trench wiring is formed in a low dielectric constant insulating film.

[0068]

As described above, according to the present invention, in forming a trench wiring using a low dielectric constant film as an interlayer insulating film having no resistance to the step of removing a resist mask, a low dielectric constant is formed on a semiconductor substrate. An insulating film is formed, and a mask layer including two or more stacked inorganic insulating films is formed on the low dielectric constant insulating film. Then, an opening is formed in the mask layer, and a wiring groove is formed in the low dielectric constant insulating film through the opening by dry etching. After forming such a wiring groove, a conductive film is deposited so as to fill the wiring groove, the mask layer is used as a polishing protection film for the low dielectric constant insulating film, and unnecessary portions are removed by a CMP method. A trench wiring is formed so as to be embedded in the trench.

Here, in the step of removing the resist mask, the low dielectric constant insulating film is protected from the resist removing step such as plasma ashing by the lower inorganic insulating film of the two or more kinds of inorganic insulating films to be laminated. I do.

For this reason, in forming the groove wiring, it becomes easy to form a wiring groove having extremely high dimensional accuracy in, for example, an organic low dielectric constant film by forming the groove wiring. Then, the application of the CMP technique when the organic low dielectric constant film is used as the interlayer insulating film is facilitated. Further, it is possible to form a multilayer wiring structure using fine groove wiring.

Further, in forming a trench wiring using copper as a wiring material, oxidation of the copper surface is completely prevented.

As described above, since the trench wiring is completely covered with the low dielectric constant insulating film, the parasitic capacitance between the trench wirings is greatly reduced. Further, it is easy to improve the performance and reliability of the fine multilayer wiring accompanying the miniaturization or multifunctionalization of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention in the order of manufacturing steps of trench wiring.

FIGS. 2A to 2C are cross-sectional views for explaining a first embodiment of the present invention in the order of manufacturing steps of trench wiring.

FIG. 3 is a cross-sectional view for explaining the first embodiment of the present invention in the order of manufacturing steps of the trench wiring.

FIG. 4 is a cross-sectional view for explaining a second embodiment of the present invention in the order of manufacturing steps of trench wiring.

FIG. 5 is a cross-sectional view for explaining a second embodiment of the present invention in the order of manufacturing steps of a trench wiring.

FIG. 6 is a cross-sectional view for explaining the second embodiment of the present invention in the order of the manufacturing process of the trench wiring.

FIG. 7 is a cross-sectional view illustrating a related art in the order of manufacturing steps of trench wiring.

FIG. 8 is a cross-sectional view illustrating a related art in the order of manufacturing steps of trench wiring.

[Explanation of symbols]

 1,101 silicon substrate 2,102,104 silicon oxide film 3,3a, 3b low dielectric constant insulating film 4,4a, 4b first mask layer 5,5a, 5b second mask layer 6,6a, 6b resist mask 7, 7a, 7b First opening 8, 8a Second opening 9, 9a, 107 Wiring groove 10 Barrier layer 11 Metal wiring film 12, 12a, 109 Groove wiring 13 Coating insulating film 14 Interlayer insulating film 15 Protective insulating film 16 Through hole 103 Organic low dielectric constant film 105 Resist pattern 106 Opening 108 Al alloy film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 21/762 H01L 21/88 D (58) Investigation field (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21 / 321 H01L 21/3213 H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/43 H01L 29/47 H01L 29/872

Claims (8)

(57) [Claims] An organic insulating film is formed on a semiconductor substrate.
And laminating two or more types on the organic insulating film.
Forming a mask layer composed of an inorganic insulating film;
Forming an opening in the mask layer and etching the mask layer.
Distributed on the organic insulating film by dry etching
Forming a line groove, and forming the wiring groove after forming the wiring groove.
Depositing a conductor film to fill the groove;
The mask layer is used as a polishing protective film for the organic insulating film.
Unnecessary portions of the conductor film are removed by chemical mechanical polishing, and the wiring
Forming a groove wiring so as to be buried in the groove; and, after forming the groove wiring, removing the mask layer and forming silicon oxide on the entire surface.
Method of manufacturing a semi-conductor device characterized by depositing a than the dielectric constant of small low-dielectric constant insulating film film. 2. A mask layer is formed by laminating a first mask layer and a second mask layer in this order, and a predetermined pattern of a resist mask formed on the second mask layer is formed on the second mask layer. the etched transcription, post the etching transfer, the resist mask is removed, according to claim 1 Symbol, wherein the opening is formed through the etching of the first mask layer in which the second mask layer as an etching mask Manufacturing method of the semiconductor device described above. 3. A method according to claim 1, further comprising the step of forming a groove wiring below the multilayer wiring.
Forming a first organic insulating film on the entire surface;
A first mask layer and a second mask layer were laminated in this order on top
Forming a mask layer for a through hole;
After forming openings for through holes in the mask layer,
And forming two types of organic insulating films on the second organic insulating film.
Wiring groove mask composed of laminated inorganic insulating film as described above
Forming a layer and forming an opening in the wiring groove mask layer
With the wiring groove mask layer serving as an etching mask.
Forming wiring grooves in the second organic insulating film by light etching
A step of, after forming the wiring groove, and etching transferring the opening for through-hole in said first mask layer formed on the second mask layer, the lower layer of the trench wiring through the opening for the through hole Forming a through hole reaching the first organic insulating film.
Method of manufacturing a semi-conductor device that. 4. An inorganic low dielectric constant insulating film having a relative dielectric constant smaller than that of a silicon oxide film is formed between the lower trench wiring and the first organic insulating film. 4. The method according to claim 3 , wherein a through hole is also formed in the film. 5. A step of depositing a conductor film so as to fill the wiring groove and the through hole after the formation of the through hole, and the step of forming the wiring groove mask layer as a polishing protection film for the second organic insulating film. the unnecessary portions of the conductive film is removed by chemical mechanical polishing, according to claim 3 or claim, characterized in that it comprises a step of forming an upper groove wiring so as to be embedded in the wiring grooves and the through holes as 5. The method for manufacturing a semiconductor device according to item 4 . 6. The method of claim 1, wherein the conductive film is made of copper, the method of manufacturing a semiconductor device according to claim 2 or claim 5, wherein. Wherein said first mask layer, the second mask layer, respectively, according to one of claims of claims 6 silicon oxide film, a 請 Motomeko 2 you being a silicon nitride film Of manufacturing a semiconductor device. Wherein said organic insulating film, the first organic insulating film and the second organic insulating film, characterized in that it is constituted by a full Tsu fluorinated amorphous carbon, benzylidene-cyclo-butene or organic polysilazane the method of manufacturing a semiconductor device according to one of claims one of claims 1 to 7.