JP3272784B2 - Insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device used as a power switching element.

[0002]

2. Description of the Related Art In recent years, as a power switching element,
Insulated gate bipolar transistor (Insulated Gate)
Bipolar Transistor (IGBT) is used.
FIG. 10 shows an example of this IGBT.

In the figure, 1 is p⁺ Type Si substrate (emitter layer)
And a low impurity concentration n^- Mold layer (high resistance base
Layer 2 is formed, and this n^- P-type base on the surface of mold layer 2
Layer 3 and n⁺ A mold source layer 4 is formed. Where n
⁺ Type source layer 4 is self-aligned with the end of p-type base layer 3.
Is formed with the channel region 5 left. Cha
On the tunnel region 5, a gate electrode 7 is interposed via a gate insulating film.
Is formed. And, on the source layer 4, a base layer
3 and a source electrode (Caso
C) 8 is formed and p⁺ Drain voltage is applied to the back of the mold substrate 1.
A pole (anode) 9 is formed.

In this structure, n ⁺ N ⁻ from the source layer 4 through the channel region 5. With respect to the electron current injected into the mold layer 2, p ⁺ N from type substrate 1 ^- Hole injection into the mold layer 2 occurs, resulting in n ⁻ Conduction modulation occurs in the mold layer 2 due to accumulation of a large amount of carriers. n ^- The hole current injected into the mold layer 2 passes right below the source layer 4 of the p-type base layer 3 and escapes to the source electrode 8. This structure is similar to a thyristor but does not operate. The source electrode 8 is composed of the p-type base layer 3 and n ⁺ The thyristor operation is prevented by short-circuiting the mold source layer 4, and the element is turned off when the gate-source voltage is reduced to zero.

However, in this type of IGBT, although the injection efficiency of the anode-side emitter can be increased, there is a limit in increasing the efficiency of electron injection on the cathode side for the purpose of preventing the latch-up of the parasitic thyristor. . Therefore, the accumulation of carriers in the high-resistance base layer is smaller than that of the thyristor, and an increase in the on-resistance of the high-resistance base layer, which is the most dominant factor in determining the characteristics of the high breakdown voltage element, cannot be avoided.

[0006]

As described above, in the conventional IGBT having a bipolar transistor as a basic structure, the maximum current interruption capability can be increased, but the on-resistance is larger than that of a GTO thyristor having a thyristor as a basic structure. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an insulated gate having a low on-resistance while maintaining a large maximum current interruption capability and capable of increasing the withstand voltage of an element. To provide a semiconductor device.

[0008]

The gist of the present invention is to provide a thyristor structure or a diode structure having an n-emitter that is not in contact with the cathode electrode between the on-channels on the cathode side of a vertical IGBT, The object is to set the area ratio between the thyristor structure or the diode structure and the IGBT portion in an optimum range.

That is, the present invention (Claim 1) provides a second conductive type high-resistance base layer laminated on a first conductive type emitter layer and a surface portion of the second conductive type high-resistance base layer. The formed first conductive type base layer, the second conductive type source layer formed on the surface of the first conductive type base layer, and the first conductive type base layer on the surface of the high resistance base layer are separated from each other. A second conductive type emitter layer, a first main electrode in contact with the first conductive type emitter layer, a second main electrode in contact with the first conductive type base layer and the second conductive type source layer, In an insulated gate semiconductor device having a gate electrode formed between a second conductivity type source layer and a second conductivity type emitter layer with a gate insulating film interposed therebetween, a lateral unit orthogonal to a thickness direction of each layer is provided. The cell size is 120 μm or less.

Further, the present invention (claim 2) provides a high-resistance base layer of the second conductivity type laminated on the emitter layer of the first conductivity type, and a first resistance layer formed on the surface of the high-resistance base layer. A first conductive type base layer and a second first conductive type base layer formed on the surface of the high-resistance base layer so as to be separated from the first conductive type base layer.
A conductive type base layer; a second conductive type emitter layer formed on a surface of the second first conductive type base layer;
A second conductive type source layer formed on a surface portion of the conductive type base layer, a first main electrode in contact with the first conductive type emitter layer,
A second main electrode that is in contact with the first first conductivity type base layer and the second conductivity type source, and is formed between the second conductivity type source layer and the second conductivity type emitter layer via a gate insulating film. In the insulated gate semiconductor device provided with a gate electrode, the unit cell size in the lateral direction orthogonal to the thickness direction of each layer is 12
The thickness is set to 0 μm or less, preferably 5 μm or more.

Here, as a preferred embodiment of the present invention, the first conductivity type base layer in the IGBT portion is formed in a ring shape on the surface of the high resistance base layer, and the inside of the first conductivity type base layer is formed. A first conductivity type source layer is formed on the surface in a ring shape. Further, the gate electrode is formed inside the ring-shaped source layer of the first conductivity type, and the emitter of the second conductivity type is formed below the gate electrode.

[0012]

According to the present invention, a thyristor or a diode is formed adjacent to a vertical IGBT to reduce the on-resistance of a high-resistance base layer to reduce the on-resistance as a switching element. Can be. Moreover, the IGB formed in series with the thyristor or the diode
By optimizing the size of the thyristor or diode portion (120 μm or less) in consideration of the resistance of the T-on channel, the on-resistance can be made lower than the minimum value obtained by the IGBT alone. Therefore, it is possible to sufficiently reduce the on-resistance while keeping the maximum current interruption capability of the IGBT large.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a schematic configuration of an insulated gate semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA 'of FIG. 11 in the figure is p ⁺ Type S
i-substrate (first conductivity type emitter layer).
N of the low impurity concentration above ^- A mold layer (high resistance base layer) 12 is formed. n ^- A p-type layer (first first conductivity type base layer) 13 is formed in a rectangular ring shape on a surface portion of the mold base layer 12, and n ⁺ is formed on an inner surface of the p-type base layer 13. A mold layer (second conductivity type source layer) 14 is formed in a rectangular ring shape.

Then, on the element surface on which each of the above layers is formed, n ⁺ A gate electrode 17 is formed inside the mold source layer 14 via a gate insulating film 16. Also, n ⁺ A source electrode (cathode electrode; second main electrode) 18 is formed on the p-type base layer 13 at the same time as the p-type base layer 13, and a drain electrode (anode electrode; first main electrode) is formed on the back surface of the substrate 11. An electrode 19 is formed.

The structure up to this point is the same as that of the conventional device. However, in this embodiment, in addition to this, the gate electrode 1 on the surface of the device is additionally provided.
Below p, a p-type layer (second first conductivity type base layer) 21 is formed separately from p-type base layer 13. And
N ⁺ is added inside the surface of the p-type base layer 21. Mold layer (second
A conductive type emitter layer 22 is formed.

With such a structure, the p-type base layer 2
1 and n ⁺ With the provision of the emitter layer 22, the n ⁺ Type emitter layer 22, p
Type base layer 21, n ^- Mold base layer 12 and p ⁺ A thyristor structure including the mold emitter layer 11 is formed, and this thyristor is connected in parallel with the IGBT. Then, the electrons injected from the source electrode 18 of the vertical IGBT pass through the n-type channel immediately below the gate electrode and pass through the n ⁺ channel of the thyristor provided between the on-channel 15 and the on-channel 15 ′. Is supplied to the mold emitter layer 22. And, with this thyristor structure, high resistance n ⁻ The on-resistance of the mold base layer 12 decreases.

Here, it is necessary to sufficiently reduce the area of the thyristor portion in consideration of the on-channel resistance of the IGBT formed in series with the thyristor. FIG.
Shows the on-voltage distribution of the present structural element. V
1 is n ⁺ Voltage drop of the emitter layer 22 and V2 is a high resistance n
^- Voltage of the base layer 12, V3 is p ⁺ The voltage drop of the emitter layer 11 and Vch are n ^{+ of the} vertical IGBT. Thyristor n ⁺ M up to the type emitter layer 22
This is the channel resistance of the OSFET. Since the p-type base layer 21 of the thyristor is separated from the IGBT portion, the device is turned off (when -15 V is applied to the gate electrode 17).
Then, the p-type base layer 21 of the thyristor and the p-type base layer 13 in the IGBT portion are connected by a p-channel to guarantee the element breakdown voltage.

Further, in the on-state of the device, since the p-type base layer 21 of the thyristor is a state close floating or in the external potential of the device, for the thyristor shifts to the ON state, the thyristor n ⁺ It is not necessary to exceed a built-in voltage between the type emitter layer 22 and the p-type base layer 21, n ⁺ The width of the mold emitter layer 22 can be designed to be narrow. For example, if the p-type base layer 21 of the thyristor and the p-type base layer 13 of the IGBT portion are connected when the device is in the ON state, the n-emitter width of the thyristor is increased to exceed this built-in voltage, and the lateral width immediately below the n-emitter is increased. The thyristor does not turn on unless a voltage higher than the built-in voltage is obtained by the resistor.

FIG. 4 shows the same design of the IGBT portion, but is a calculation of the current density flowing through the element when the cell size of the element is changed. Here, the size of the IGBT portion was fixed (Ls = 5 μm), and the current density flowing through the element was calculated by changing the size of the thyristor structure portion. The hole lifetime τp was 10 μs, and the anode-cathode voltage was 2.6 V.

As a result, n ⁺ Without emitter (IG
In the case of BT), the current density increased as the cell size decreased, and the current density decreased when the cell size became too small. Also, n ⁺ With emitter (IGB
T + SCR), the current density increases with decreasing cell size, and always n ⁺ The current density is higher than without an emitter. Further, when the cell size becomes 120 μm or less, n ⁺ It was larger than the maximum current density without an emitter.

FIG. 4 shows the characteristics of the IGBT portion.
Changes slightly depending on the size, thickness of each layer, and other parameters.
However, the relationship between the two curves is almost constant,
Is less than 120 μm,⁺ With emitter
Is always n⁺ Than the maximum current density without the emitter
growing. Therefore, n⁺ Cell with emitter
If the size is 120 μm or less, the size cannot be obtained conventionally
It is possible to obtain a high current density.

As described above, in the case of having the n-emitter structure and the case of not having the n-emitter structure (conventional IGBT), the cell size (n
It is found that it is advantageous to have an emitter width = cell size−IGBT) of 120 μm or less and an n-emitter structure. Therefore, if the cell size is 120 μm or less,
By setting it to μm, it is possible to realize a sufficiently low on-resistance while maintaining the maximum current interrupting ability of the IGBT, and its usefulness is great.

FIG. 5 is a sectional view of an element structure showing a main part of a second embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the p-type base layer 21 in the first embodiment is omitted.

In this case, instead of the thyristor structure, n
⁺ Type emitter layer 22, n ^- Mold base layer 12 and p ⁺ Although a diode structure including the mold emitter layer 11 is formed, the basic operation is the same as that of the first embodiment.
Also in this example, when the width of the IGBT portion was made constant and the width of the diode structure portion was varied to calculate the current density flowing through the element, a result substantially similar to that of FIG. 4 was obtained. That is, when the cell size is 120 μm or less, it is possible to obtain a large current density that cannot be obtained by the conventional IGBT.

FIG. 6 is a sectional view of an element structure showing a main part of a third embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the p-type source layer 21 in the first embodiment is omitted, and n ⁺ P ⁺ The mold layer 23 is selectively provided.

In this case, p ⁺ The portion including the mold layer 23 has a thyristor structure, and operates basically in the same manner as in the first embodiment. In this embodiment, the cell size is 120 μm.
In the following, it is possible to obtain a large current density that cannot be obtained by the conventional IGBT.

FIG. 7 is a sectional view of an element structure showing a main part of a fourth embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the p-type source layer 21 in the first embodiment is omitted, and n ⁺ An n-type layer 24 connected to the p-type source layer 13 is provided below the type emitter layer 22.

In this case, the basic operation is the same as that of the first embodiment.
It is possible to obtain a large current density that cannot be obtained with the GBT. In addition, the provision of the n-type layer 24 has an advantage that the on-resistance can be reduced as compared with the second embodiment.

FIG. 8 is a plan view showing a schematic structure of an insulated gate type semiconductor device according to a fifth embodiment of the present invention, and FIG. 9 is a sectional view taken along lines AA 'and BB' of FIG. . 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the p-type source layer 21 in the first embodiment is replaced by n ⁺ It is formed not only to cover the type emitter layer 22 but also below the p-type source layer 12. Specifically, n ⁺ The emitter layer 22 is formed in a stripe shape that is long in one direction. The p-type source layer 21 is connected to the IGBT portion and the thyristor structure portion in the long side direction of the element, and the p-type source layer 21 is separated in the short side direction. Have been. Here, in FIG. 9B, the p-type source layer 21 is n ⁺ It is formed on a part of the bottom of the type emitter layer 22, n ⁺
It may be formed so as to completely cover the mold emitter layer 22.
However, it does not come into contact with the adjacent p layer.

Even in such a configuration, a thyristor structure is formed adjacent to the IGBT, and the cell size in the short side direction of the element is set to 120 μm or less, which is similar to that of the first embodiment. The effect of is obtained.

The present invention is not limited to the above-described embodiments, but can be implemented in various modifications without departing from the scope of the invention. In the embodiment, the emitter layer on the drain electrode side is p-type, and the source layer on the source electrode side is n-type. However, the present invention is not limited to this, and the conductivity types of all layers may be reversed. Conditions such as the impurity concentration, depth, and size of each layer may be appropriately set according to the specifications.

[0034]

As described above in detail, according to the present invention, an n-emitter not in contact with the cathode electrode is provided between the on-channel of the vertical IGBT on the cathode side,
A thyristor or a diode having a p-base layer electrically connected to the p-base layer of the vertical IGBT via insulation or resistance is provided, and the thyristor (diode) and the IGB are provided.
By setting the area ratio of T to an optimum range, it is possible to realize an insulated gate semiconductor device having a low on-resistance while maintaining a large maximum current interruption capability and capable of increasing the withstand voltage of an element. .

[Brief description of the drawings]

FIG. 1 is a plan view showing an element structure of an insulated gate semiconductor device according to a first embodiment.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is an element structure sectional view showing a part of the element shown in FIG. 2;

FIG. 4 is a characteristic diagram showing a relationship between a cell size and a current density.

FIG. 5 is a sectional view of an element structure showing a main part configuration of a second embodiment.

FIG. 6 is a sectional view of an element structure showing a main part configuration of a third embodiment.

FIG. 7 is an element structure cross-sectional view showing a main part configuration of a fourth embodiment.

FIG. 8 is a plan view showing an element structure of an insulated gate semiconductor device according to a fifth embodiment.

FIG. 9 is a sectional view taken along the lines AA ′ and BB ′ of FIG. 8;

FIG. 10 is a sectional view showing an element structure of a conventional insulated gate semiconductor device.

[Explanation of symbols]

11 ... p ⁺ -Type Si substrate (first conductivity type emitter layer) 12... N ⁻ Type layer (second conductivity type high-resistance base layer) 13 ... p-type layer (first conductivity type base layer) 14 ... n ⁺ Mold layer (second conductivity type source layer) 15 channel region 16 gate insulating film 17 gate electrode 18 source electrode 21 p-type layer (first conductivity type base layer) 22 n ⁺ Mold layer (second conductivity type emitter layer) 23... P ⁺ Mold layer 24 ... n-type layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-27164 (JP, A) JP-A-62-150769 (JP, A) JP-A-60-236265 (JP, A) 273683 (JP, A) JP-A-61-159767 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 29/749

Claims (2)

(57) [Claims] A first conductive type emitter layer laminated on the first conductive type emitter layer;
A conductive high-resistance base layer; a first conductive type base layer formed on the surface of the second conductive type high-resistance base layer; and a second conductive layer formed on the surface of the first conductive type base layer. A conductive type source layer; a second conductive type emitter layer formed on the surface of the high resistance base layer so as to be separated from the first conductive type base layer; and a first conductive type emitter layer in contact with the first conductive type emitter layer. A main electrode, a second main electrode in contact with the first conductive type base layer and the second conductive type source layer, and a gate insulating film interposed between the second conductive type source layer and the second conductive type emitter layer. An insulated gate semiconductor device, comprising: a gate electrode formed in a horizontal direction, and a unit cell size in a lateral direction orthogonal to a thickness direction of each layer is 120 μm or less. A second conductive type emitter layer laminated on the first conductive type emitter layer;
A conductive high-resistance base layer; a first first conductivity-type base layer formed on the surface of the high-resistance base layer; and a first first conductivity-type base layer on the surface of the high-resistance base layer. A second conductive type base layer formed apart from the first conductive type base layer, a second conductive type emitter layer formed on the surface of the second first conductive type base layer, and the first first conductive type base layer. A second conductive type source layer formed on the surface of the conductive type base layer, a first main electrode in contact with the first conductive type emitter layer, the first first conductive type base layer and the second conductive type A second main electrode in contact with the source layer; and a gate electrode formed between the second conductive type source layer and the second conductive type emitter layer via a gate insulating film. An insulated gate having a unit cell size in a lateral direction orthogonal to a thickness direction of 120 μm or less. Semiconductor device.