JP3271255B2 - Emitter coupling logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. INDUSTRIAL APPLICATIONS BACKGROUND ART Problems to be Solved by the Invention (FIGS. 6 and 7) Means for Solving the Problems (FIGS. 1, 2 and 4) Operation (FIG. 5) Examples (FIGS. 1 to 1) FIG. 5) (1) First embodiment (FIGS. 1 to 3) (2) Second embodiment (FIGS. 4 and 5) (3) Other embodiments

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emitter-coupled logic circuit, and is suitably applied to, for example, a shift register or a frequency divider.

[0003]

2. Description of the Related Art Today, a signal processing integrated circuit (hereinafter, referred to as a signal processing IC) for processing an analog signal also employs a signal processing mode based on various control data output as serial data from a microprocessor. Settings are becoming more common.

For example, in the case of an in-vehicle stereo device, the balance of the volume and the volume reproduced from the left and right speakers by serial data, and various functions such as a tone control and a fader are set, so that a touch-type input key is used. Control and reproduction of a reproduction sound based on setting information selected immediately before by the user are realized.

At this time, a shift register for receiving serial data, serial-parallel conversion by a latch, and a data holding function are indispensable functions for realizing these functions, and these logic circuits are bipolar circuits. In the case of an IC, an emitter-coupled logic circuit (hereinafter, referred to as an ECL logic circuit) or an IIL (Integrated Injection Logi
c) It is realized by a circuit or the like.

[0006]

For example, a shift register can be constituted by a cascade connection of two stages of flip-flops FF1 and FF2 as shown in FIG.
When the number of elements per stage is large and a plurality of stages of shift registers are connected, there is a disadvantage that the circuit scale becomes large.

The flip-flops FF1 and FF2
Are transfer gates 2 and 12 each composed of a differential pair of transistors Q1, Q2 and Q11, Q12, and load resistors R1, R2.
And transistors Q3, Q4 and load resistors R11, R12
And a latch gate 3 including transistors Q13 and Q14.
And 13 as a basic configuration.

The switching of the operation state of the transfer gates 2 and 12 and the latch gates 3 and 13 is performed by the transistor Q.
Switching is performed by switching gates 4 and 14 which are differential pairs of Q5, Q6 and Q15, Q16.

A reset gate 5 and a current source 6 are connected to the switching gate 4. Here, when the reset signal RST is logic "L", the reset gate 5 controls the switching circuit 4 to an on state by drawing a current from the common emitter of the transistors Q5 and Q6 via the transistor Q7. Has been made.

The reset gate 5 outputs a reset signal R
When ST is at logic "H", a current is drawn from the connection point QM between the load resistor R1 and the transistor Q3 via the transistor Q8, thereby forcibly changing the potential of the connection point QM to logic "L". It is made to fall.

However, as can be seen from FIG. 6, when the flip-flops FF1 and FF2 are connected in cascade in this manner, about 24 elements are required for each stage, and for example, a 50-stage shift register is required. When a register is constructed, there is a problem that about 1200 elements are required and the circuit scale becomes very large.

Similarly, a frequency divider as shown in FIG. 7 is widely known as an ECL circuit having a transfer gate and a latch gate, but also in this case, since the number of elements per stage is large, a multistage configuration is employed. There is a drawback that the circuit scale becomes large when an attempt is made to construct a frequency divider.

That is, in the case of this frequency divider 20, the currents drawn from the respective gates of the latch gate 21 and the transfer gate 22 and the latch gates 31 and 32 to the current sources 24 and 34 are alternately switched by the switching gate 23. The operation state is switched by the following.

When one state is transferred to the other, and the transferred state is retransmitted to one, the polarity is inverted so that the output stage 25 outputs the frequency-divided output of the clock pulse CP. ing.

However, in this case, as can be seen from FIG. 7, if the frequency dividing circuit is configured in this way, about 2
Six elements are required, and when a multi-stage frequency divider is configured, the number of elements increases and the circuit scale becomes very large.

The present invention has been made in consideration of the above points, and has an emitter-coupled logic circuit capable of further reducing the circuit scale while maintaining high speed of a shift register and a frequency divider and coexistence with an analog circuit. It is intended to propose.

[0017]

In order to solve this problem, according to the present invention, an emitter electrode is connected in common, and a first transistor Q41 is connected to a base electrode of a second transistor Q42 to a collector electrode of the first transistor Q41. The second self-holding circuit section 43, in which the emitter electrode is connected in common with the self-holding circuit section 42 of the above, and the base electrode of the fourth transistor Q44 is connected to the collector electrode of the third transistor Q43, Six transistors Q45 and Q46
, Each collector electrode is connected to a common emitter of the first and second transistors Q41 and Q42 and a common emitter of the third and fourth transistors Q43 and Q44, and a clock signal CP applied to the base electrode is provided. Switching means 44 for alternately switching the operation states of the first and second self-holding circuit units 42 and 43 based on the first and second self-holding circuit units 42 and 43. , The threshold voltage VTH applied to the base electrodes of the first and third transistors Q41 and Q43 is outside the logical amplitude (GNDＧ−0.4 [V]) (−0.6 V).
[V]), and when transferring data, the threshold voltage VTH is set to the intermediate value of logical amplitude (-0.2 [V]),
The data held by the first self-holding circuit portion is transferred to the second self-holding circuit portion 43 based on a collector current drawn from the collector electrode of the third transistor to the collector electrode of the second transistor Q42. .

Further, in the present invention, the first and second self-holding circuit units 42 and 43 are designed to erase data when
The threshold voltage VTH is set outside the logical amplitude, and the clock signal CP is forcibly raised or lowered.
Alternatively, the data held by one of the second self-holding circuit units 42 and 43 is erased.

Further, in the present invention, a first self-holding circuit portion 71 in which an emitter electrode is commonly connected, a collector electrode of a first transistor Q71 is connected to a base electrode of a second transistor Q72, and the emitter electrode is The fourth transistor Q74 of the third and fourth transistors Q73 and Q74 which are connected in common and connected in parallel with each other.
And a differential pair of sixth and seventh transistors Q76 and Q77, the collector electrodes of which are connected to the base electrode of the fifth transistor Q75. Second transistor Q7
1 and 2 are connected to a common emitter of Q1 and Q72 and a common emitter of third, fourth and fifth transistors Q73, Q74 and Q75, and based on a clock signal CP supplied to a base electrode, first and second self-holding circuit sections. Switching means 73 for alternately switching the operation states of the transistors 71 and 72, and the collector electrode of the first transistor Q71 is connected to the power supply GND.
Is connected via a first resistor R71 to the base electrode of the second transistor Q72 and the collector electrode of the third transistor Q73 via a second resistor R72, and is connected to the collector of a fourth transistor Q74. The electrodes are
The power supply GND is connected via the third and fourth resistors R73 and R74, and the collector electrode of the second transistor Q72 is connected to the connection point between the third and fourth resistors R73 and R74. The self-holding circuit unit 71 transfers the data held by the first self-holding circuit unit 71 to the second self-holding circuit unit 72 based on the collector current drawn from the third resistor R73 to the collector electrode of the second transistor Q72. The second self-holding circuit unit 72 transfers and holds the second self-holding circuit unit 72 based on a collector current drawn into the collector electrode of the third transistor Q73 from the first and second resistors R71 and R72. The data is transferred to the first self-holding circuit unit 71.

[0020]

When erasing data held in the first and second self-holding circuit sections 42 and 43, the threshold voltage VTH applied to the base electrodes of the first and third transistors Q41 and Q43 is changed to a logical amplitude. (GND ~ -0.4 [V])
When the data is transferred, the threshold voltage VTH is set to an intermediate value of the logical amplitude (−0.2 [V]).
[V]). Thus, the data held in the latch portion of the shift register circuit for sequentially transferring data to the next stage can be reliably erased.

The data held by the first self-holding circuit 71 is transferred to the second self-holding circuit 72 based on the collector current drawn into the collector electrode of the second transistor Q72, and the collector of the third transistor Q73 is The data held by the second self-holding circuit section 72 is transferred to the first self-holding circuit section 71 by drawing the collector current divided by the third and fourth transistors Q73 and Q74 into the electrode. As a result, a circuit for dividing the frequency of the clock signal CP for switching the operation state of the first and second self-holding circuit sections 71 and 72 can be constituted by a small number of elements.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) First Embodiment In FIG. 1, reference numeral 40 denotes an ECL type shift register having a reset function as a whole, and two shift register stages constituted by ten elements are cascaded. It has a configuration. Here, the shift register stages 41 and 51 constituting the first and second stages of the shift register 40 have the same configuration.

That is, the shift register stages 41 and 51
Are two sets of latch gates 42, 43 and 52, respectively.
53, switching gates 44 and 54 and constant current source 45
And 55.

Hereinafter, the shift register stage 41 will be described. The latch gates 42 and 43 are respectively constituted by NPN type bipolar transistors Q41, Q42 and Q43, Q44 to which emitters are commonly connected.

Here, the bases of the common-collector transistors Q42 and Q44 located at the rear of the pair of transistors are connected to the common-base transistor Q4 located at the front.
1 and Q43, and a resistor R which generates a logic amplitude is provided between the connection point and the ground potential (GND).
41 and R42 are connected.

The latch gates 42 and 43 are provided in a circuit provided before the connection point, that is, a gate drive circuit 46.
And the logical outputs IIN and QS from the latch gate 42
(N), and the transistors Q41 and Q4
Based on the result of comparison with the threshold voltage VTH input to the base of No. 3, any one of the transistors Q41 and Q42 and the transistors Q43 and Q44 is switched on.

The switching gate 44 is constituted by a differential pair of transistors Q45 and Q46. When the clock input terminal CP1 is at logic "H", the switching gate 42 is turned on, and the other clock input terminal is turned on. CP
When 2 is logic "H", the latch gate 43 is switched to the ON state to switch the operation state.

When the potential of the clock input terminal CP1 is logic "H", the switching gate 44 outputs the logic output IIN of the inverted input signal IIN which is the output of the preceding gate drive circuit 46.
The logical value of QM (N) is held. Whether the collector current is drawn through the resistor R42 of the subsequent latch gate 43 in the inactive state is switched, and the logic output IQM is switched.
A logic output QS (N) having a logic value opposite to that of (N) is connected to a resistor R4.
2 is generated.

On the other hand, when the potential of the clock input terminal CP2 is logic "L", the switching gate 44
The logic value of the logic output QS (N) generated at the resistor R42 is held by the latch gate 43 at the subsequent stage. Whether the collector current is drawn or not is switched via the resistor R51 of the latch gate 52 of the succeeding flip-flop 51 in the inactive state, and the logic output IQM (N + 1) having a logic value opposite to the logic output QS (N) is connected to the resistor. Generated in R51.

At this time, the logical output IQM (N + 1) output from the output terminal of the shift register stage 41 and the logical output IQM (N) input to the input terminal are in phase, and the shift register stage 41 is based on the clock pulse CP. The logic outputs applied to the input terminals are sequentially transferred to the subsequent stage.

In this embodiment, the clock pulse CP is applied to the first latch 42 of the shift register stage 41.
Since there is no function to take in the inverted input signal IIN when is at the logic "H", the gate drive circuit 46 transfers the inverted output of the input signal IN to the latch gate 42.

Here, the gate drive circuit 46 is composed of transistors Q61 and Q62 forming a differential pair and a switching gate for switching the operation state of the differential pair.

The switching of the switching gate is performed by switching which of the transistors Q63 and Q64 draws the collector current drawn by the transistor Q65 serving as the current source.

The shift register 40 forcibly resets the logical values of the logical outputs QS (N) and QS (N + 1) output from the shift resist stages 41 and 51 by the reset circuit 47 to the logical "L". In this embodiment, the reset circuit 47 is constituted by an inverter 48 and an OR circuit 49.

Here, the inverter 48 outputs the reset signal IN
IT is inverted and the threshold voltage V is input to the threshold voltage input terminal.
Supply TH. The OR circuit 49 outputs a reset signal IN
The logical sum of IT and clock pulse CP is used as the clock input terminal C.
P1 and its inverted output to the other clock input terminal C
This is supplied to P2.

In the case of this embodiment, the reset circuit 47
When reset signal INIT is logic "L" (ie, during normal operation), threshold voltage VTH is set to -0.2 [V], whereas when logic "H" (that is, at reset), threshold voltage VTH is set. VTH is set to -0.6 [V].

The value of the threshold voltage VTH when the reset signal INIT is logic "H" is determined by the logic output QS (N) output from the shift register stages 41 and 51.
And QS (N + 1) are set sufficiently lower than the voltage value when the logic value is logic "L".

The potential of the clock input terminal CP1 given by the OR of the OR circuit 49 is equal to the clock pulse C
When P or the reset signal INIT rises to logic "H", it rises to logic "H".

As a result, at the time of reset, the reset circuit 47 controls the transistors Q41, Q42 and Q51, Q52 constituting the latch gates 42 and 52, which are connected to the common collector, to the on state, and loads the collector current. Resistors R42 and R52
Logic outputs QS (N) and Q
S (N + 1) is forcibly reduced to logic "L" and initialized.

In the above configuration, the shift register 40
Will be described separately for two operations, reset and transfer of latch data. First, when resetting the latch data immediately after power-on, the reset signal INIT is raised to logic "H", the threshold voltage VTH is lowered to -0.6 [V], and the logic value of the clock input terminal CP1 is forcibly set to logic. Start up at "H".

At this time, the switching gates 44 and 54
Of transistors Q45, Q46 and Q5
5, transistors Q45 and Q55 out of Q56 are turned on, and latch gates 42 and 52 in the preceding stage are selected to be turned on.

Here, the threshold voltage VTH applied to the bases of the transistors Q41 and Q51 constituting the latch gates 42 and 52 is as low as -0.6 [V] and is outside the logic amplitude, so that the logic output IQM ( N) and IQM (N + 1) regardless of the value of the transistor Q41.
And Q51 are turned off, and the other transistors Q42 and Q52 are turned on.

Accordingly, the collector current is supplied from the resistors R42 and R52 of the latch gates 43 and 53 in the inactive state to the current sources 45 and 5 via the transistors Q42 and Q52.
5, the logical outputs QS (N) and QS (N + 1) output from the output terminal are forcibly set to logical "L", respectively, and are initialized.

Subsequently, when the input of the serial data IN is started, the data is transferred based on the clock pulse CP. At this time, the clock pulse CP becomes logic "L".
The case where the logic outputs QS (N) and QS (N + 1) of the first and second shift register stages 41 and 51 are logic “H” and “L” respectively will be described.

At this time, the switching gates 44 and 54
Since the transistors Q46 and Q56 are turned on, the latch gates 43 and 53 at the subsequent stage operate as latch circuits, and hold the logical values of the logical outputs QS (N) and QS (N + 1). On the other hand, the second shift register stage 5
1 is inactive at this time, so that the logic output IQM of the latch gate 52 is inactive.
The logic value of (N + 1) is determined by the collector current drawn by transistor Q44.

Here, the logic output Q of the shift register stage 41
Since the logical value of S (N) is logical "H", the logical output Q
The logic “L” obtained by inverting S (N) is the logic output IQM (N +
Transferred as 1).

Next, when the clock pulse CP rises to the logic "H", the switching gate 4 is turned on, contrary to the above case.
The transistors Q45 and Q55 of Nos. 4 and 54 are turned on, respectively, and the latch gates 42 and 52 in the preceding stage operate as latch circuits.

As a result, the transistors Q44 and Q54
Through the logical outputs QS of the shift registers 41 and 51
Although (N) and QS (N + 1) are no longer transferred to the subsequent stage, the other latch gates 42 and 52 shift to the active state and hold the state newly set immediately before.

For example, if the logic value of the immediately preceding inverted input signal IIN is logic "H", the latch gate 42 holds this logic value and the transistor Q42 is turned on, so that the logic output QS ( N) falls to the opposite logical value, that is, logical "L".

The latch 52 of the shift register 51 at the next stage holds the logical value "L" of the logical output IQM (N + 1), and the transistor Q51 is turned on so that the collector current does not flow through the resistor R52.
The logic “H” is output as S (N + 1).

As a result, at the end of one cycle of the clock pulse CP, the logic outputs QS (N) and QS (N + 1) of each of the shift register stages 41 and 51 are changed from logic "H" and logic "L" to logic "L" and logic "L". The logic “H” and the immediately preceding logic value are transferred to the subsequent stage. Similarly, the logic value of the serial data is sequentially transferred to the subsequent stage each time the clock pulse CP falls and rises, and the shift register 40 functions as a shift register.

According to the above arrangement, the latch portion of each shift register stage 41 is connected to the base-grounded transistor Q4.
1, Q43 and collector-grounded transistor Q42,
The shift register stage can be constituted by ten elements by transferring the signal by the collector current flowing through the transistors Q42 and Q44 whose collectors are grounded. The number of elements can be reduced to less than half of the number of shift register stages with, and the degree of integration can be further improved.

In addition, an IIL (Integrated Injec)
Integration Logic) and the IIL
This method is superior when used for processing serial data because it does not have a high-speed and special manufacturing process.

(2) Second Embodiment In FIG. 4, reference numeral 70 denotes an ECL-type frequency dividing circuit as a whole, and latch gates 71 and 7 constituting a self-holding circuit.
2 and a switching gate 73 for switching between them
, And a current source 74 and an output stage 75.

In this embodiment, the latch gate 71 is connected to a common base transistor Q to which an emitter is commonly connected.
71 and a collector grounded transistor Q72, of which the base of transistor Q72 is transistor Q71.
Is connected via a resistor R72.

Here, the collector of the transistor Q71 is grounded to the ground potential GND via the resistor R71 which generates a logic amplitude together with the resistor R72, and a constant voltage of -0.2 [V] is applied to the base.

On the other hand, the other latch gate 72 is connected to a common base transistor Q73 to which an emitter is commonly connected,
Q74 and a collector-grounded transistor Q75, of which the transistor Q73 is provided with a latch gate 71 of the preceding stage by a collector current flowing based on data held.
To transfer the data to.

Here, a constant voltage of -0.2 [V] is applied to the bases of the transistors Q73 and Q74 whose bases are grounded, and the base potential of the transistor Q72 of the preceding latch gate 71 is applied to the collector of the transistor Q73. It has been made like that.

The base of the transistor Q75 is connected to the collector of the transistor Q74 which is grounded. The other end of the collector of the transistor Q74 is supplied with a ground potential GND and a resistor R which generates a logic amplitude.
74 and R73 are connected, and the collector of the transistor Q72 of the latch gate 71 of the preceding stage is connected to the connection point between the resistors R73 and R74.

The switching gate 73 is constituted by a differential pair composed of transistors Q76 and Q77, and supplies a collector current drawn into a current source 74 connected to an emitter to either the latch gate 71 or 72 so that the latch gate 73 is switched. Is switched over.

The frequency divider 70 outputs the logic output of the latch gate 72 in the second stage from the output stage 75 constituted by the buffer transistor Q79, the transistor Q80 constituting the current source and the resistor R76 from the output terminal. Has been made.

In the above configuration, the clock pulse CP
Is logic "H" (FIG. 5A), and the latch gate 72
That the transistor Q74 of the frequency divider 7 is off.
The operation of 0 will be described.

At this time, the transistor Q78 of the current source 74
The collector current I0 flowing into the transfer transistor Q
The collector current I / 2, which is divided by the transistor Q74 constituting a latch portion and the latch portion, flows into the transistor Q74.

This current (I / 2) flows through two resistors R73 and R74 (= R + R), the potential at point B2 drops to -0.4 [V] as shown in FIG. Voltage Q falls to logic "L". As a result, the base potential of the transistor Q75 becomes lower than the base potential (−0.2 [V]) of the other transistor Q74 by 0.2 [V], and the transistor Q75 maintains the off state.

On the other hand, the current (I / 2) flowing through the transfer transistor Q73 is equal to the resistances R71 and R72 (= R + R).
And the potential at point A2 drops to -0.4 [V] as shown in FIG. 5 (C).

Next, when the clock pulse CP becomes logic "L" (ie, -VF-0.4 [V]), the current switches from the transistor Q77 to the transistor Q76. At this time, the base potential of the transistor Q72 constituting the latch portion of the latch gate 71 is -0.4 [V], which is lower than the base potential of the other transistor Q71 whose base is grounded, so that the collector current I0 flows through the transistor Q71.

At this time, the collector current I0 flows only through the resistor R71, but since the current value is twice the current (I / 2) flowing through the transfer transistor Q73, the points A1 and A2
Is maintained at -0.4 [V]. On the other hand, the potentials at the points B1 and B2 of the latched gate 72 in the inactive state are both 0 [V] because the transistors Q72 and Q74 are turned off, and become logic "H".

When the clock pulse CP becomes logic "H" again, the latch gate 72 switches to the active state. In this case, since the base potential of the transistor Q75 is higher than the logic "H" (that is, 0 [V]) and the base potential of the transistor Q74, the collector current I0 flows to the transistor Q75 side, and the other transistors Q73, Q73
Reference numeral 74 keeps the off state because the emitter potential rises.

As a result, no current flows through the resistor R71 of the latch gate 71 in an inactive state, so that the potentials at the points A1 and A2 rise from -0.4 [V] to 0 [V]. Subsequently, when the clock pulse CP changes to logic "L" again and the latch gate 71 switches to the active state, the collector current I0 flows through the resistor R73 this time because the transistor Q72 is on.

As a result, the potential at the point B2 of the latch gate 72 in the inactive state changes from 0 [V] to -0.4 [V].
Fall to. The frequency divider 70 repeats the same operation each time the logic value of the clock pulse CP switches, and outputs an output obtained by dividing the clock pulse CP by two from the output terminal.

According to the above configuration, one of the pair of latch gates 71 and 72 is constituted by the transistor Q71 whose base is grounded and the transistor Q72 whose collector is grounded, and the other latch gate 7 is connected.
2 comprises a transistor Q74 whose base is grounded, a transistor Q75 whose collector is grounded, and a transistor Q73 for transfer. A signal latched on the latch gate 71 is transferred by a collector current flowing through the transistor Q72. By transferring the signal latched by the latch unit 72 by current division of the transistors Q73 and Q74, the frequency divider can be constituted by 16 elements.

As a result, the number of frequency dividers that can be mounted in the same area can be greatly increased, and the range in which a frequency divider based on ECL can be used can be further expanded.

(3) Other Embodiments In the above-described embodiment, when resetting data, the logic value applied to the clock input terminal CP1 at the rising edge of the reset signal INIT is forcibly set to the logic "H". ”, Whereby the logical output QS (N),
Although the case where QS (N + 1) is initially set to the logic "L" has been described, the present invention is instead replaced with the clock input terminal CP.
The logic value given to 1 is forced to fall to logic "L", whereby the logic outputs QS (N), QS (N + 1)
May be initialized to logic “H”.

In the above embodiment, the case where the shift register has a two-stage configuration has been described. However, the present invention is not limited to this, and can be widely applied to a case where three or more stages are connected.

Further, in the above embodiment, the frequency divider 7
The case where the clock pulse is divided by 2 by 0 has been described. However, the present invention is not limited to this. By connecting a plurality of frequency dividers, the clock pulse can be divided into N (N = 3, 4,...).
The present invention may be widely applied to frequency division.

Further, in the above embodiment, the case where the reset signal INIT is set to -0.6 [V] has been described. However, the present invention is not limited to this, and may be set to another value.

Further, in the above embodiment, the case where the logic amplitude is set to 0.4 [V] has been described, but the present invention is not limited to this, and the logic amplitude may be set to another value.

[0079]

As described above, according to the present invention, when erasing data held in the first and second self-holding circuits, the data is applied to the base electrodes of the first and third transistors. The threshold voltage is set outside the logical amplitude, and when data is transferred, the threshold voltage is set to an intermediate value of the logical amplitude. As a result, the data held in the latch can be reliably erased.

According to the present invention, as described above, the data held by the first self-holding circuit section is stored in the second self-holding circuit section based on the collector current drawn into the collector electrode of the second transistor.
And the collector current divided by the third and fourth transistors is drawn into the collector electrode of the third transistor, and the data held by the second self-holding circuit unit is transferred to the third self-holding circuit unit. 1 to the self-holding circuit unit. Thus, the frequency divider for dividing the frequency of the clock signal for switching the operation state of the first and second self-holding circuit units can be configured with a small number of elements.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of a shift register using an emitter-coupled logic circuit according to the present invention.

FIG. 2 is a connection diagram for explaining the input stage.

FIG. 3 is a schematic diagram for explaining a threshold voltage applied at the time of data transfer and erasure;

FIG. 4 is a connection diagram showing one embodiment of a frequency divider using an emitter-coupled logic circuit according to the present invention.

FIG. 5 is a signal waveform diagram for explaining the operation.

FIG. 6 is a connection diagram showing a configuration of a conventional shift register.

FIG. 7 is a connection diagram showing a configuration of a conventional frequency divider.

[Explanation of symbols]

1, 40 shift register, 2, 3, 12, 13, 2
1, 22, 31, 32, 42, 43, 52, 53 ... Latch gates, 4, 14, 23, 44, 54 ... Switching gates, 20 ... Frequency dividers, 41, 42 ... Shift resist stages.

Claims (3)

(57) [Claims] An emitter electrode is connected in common, a collector electrode of a first transistor is connected to a base electrode of a second transistor, and a first self-holding circuit section is connected to the collector electrode of the second transistor. A second self-holding circuit section in which a base electrode of a fourth transistor is connected to a collector electrode of the transistor; and a differential pair of fifth and sixth transistors, wherein each collector electrode is formed of the first and second transistors. Switching means connected to the common emitter of the transistors and the common emitter of the third and fourth transistors and alternately switching the operation states of the first and second self-holding circuit units based on a clock signal applied to a base electrode; The first and second self-holding circuit units are provided to base electrodes of the first and third transistors when erasing data. When the threshold voltage is set outside the logical amplitude and data is transferred, the threshold voltage is set to an intermediate value of the logical amplitude, and the collector electrode of the second transistor is shifted from the collector electrode of the third transistor. An emitter coupling logic circuit for transferring data held by the first self-holding circuit unit to the second self-holding circuit unit based on a collector current drawn into the emitter circuit. 2. The first and second self-holding circuit sections, when erasing data, set the threshold voltage outside the logical amplitude and forcibly raise or lower the clock signal. 2. The emitter-coupled logic circuit according to claim 1, wherein the data held by one of the first and second self-holding circuit units is erased. 3. A first self-holding circuit section in which an emitter electrode is connected in common and a collector electrode of a first transistor is connected to a base electrode of a second transistor, and an emitter electrode is connected in common and connected in parallel with each other. A second self-holding circuit part in which the base electrode of the fifth transistor is connected to the collector electrode of the fourth transistor of the third and fourth transistors, and a differential pair of the sixth and seventh transistors Each collector electrode is connected to a common emitter of the first and second transistors and a common emitter of the third, fourth and fifth transistors, and is connected to the common electrode of the third, fourth and fifth transistors based on a clock signal applied to the base electrode. Switching means for alternately switching the operation states of the first and second self-holding circuit units, wherein the collector electrode of the first transistor is connected to a power source and the first transistor.
And the collector electrode of the fourth transistor is connected to the base electrode of the second transistor and the collector electrode of the third transistor via a second resistor. And a third self-holding circuit unit, the collector electrode of the second transistor being connected to a connection midpoint of the third and fourth resistors, Transferring the data held by the first self-holding circuit unit to the second self-holding circuit unit based on a collector current drawn into the collector electrode of the second transistor from the third resistor; The self-holding circuit unit stores data held by the second self-holding circuit unit based on a collector current drawn into the collector electrode of the third transistor from the first and second resistors. An emitter-coupled logic circuit for transferring the data to a first self-holding circuit unit.