JP3270954B2 - Method of manufacturing thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved method of manufacturing a thin film transistor matrix for driving a liquid crystal display.

At present, a liquid crystal display device is frequently used for a display portion in an information processing device, a display portion in a television, and the like. In order to achieve this, it is necessary to eliminate the occurrence of defects and to enable manufacturing at a high yield.

Since the production yield of a liquid crystal display device largely depends on the quality of a thin film transistor matrix,
A manufacturing method that does not cause such defects must be developed.

[0004]

2. Description of the Related Art FIG. 11 is a plan view of an essential part showing one pixel in a conventional thin film transistor matrix.

In the drawing, 1 is a gate, 2 is a gate bus line, 3 is a storage capacitor bus line, 4 is a drain, 5 is a drain bus line, 6 is a source, and 7 is a pixel electrode. Are respectively shown.

Here, a thin film transistor (thin film t) is formed by the gate 1, the drain 4, the source 6, and the like.
It is needless to say that a transistor (TFT) is configured.

FIGS. 12 to 20 are cutaway side views of a main part showing a thin film transistor matrix in a process step for explaining a conventional technique, and will be described below with reference to these drawings. These figures correspond to those cut along the line XY shown in FIG.

Referring to FIG. 12, 12- (1) A gate 12, a gate bus line, a storage capacitor bus bus are formed by forming a Ti / Al film on a glass substrate 11 and then patterning it.
A line 13 is formed.

Referring to FIG. 13, 13- (1) P-CVD (plasma chemical)
The gate insulating film 14 made of SiN having a thickness of 400 [nm], the a-Si operation layer 15 having a thickness of 10 [nm], and the thickness of 10 [nm] are obtained by applying an al deposition method. The channel protection film 16 made of SiN is formed. Here, a in a-Si means amorphous (hereinafter the same).

Referring to FIG. 14, 14- (1) A resist film 17 is formed on the surface, and a gate 1 is formed.
Back exposure using a Ti / Al film as a mask
Patterning is performed by self-alignment, and surface exposure is performed using a photomask 18 having a pattern corresponding to the channel so that the resist film 17 is left only on the channel.

Referring to FIG. 15, 15- (1) The channel protective film 16 is etched using the resist film 17 as a mask.

Referring to FIG. 16, 16- (1) After removing the resist film 17, etching is performed for about 10 seconds with dilute hydrofluoric acid in order to remove a natural oxide film on the surface. 16- (2) An n ⁺ -a-Si ohmic contact layer 19 and a Cr film 20 are formed.

Referring to FIG. 17, 17- (1) A resist film 21 having a pattern of a source electrode, a drain electrode, and a drain bus line is formed.

18- (1) Cr film 2 using resist film 21 as a mask
0, n ⁺ -a-Si ohmic contact layer 19, a
Etching the Si working layer 15; In the figure, Cr
The source electrode obtained by etching the film 20 is indicated by 20S, and the drain electrode is indicated by 20D.

Referring to FIG. 19, 19- (1) By applying the sputtering method,
After forming an ITO (indium tin oxide) film, the pixel electrode 22 is formed by etching.

Referring to FIG. 20, 20- (1) the application of the P-CVD method
An N protective film 23 is formed, and an opening 23A for exposing the pixel electrode 22 is formed.

[0017]

According to the conventional technique described above, when the channel protective film 16 made of SiN is etched in the step 15- (1), foreign substances and the like existing in the gate insulating film 14 made of SiN are removed. As a cause, the etchant seeps and pin holes are generated.

Although the gate insulating film 14 is not only a gate insulating film but also serves as an interlayer insulating film in other portions, the pin holes are formed in overlapping portions of the conductive film, for example, the gate 12 and the gate insulating film. Bus line and storage capacitor bus line 13 and source electrode 2
If it exists between the OS, the drain electrode 20D, the pixel electrode 22, and the like, an interlayer short-circuit occurs, resulting in a line defect or a point defect when viewed on a display.

Similarly, in step 15- (1), SiN
When etching the channel protective film 16 made of SiN, the SiN is etched with hydrofluoric acid. When the etching is completed, the a-Si operation layer 15 is exposed.

Usually, since the a-Si surface is water repellent, water washing is performed after the completion of etching, and when water is dried, water stains (water marks) tend to occur. In particular,
In the prior art, a mask made of a resist film is used for etching the channel protective film 16 made of SiN. However, since the resist film is thick, water stains are further generated due to the influence of the step. It will be easier. The reason is that an air knife is used for drying water after washing with water, but there is a drawback that drainage is poor if there is a step.

The above-mentioned water stain causes a contact failure between the a-Si operating layer 15 and the n ⁺ -a-Si ohmic contact layer 19 and causes a point defect on a display.

The present invention solves the problem of etching the channel protective film by simply adding a simple modification to the manufacturing process, and can reduce various display defects caused by interlayer short circuit and water stain. Attempts to improve manufacturing yield.

[0023]

In the method of manufacturing a thin film transistor matrix according to the present invention, (1) at least a gate electrode (for example, a gate electrode 32G) is formed on an insulating transparent substrate (for example, a glass substrate 31). Then, a gate insulating film (for example, a gate insulating film 34 made of SiN), an electrode material film (for example, a Cr film 35), and a semiconductor ohmic contact layer (for example, n ⁺ -a-Si)
Forming a layer of the ohmic contact layer 36), and then removing the semiconductor ohmic contact layer and the electrode material film in the portion where the channel of the thin film transistor is to be formed to form an opening (for example, the opening 37A). And a step of laminating a semiconductor operation layer (for example, an a-Si operation layer 38) and a channel protection film (for example, a SiN channel protection film 39) for filling the opening. Or

(2) In the above (1), the electrode material film is a transparent conductive film (for example, ITO film or the like), and the semiconductor ohmic contact layer and the resist for forming the opening by removing the electrode material film are removed. The film is exposed from the back of the insulating transparent substrate using the gate electrode as a mask, or

(3) In the above (1) or (2),
When forming a source electrode and a drain electrode with an electrode material film that is a transparent conductive film, a step of simultaneously forming a pixel electrode connected to the source electrode is included, or

(4) In the above (1), (2) or (3), when the gate insulating film, the electrode material film and the semiconductor ohmic contact layer are laminated, the gate insulating film and the electrode material film An etching stop layer (for example, an a-Si etching stop layer) is interposed therebetween.

[0027]

By adopting the above means, when etching the channel protective film, it is possible to prevent the generation of pins and holes in the gate insulating film due to the penetration of the etchant, so that the occurrence of interlayer short-circuit is reduced. In addition, at the time of hydrofluoric acid treatment performed for improving the contact characteristics, since there is no resist film having a large step, drainage during the drying treatment after etching is good, Water stains are unlikely to occur, so
The production yield of the matrix is improved, so that line defects and point defects on the display can be reduced.

FIG. 1 is a plan view of a principal part showing one pixel of a thin film transistor matrix completed according to the embodiment of the present invention.

In the figure, 32 is a gate bus line, 32G is a gate electrode, 33 is a storage capacitor bus line, 35S is a source electrode, 35D is a drain electrode, and 35L is a drain electrode connected to the drain electrode 35D. Bus line, opening 37A, source electrode 3
The pixel electrodes in contact with 5S are shown.

FIGS. 2 to 10 are main part explanatory diagrams showing a thin film transistor matrix at important process steps for explaining an embodiment of the present invention. Hereinafter, description will be given with reference to these drawings. In the drawing, (A) is a cutaway side of the main part,
FIG. 1B shows a plan view of a main part, and FIG. 1B shows a plan view of the main part as needed, and FIG.
Corresponds to the plane cut along the line XY.

FIG. 2 2- (1) A Ti film having a thickness of, for example, 80 [nm] and an Al film having a thickness of 80 [nm] are formed on the glass substrate 31 by applying the sputtering method.

2- (2) Etching of Ti / Al film by applying a resist process in the lithography technique and a plasma etching method using chlorine and boron chloride (Cl ₂ + BCl ₃ ) as an etching gas. To the gate electrode 32G and the gate bus line 3
2. Form the storage capacitor bus line 33.

Referring to FIG. 3, 3- (1) a gate insulating film 34 made of SiN having a thickness of 400 [nm] and a Cr film 35 having a thickness of, for example, 100 [nm] by applying the P-CVD method. Then, an n ⁺ -a-Si ohmic contact layer 36 having a thickness of, for example, 100 nm is sequentially formed.

Referring to FIG. 4, 4- (1) opening 3 is formed on gate electrode 32G by applying a resist process in the lithography technique.
A resist film 37 having 7A is formed.

Referring to FIG. 5, 5- (1) etching gas is Cl ₂ + BCl ₃ (n ⁺
-A-Si) plasma etching method, and
By applying a wet etching method using ceric ammonium nitrate (for Cr) as an etchant, the ohmic contact layer 36 and the Cr film 35 are etched using the resist film 37 as a mask, and the opening 37 is formed.
A is stretched.

6- (1) The resist film 37 is immersed in a resist stripper.
Then, etching is performed for about 10 seconds with dilute hydrofluoric acid to remove the natural oxide film on the surface.

6- (2) The a-Si working layer 38 having a thickness of, for example, 50 nm is obtained by applying the P-CVD method.
Then, a SiN channel protective film 39 having a thickness of, for example, 200 [nm] is formed by lamination.

Referring to FIG. 7, 7- (1) A resist film 40 having a pattern covering the TFT region and having a pattern extending in the direction of the drain bus line is formed by applying a resist process in the lithography technique. .

8- (1) Dilute hydrofluoric acid (for SiN)
Of the SiN channel protective film 39 and the a-Si by using the resist film 40 as a mask by applying the wet etching method as described above and the plasma etching method using Cl ₂ + BCl ₃ (for a-Si) as an etching gas. The operation layer 38 and the n ⁺ -a-Si ohmic contact layer 36 are sequentially etched so as to form a mesa in the TFT region.

9- (1) By applying a resist process in the lithography technique, a source electrode, a drain electrode,
Resist film 4 having a drain bus line pattern
Form one.

10- (1) By applying a wet etching method using ceric ammonium nitrate as an etchant,
Using the resist film 41 as a mask, the Cr film 35 is etched to form a source electrode 35S, a drain electrode 35D, and a drain bus line 35L.

10- (2) An ITO film having a thickness of, for example, 100 nm is formed by applying the sputtering method.

10- (3) By applying the resist process in the lithography technique and the wet etching method using ferric chloride as an etchant, the ITO film formed in the step 10- (2) is formed. The pixel electrode 42 is formed by etching.

In the present invention, the present invention is not limited to the above embodiment, and many other modifications can be realized.
-In (1), the source electrode 35S and the drain electrode 3
When a resist film 37 having an opening 37A is formed on the gate electrode 32G by replacing Cr, which is a material such as 5D, with a transparent conductive film such as ITO, a back exposure using the gate electrode 32G as a mask is performed. Patterning by self-alignment.

In this manner, the advantage of the self-alignment, that is, the necessity of pattern alignment is eliminated, the element size can be reduced by the alignment margin, and the aperture ratio of the pixel is improved. The advantage of being able to do so can be enjoyed.

The source electrode 35S and the drain electrode 3
When 5D or the like is formed of a transparent conductive film, the source electrode 35
Since S and the pixel electrode 42 can be formed integrally, there is no need to separately provide a step of forming the pixel electrode 42.

Further, in the step 6- (1),
After removing the resist film 37, etching is performed for about 10 seconds with dilute hydrofluoric acid in order to remove the natural oxide film on the surface. In this case, a slight amount of gate insulation made of SiN is used. The film 34 is etched.

To deal with this, the above-mentioned step 3- (1)
In this case, if each layer is formed by interposing an etching stop layer made of, for example, a-Si between the gate insulating film 34 and the Cr film 35, the etching of the gate insulating film 34 can be prevented.

[0049]

In the method of manufacturing a thin film transistor matrix according to the present invention, at least a gate electrode is formed on an insulating transparent substrate, and then a gate insulating film, an electrode material film, and a semiconductor ohmic contact layer are laminated. Then, an opening is formed by removing the semiconductor ohmic contact layer and the electrode material film in a portion where a channel of the thin film transistor is to be formed, and a semiconductor operation layer and a channel protection film that fill the opening are stacked. ing.

By adopting the above configuration, when etching the channel protective film, it is possible to prevent the occurrence of pin holes and holes in the gate insulating film due to the penetration of the etchant. In addition, at the time of hydrofluoric acid treatment performed for improving the contact characteristics, since there is no resist film having a large step, drainage during the drying treatment after etching is good, Since water stain is unlikely to occur, the production yield of the thin film transistor matrix is improved, and thus line defects and point defects on the display can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part showing one pixel of a thin film transistor matrix completed according to an embodiment of the present invention.

FIG. 2 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 3 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining one embodiment of the present invention.

FIG. 4 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 5 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 6 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 7 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 8 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 9 is an explanatory view of a main part of a thin film transistor matrix in a process step for explaining one embodiment of the present invention.

FIG. 10 is an explanatory view of a main part showing a thin film transistor matrix in a process key point for explaining an embodiment of the present invention.

FIG. 11 is a plan view of a main part showing one pixel in a conventional thin film transistor matrix.

FIG. 12 is a fragmentary side view showing a thin film transistor matrix at a key point in a process for explaining a conventional technique.

FIG. 13 is a fragmentary sectional side view showing a thin film transistor matrix at a key point in a process for explaining a conventional technique.

FIG. 14 is a fragmentary sectional side view showing a thin film transistor matrix at a key point in a process for explaining a conventional technique.

FIG. 15 is a fragmentary side view showing a thin film transistor matrix at a key point in a process for explaining a conventional technique.

FIG. 16 is a cutaway side view of a main part showing a thin film transistor matrix in a process key point for explaining a conventional technique.

FIG. 17 is a fragmentary side view showing a thin film transistor matrix in a process key point for explaining a conventional technique.

FIG. 18 is a fragmentary side view showing a thin film transistor matrix at a key point in a process for explaining a conventional technique.

FIG. 19 is a fragmentary side view showing a thin film transistor matrix at a key point in a process for explaining a conventional technique.

FIG. 20 is a fragmentary side view showing a thin film transistor matrix in a process key point for explaining a conventional technique.

[Explanation of symbols]

31 Glass substrate 32 Gate bus line 32G Gate electrode 33 Storage capacitor bus line 34 Gate insulating film 35 Cr film 35S Source electrode 35D Drain electrode 35L Drain bus line 36n ⁺ -a-Si ohmic contact layer 37 resist film 37A opening 38 a-Si working layer 39 SiN channel protective film 40 resist film 41 resist film 42 pixel electrode

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-41518 (JP, A) JP-A-5-199218 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368 G09F 9/30 338 H01L 29/786

Claims (4)

(57) [Claims] A step of forming at least a gate electrode on an insulating transparent substrate and then forming a gate insulating film, an electrode material film, and a semiconductor ohmic contact layer on the insulating transparent substrate; Forming an opening by removing the semiconductor ohmic contact layer and the electrode material film, and then forming a semiconductor active layer and a channel protection film that fill the opening. A method for manufacturing a thin film transistor matrix, which is characterized in that: 2. The method according to claim 1, wherein the step of removing the semiconductor ohmic contact layer and the electrode material film to form an opening comprises exposing the resist film from the back of the insulating transparent substrate using the gate electrode as a mask. 2. The method according to claim 1, wherein the method is performed. 3. The method according to claim 1, further comprising the step of simultaneously forming a pixel electrode connected to the source electrode when forming the source electrode and the drain electrode with the electrode material film which is a transparent conductive film. Item 3. A method for manufacturing a thin film transistor matrix according to Item 2. 4. The method according to claim 1, wherein an etching stop layer is interposed between the gate insulating film and the electrode material film when the gate insulating film, the electrode material film, and the semiconductor ohmic contact layer are laminated. The method for manufacturing a thin film transistor matrix according to claim 2.