JP3263918B2 - Error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial application Conventional technology (FIGS. 2 to 9) Problems to be solved by the invention (FIGS. 2 to 10) Means for solving the problem (FIG. 1) Operation (FIG. 1) Example (FIG. 1) 9) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit, and more particularly, to an error correction circuit for detecting and correcting errors in transmission data transmitted by adding an error correction code based on a product code format.

[0003]

2. Description of the Related Art Conventionally, as a recording / reproducing apparatus for recording information data at high density, ANSI ID-1 format (Th.
ird draft PROPOSED AMERICAN NATIONAL STANDARD 19mm
TYPEID-1 INSTRUMENTATION DIGITAL CASSETTE FORMAT
There is a data recorder based on X3B6 / 88-12 Project 592-D 1988-03-22).

In such a data recorder, information data is subjected to error correction encoding in a product code format using a Reed-Solomon code, and the resulting data is recorded on a magnetic tape, and is reproduced. Processing is performed to detect transmission errors and correct them.

The outline of this data recorder will be described below. FIG. 2 shows a recording pattern on a magnetic tape by a data recorder conforming to the ID-1 format. ANN
Is an annotation track for recording annotations. .., TR1, TR2, TR3,... Are data tracks on which information data is recorded, and one sector is formed for each track. Each data track is alternately recorded in azimuth. CTL is a control track in which a control signal is recorded, and TC is a time code track in which a time code is recorded.

The data tracks TR1, TR2, TR
.. Are defined as shown in FIG. 3 in common for each track. That is, one data track TR corresponds to one sector S
It is compatible with EC, and includes a preamble part PR, a data recording part DT, and a postamble part PS. The preamble part PR corresponds to the lower head of the data tracks TR1, TR2, TR3,.

The preamble part PR includes a rising sequence RUS having a length of 20 bytes, a synchronization code SYNC _PR and a sector identification data ID _SEC1 each having a length of 4 bytes,
It is formed from auxiliary data DT _AUX having a length of 6 bytes.

The following data recording section DT has 256 synchronization blocks BLK (BLK ₀ , BLK ₁ , BLK ₂ ,...).
.., BLK ₂₅₅ ), and the input information data is recorded in this portion. Each synchronization block BLK has a 4-byte block synchronization code SYNC _BLK , a 1-byte block identification data ID _BLK , and a 153-byte inner data (internally encoded input information data) D
It is formed by a parity code RI consisting of I and an 8-byte Reed-Solomon code. The subsequent postamble part PS has a 4-byte length synchronization code S.
It is formed by YNC _PS and sector identification data ID _SEC2 .

FIG. 4 shows a recording system of an ID-1 format data recorder. In the recording system 1, input information data is subjected to error correction coding for forming a product code, and is recorded. The outline of the operation of each circuit is as follows. First, input information data DT _USE having a 1-byte 8-bit configuration is input to the outer code generation circuit 2.

As shown in FIG. 5, the code generation circuit 2 uses a predetermined generator polynomial for each data block in units of 118 bytes of the input information data DT _USE to convert the data block from 10 bytes of the Reed-Solomon code. The parity codes RO _{0 to} RO ₃₀₅ are generated as outer codes, added to the end of each data block, and output as an outer data block DO. The outer data block DO is sent to the memory 4 via the first multiplexer 3.

FIG. 6 shows the structure of the memory 4 and the data arrangement in the memory. As shown in FIG.
It is composed of memories MEM1 and MEM2 each having 54 bytes and 128 bytes in a column, and MEM1 has 153 blocks of sequentially input outer data blocks DO _{0 to} DO _0.
O ₁₅₂ has outer data block DO in MEM2.
Outer data blocks DO _{153 to} DO ₃₀₅ for 153 blocks sequentially input after _{0 to} DO ₁₅₂ are written for one outer data block for each column. The information data of one outer data block is 118 bytes, and each of the memories MEM1 and MEM2 has 1 byte.
Since 53 blocks are written, 118 ×
This means that 153 × 2 bytes, that is, 36,108 bytes of information data have been written.

The order of writing data in each column of the memories MEM1 and MEM2 is the order of the direction A in FIG.
The lower 10 bytes of each of EM1 and MEM2 correspond to an outer code. The memory 4 also includes data block identification data ID _B generated by the identification data generation circuit 5 for identifying each row of the memories MEM1 and MEM2.
The data ID _{BE for} the even number of the data block identification data ID _B is sent to the memory MEN1, and the data ID _BO for the odd number is sent to the memory MEM2, one column each, The data is written in the order of the direction A.

The data written in the memories MEM1 and MEM2 is such that one row of data is treated as one block,
They are read out in the order of direction B. For reading in units of rows, data block identification data ID _B (00, 01, 02, 03,...)
Are performed alternately for the memories MEM1 and MEM2.

The data read from the memories MEM1 and MEM2 is input to the inner code generation circuit 6. Inner code generating circuit 6, for each of the data blocks inputted, using a predetermined generating polynomial to generate a parity code RI ₀ to Ri ₂₅₅ of 8 bytes of Reed-Solomon code as the inner code, each data block After the
Inner data blocks DI _{0 to} DI as shown in FIG.
_{The value} is output to the second multiplexer circuit 7 as ₂₅₅ .

The second multiplexer circuit includes an inner data block DI ₀ comprising preamble data PR, postamble data PS formed by the preamble section postamble section generation circuit 8 and an output of the inner code generation circuit 6.
ＤＩDI ₂₅₅ are sequentially selected and output. The order of the output data, the preamble data PR, inner data blocks DI ₀ ~DI _255, a post-amble data PS.

The output of the second multiplexer circuit 7 is input to the data distribution circuit 9. The data distribution circuit 9 distributes (randomizes) the data by taking an exclusive OR of one byte of the input data and predetermined data. The dispersed data is input to the 8-9 modulation circuit 10. This 8-9 modulation circuit 10 removes the DC component of the signal waveform recorded on the magnetic tape (DC
To make the data free, the data structure is converted from 8 bits to 9 bits. The outline of this conversion is as follows.

For each value of 1-byte 8-bit input data having 256 kinds of values, two kinds of 9-bit data are ID-1.
It is predetermined by the format. These two types of 9-bit data are stored in the CDS (Codeword Digital Su
Data in which the polarity of m) is different from positive or negative. The 8-9 modulation circuit monitors the DSV (Digital Sum Variation) of the 9-bit data output according to the input data, and controls the 9 types of 9-bit data having different CDS values so that this value converges to zero. Select one of the data. Thus, 1
Byte 8-bit input data is converted into DC-free 9-bit data. The 8-9 modulation circuit 1
In 0, the format of the input data of NRZL (Nonreturn to Zero Level) is set to NRZI (Nonreturn to Zero Invers).
The circuit for converting to e) is also included.

The output of the 8-9 modulation circuit 10, that is, the data consisting of the NRZI of the 9-bit configuration, is input to the third multiplexer circuit 11. This multiplexer circuit 11
Forms an inner data blocks DI ₀ -DI adding 4 bytes long fixed synchronization code SYNC _B formed by the synchronization code generating circuit 12 to each data block of ₂₅₅ synchronous blocks BLK ₀ ~BLK _255. The code pattern of the synchronization code SYNC _B is defined in ID-1 format, and it is specified that the pattern recorded on the magnetic tape must also maintain the form of the code pattern.

FIG. 8 shows a map display of the data obtained by the above processing. The output of the third multiplexer circuit 11 is a data array obtained by scanning the maps MAP1 and MAP2 in the horizontal direction, and is as shown in FIG.

The output of the third multiplexer circuit 11 is
The signal is input to the parallel-serial conversion circuit 13. The parallel-to-serial conversion circuit 13 receives a preamble portion PR having a bit-parallel configuration and a synchronization block BLK _0- .
BLK ₂₅₅ converts each data of the postamble part PS into data S _REC of a bit serial configuration.

The serial data S _REC is amplified by a recording amplifier circuit 14 and then supplied as a recording signal to a magnetic head 16 for performing helical scanning on the magnetic tape 15, whereby the magnetic tape 15 has a signal shown in FIG. The recording tracks TR (... TR1, TR2, TR3, TR4,...) Shown in FIG. Thus, the recording system 1 of the data recorder
_Can be recorded by adding an error correction code to desired information data DT _USE based on a Reed-Solomon product code format.

Also, as described above, the recording system 1 of the data recorder
Data DT recorded on the magnetic tape 15 by the
_{The USE} is reproduced by the reproduction system 20 of the data recorder shown in FIG. In the signal processing of the reproduction system 20, the processing completely opposite to that of the recording system 1 is performed. That is, in the reproducing system 20 of this data recorder, the recording tracks TR (... TR 1, TR 2,.
, TR3, TR4,...) Are read out as re-corrected signals _SPB , which are input to the reproduction amplifier circuit 21.

The reproduction amplifier circuit 21 includes an equalizer, a binarization circuit, and the like. The reproduction amplifier circuit 21 binarizes the input reproduction signal S _PB, and converts the binarized signal into a serial / parallel conversion circuit 22 which continues as reproduction digital data DT _PB . Output. Serial-parallel conversion circuit 22 converts the reproduced digital data DT _PB serial format to 9-bit parallel data DT _PR.

The synchronization code detection circuit 23 outputs a 4-byte synchronization code SYN from the flow of the parallel data DT _PR.
Detecting a C _B, identifying the sync block on the basis of this. Here, the parallel data D in the NRZI format is used.
A circuit for converting T _PR to NRZL format is also included.

The output of the synchronization code detection circuit 23 is 8-9
The signal is input to the demodulation circuit 24. The 8-9 demodulation circuit 24 is a circuit for restoring the data converted from 8 bits to 9 bits for the DC-free operation in the recording system to 8 bits again. This circuit is constituted by a ROM (Reed Only Memory), and converts data from 9 bits to 8 bits by a look-up process.

The data restored to the 8-bit data is subjected to processing (derandomization) in the data integration circuit 25, which is the reverse of the processing received in the recording system, ie, the decentralization processing. This integration is achieved by performing an exclusive OR operation on the same predetermined data used for the distribution and the input data of the data integration circuit 25.

The inner code error detection / correction circuit 26 outputs the inner data block DI among the determined synchronization blocks.
_{For 0 to} DI ₂₅₅ , error detection and correction are performed using the 8-byte inner codes RI _{0 to} RI ₂₅₅ added to the respective blocks.

The inner data blocks DI _{0 to} DI _{255 which} have been subjected to the inner code error correction are sent to the identification data detecting circuit 27.
Based on the block identification data ID _B of 1 byte length are added to each block detected by the memory 28 having the same construction as the memory 4 of the recording system shown in FIG. 6, 1 data block is on one line Written. The order of writing is
The order of reading from the memory 4 of the recording system is the same as that of ME.
M1 and MEM2 are alternately arranged in a row unit along the block identification data.

Each memory MEM1 and MEM2 of the memory 28
Is written in the next column direction in the same order as the writing order of the memory 4 of the recording system. As a result, the outer data blocks DO _{0 to} DO having a length of 128 bytes are obtained.
₃₀₆ is obtained again. Outer code error detection and correction circuit 29
Performs error detection and correction on outer data blocks DO _{0 to} DO ₃₀₆ output from the memory 28 using the 10-byte long outer codes RO _{0 to} RO ₃₀₆ added to the respective blocks. Thus, the information data DT _USE recorded on the magnetic tape 15 is reproduced.

[0030]

However, in the reproducing system 20 of the magnetic recording / reproducing apparatus having such a configuration, in the inner code error detecting and correcting circuit 26, the synchronous block B for the memory 28 for the synchronous block BLK in which the error cannot be corrected.
LK writing is controlled to be stopped. For this reason, an error occurs in a portion other than the synchronous block data DT _BLK , and if the error cannot be corrected due to the error, the synchronous block data DT _BLK which is not actually erroneous.
Is not written into the memory, the correct synchronization block data DT _BLK is not sent to the outer code error detection and correction circuit 29, and as a result, error correction becomes impossible even in the outer code error detection and correction circuit 29. Atsuta.

In the inner code error detection and correction circuit 26, when an error is corrected by mistake in a certain synchronous block BLK, and when the identification data ID _BLK of the synchronous block BLK is incorrect, the memory in which the synchronous block BLK is incorrect is corrected. If a correct synchronization block BLK is written in the address and, as a result, the erasure correction is performed in the outer code error detection and correction circuit 29, there is a problem that the erroneous correction is further performed.

Further, the identification data IDBLK has the value "00".
Even if data of all "0" is input due to a dropout or the like on the magnetic tape 15 in the synchronous block _BLK K other than the identification block ID _BLK is stored in the address of the memory 28 corresponding to the value "00". When the outer block error detection and correction circuit 29 performs erasure correction in the same manner as described above in order to write the synchronous block BLK of all "0" as correct data, there is a problem that the erroneous correction is further performed.

To solve such a problem, an error correction circuit 30 including a memory control circuit 31 as shown in FIG.
Is used. The counter 32 is reset to "00" by the block reset BRST, and is incremented for each inner code. After being reset by the block reset, when the block ID detected by the block ID detection circuit 33 is other than "00" and a code determined to be correct in the inner sequence comes in, the difference between the counter 32 and the block ID is determined. Obtained by the subtraction circuit 34, the counter 3
Data is written to the memory 28 using the output of 2 as a memory address.

After determining the memory address, the counter 32 loads the block ID at that time. Thereafter, that is, after the offset is obtained, the difference between the block ID and the output of the counter incremented by one for each block is detected, and the difference is judged by the judgment circuit 36. If the difference is correct, the block ID is loaded into the counter 32. Then, the sum of the loaded value (that is, the block ID) and the offset is obtained by the adding circuit 38, and the data is written as the address of the memory 28.

Thereafter, this operation is continued, and it is determined whether or not the output of the counter 32 and the block ID are the final code by the final address detection circuit 35. If the final code is determined, the writing of data to the memory 28 is stopped.

When data is read from the memory 28, the data is read using the offset as the first address and sent to the outer code error detection and correction circuit 29. However, if the offset is erroneously obtained at this time, the memory address is destroyed and correct data cannot be sent to the outer code error detection and correction circuit 29.

In practice, in this error correction circuit, in the output of the counter and the inner sequence, the difference between the block ID of the code reproduced first and the block ID determined not to be "00" but determined to be correct is determined as an offset and demodulated. The address of the write memory is obtained when
The continuity of the block ID and the continuity of the block ID are determined by the determination circuit 36, and the write address of the code is controlled. When reading, the read address of the outer sequence is determined from the obtained offset.

However, at this time, once the offset is obtained, the offset is loaded into the counter 32, and
Because the continuity from that point is checked and the read address is determined by the offset, if the offset is incorrect, the continuity judgment on the writing side is all incorrect and an error flag is set. Making that data an error.

On the read side, since the read address is different, the data arrangement is destroyed. This is because, once the offset is erroneously obtained, demodulation is performed using the offset even if the offset is logically suspect. In addition, if the offset is incorrect, all the data forming the product code become errors.

The present invention has been made in view of the above points, and it is an object of the present invention to propose an error correction circuit which can correctly grasp an offset and further improve error correction efficiency and accuracy.

[0041]

According to the present invention, there is provided an error correction method for receiving transmission data transmitted by adding an error correction code to information data based on a product code format, and correcting the error. A circuit 40 for detecting and correcting an inner code error in the transmission data;
Is written in the memory 28 in accordance with the address information obtained from the counter 32 operating in the block data unit from the block data unit BLK. The memory offset information S _OFF is obtained based on the data ID _BLK and the address information, and the continuity of the memory offset information S _OFF is determined.
If determined to be correct, memory offset information S _OFF
Is sent, and if in doubt, the memory offset information S _OFF
The memory 28 is read out according to the outer code sequence using the memory control means 41 for re-determining the value and the memory offset information S _OFF sent from the memory control means 41, and the outer code error is detected, corrected and transmitted. An outer code error detection and correction means 29 is provided.

[0042]

[0043]

The inner code error correction data transmitted from the inner code error detection / correction means in predetermined block data BLK units is
The data is written to the memory 28 in accordance with the address information obtained from the counter 32, and the memory offset information S based on the identification data ID _BLK and the address information contained in the block data in which no error exists or the error can be corrected.
_OFF and the continuity of the memory offset information S _OFF are determined. If it is determined that the information is correct, the memory offset information S _OFF is sent out. If in doubt, the memory offset information S _OFF is obtained again and the result obtained is obtained. By reading the memory 28 in accordance with the outer code sequence using the memory offset information S _OFF , even if an error occurs in the identification data ID _BLK , the block data can be read by the outer code error detection and correction means 29. And the error detection accuracy and error correction capability can be improved.

[0044]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

In the present invention, in FIG. 1 where parts corresponding to those in FIG. 10 are denoted by the same reference numerals, reference numeral 40 denotes an error correction circuit as a whole according to the present invention. And a switch circuit 42 and first and second determination circuits 43 and 44.

That is, according to the present invention, if the offset once obtained is determined to be suspicious at the time of demodulation thereafter, the offset is found again. Therefore, even if the offset is erroneously obtained, the offset is checked, and only the offset that has passed through the check is used as the regular offset.

Actually, the first judging circuit 43 judges whether or not the offset is within a predetermined range, similarly to the conventional judging circuit. When the value of the offset deviates from the predetermined range, the switch 42 is turned on. Is turned off so that the offset is not supplied to the offset detection circuit 45 until the offset value reaches a correct value.

The second judging circuit 44 monitors the difference between the output of the counter 32 and the block ID. If an offset is erroneously obtained, the offset is loaded into the counter 32. When the block IDs are successively input, the difference between the counter 32 and the block ID also holds a certain value.

Therefore, if this deviation continues for some blocks, the offset detection circuit 45 is cleared, and
Ask for the offset again. However, if it is determined by the second judging circuit 44 that the offset obtained again is not correct, the offset is obtained again, and this operation is repeated, and the remaining memory is finally set as an offset to the first memory on the read side. Determined as an address.

According to the above arrangement, if the offset once obtained is determined to be suspicious at the time of demodulation thereafter,
The offset is found again, and even if the offset is found by mistake, the offset is checked, and only the offset that has passed through the check is used as a regular offset, so that the offset can be correctly grasped and corrected. An error correction circuit that can further improve efficiency and accuracy can be realized.

In the embodiment described above, the present invention is applied to I
The present invention is applied to the reproduction system of the D-1 format data recorder. However, the present invention is not limited to this, and various types of information can be used as long as it decodes data with a parity code in a product code format for error correction. It can be widely applied to processing equipment.

[0052]

As described above, according to the present invention, the inner code correction data transmitted from the inner code error detection and correction means in a predetermined block data unit is written into the memory in accordance with the address information obtained from the counter. The memory offset information is obtained based on the identification data and the address information included in the block data in which no error exists or the error can be corrected, and the continuity of the memory offset information is determined. When it is determined that the memory offset information is correct, the memory offset is determined. Send out the information and, if in doubt, reclaim the memory offset information,
By reading the memory according to the outer code sequence using the memory offset information obtained as a result, even if an error occurs in the identification data, the block data is transmitted to the outer code error detection and correction means even if an error occurs in the identification data. It can be transmitted, and the error detection accuracy and error correction capability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction circuit according to the present invention.

FIG. 2 is a schematic diagram for explaining a recording pattern of an ID-1 format;

FIG. 3 is a schematic diagram showing the contents of a data track in an ID-1 format.

FIG. 4 is a block diagram showing a recording system of a data recorder of ID-1 format.

FIG. 5 is a schematic diagram showing an outer data block in a recording system of the data recorder.

FIG. 6 is a schematic diagram illustrating a data array in a memory in a recording system of the data recorder.

FIG. 7 is a schematic diagram showing an inner data block in a recording system of the data recorder.

FIG. 8 is a schematic diagram showing data in a map display.

FIG. 9 is a block diagram showing a reproduction system of an ID-1 format data recorder.

FIG. 10 is a block diagram showing a conventional error correction circuit.

[Explanation of symbols]

1 ... recording system, 2 ... outer code generation circuit, 3, 7, 11 ...
... MUX, 4 ... Memory, 5 ... Identification data generation circuit,
6 ... Inner code generation circuit, 8 ... Preamble section postamble section generation circuit, 9 ... Data distribution circuit, 10 ... 8
-9 modulation circuit, 12 synchronization code generation circuit, 13 ...
Parallel / serial conversion circuit, 14 ... recording amplification circuit,
15 ... magnetic tape, 16 ... magnetic head, 20 ... reproduction system, 21 ... reproduction amplification circuit, 22 ... serial / parallel conversion circuit, 23 ... synchronization code detection circuit, 24 ... 8
-9 demodulation circuit, 25 ... data integration circuit, 26 ... inner code error detection and correction circuit, 27 ... identification data detection circuit,
28: memory, 29: outer code error detection and correction circuit.

Continuation of front page (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/18 G06F 11/10 H03M 13/00

Claims (1)

(57) [Claims] (1)Based on product code format for information data
Transmission data transmitted with an error correction code
Error correction circuit, Detect and correct inner code errors in the transmission data
Inner code error detection and correction means, From the inner code error detection and correction means in block data units.
The transmitted inner code correction data is expressed in the above block data unit.
According to the address information obtained from the counter operating on
Write to memory, no errors or error correction
Possible identification data contained in the above block data and the above
Find memory offset information based on address information
And the continuity of the memory offset information is determined.
If determined to be correct, send the above memory offset information.
And, if in doubt, ask for the above memory offset information
Memory control means; The memory offset transmitted from the memory control means.
The above memory is read out according to the outer code sequence using the
The outer code that detects and corrects the outer code error and sends it out.
Signal error detection and correction means Error correction characterized by comprising
Positive circuit.