JP3262470B2 - Semiconductor substrate and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly to a method for manufacturing a substrate having a single crystal semiconductor layer on a light-transmitting insulator substrate. More specifically, the present invention relates to a semiconductor substrate in which a single crystal semiconductor for forming an element by using an epitaxial growth method or an ion implantation method is formed on a light-transmitting insulator substrate such as glass in the future, and a method for manufacturing the same.

[0002]

2. Description of the Related Art The formation of a single-crystal silicon semiconductor layer on an insulator is widely known as Silicon on Insulator (SOI) technology, and has many advantages that cannot be achieved with a bulk silicon substrate used to fabricate ordinary silicon integrated circuits. Since this substrate has a lot of researches.

If a single crystal film grown on an insulating film can be used as a substrate material for a device, it is very convenient in terms of device structure. 1) The parasitic (floating) capacitance due to the substrate is reduced. 2) It is resistant to radiation. 3) The high performance (high speed) is achieved because the aim of the latch-up free CMOS is aimed at.
C) Aim for a highly reliable device. For this reason, SOI devices have attracted attention.

Among the recently reported SOI formation methods, a so-called “bonded SOI” is particularly excellent in quality.
There is. This is because the mirror surfaces of two wafers, at least one of which has an insulating film formed by oxidation or the like, are brought into close contact with each other, heat treatment is performed to strengthen the bond at the contact interface, and then the substrate is removed from either one side. This is a technique in which a silicon single crystal thin film having an arbitrary thickness is left on an insulating film by polishing or etching. The most important in this technique is the step of thinning the silicon layer.
This is because if the silicon layer is not thinned, S
This is because the advantage of OI cannot be used.

However, in order to reduce the thickness of this silicon layer, a silicon substrate having a thickness of several hundred μm is usually uniformly coated with several μm.
It must be polished or etched to a thickness of m or less than 1 μm. These controls and uniformity of the substrate are extremely difficult techniques. Because of the difficulty of controlling the film thickness,
This “bonded SOI” has the potential to provide the highest quality single crystal thin film among SOI technologies, but has not yet been produced.

There is another important problem in bonding SOI. That is the difference in the coefficient of thermal expansion between the insulator substrate and the silicon substrate. When a silicon substrate is used on the substrate side serving as a support (that is, bonding between silicon substrates), this difference in the coefficient of thermal expansion hardly causes a problem.
However, when two substrates having greatly different coefficients of thermal expansion are bonded to each other and a temperature change occurs, a stress is generated due to a difference in the coefficient of thermal expansion between the two substrates.

In practice, when an insulating substrate other than silicon, such as glass, is used on the substrate side serving as a support, after bonding two substrates, the bonding at the interface is strengthened. During the heat treatment process at about 1000 ° C., the substrates may warp, break, or separate from each other due to the difference in thermal expansion coefficient between the two substrates. There is an example in which a material with a thermal expansion coefficient close to that of silicon is synthesized and used for the support substrate.
Such materials have poor heat resistance as far as they are known,
It cannot withstand the heat treatment for strengthening the bonding or the process temperature for forming the device.

[0008] To solve these problems, "bonded SOI"
Abe et al. Reported an example of a `` substrate '' (Extende
d Abstracts of the 1992 International Conference o
n SOLID STATE DEVICES AND MATIRIALS, 1992 Tsukuba,
pp. 437-439. or JP-A-4-286310).

In this method, the thickness is relatively thin (300 μm).
After the silicon substrate and the quartz substrate are bonded to each other, first heat treatment at about 300 ° C. is performed so that the bonded substrate does not peel or break, and then the silicon substrate is thinned to about 150 μm by etching alone. Then, annealing at about 450 ° C. is performed as a second heat treatment, and after obtaining a bonding force that can withstand the shear stress of surface grinding, grinding is performed to several μm with a grinder. Thereafter, the silicon substrate is thinned by precision polishing.

However, in this method, since a heat treatment is essential, a thin silicon substrate having a thickness of about 300 μm must be used in consideration of thermal stress. For this reason, accidents such as cracking of the substrate during work such as sticking and transporting the substrate are likely to occur, so that the work must be carefully performed. Furthermore, in order to perform heat treatment at a higher temperature, the substrate is ground thinly,
Thereafter, a cycle of performing heat treatment must be repeated. For these reasons, the “bonded SOI substrate” has a disadvantage that the manufacturing speed cannot be increased.

More specifically, the thickness of the semiconductor substrate to be attached is usually about 500 μm for a 4-inch diameter silicon substrate and 600 μm for a 5-6 inch diameter in order to maintain mechanical strength.
About μm is required. Further, when the diameter is 8 inches, a thick silicon substrate having a thickness of about 800 μm is required.
When a thin substrate having a thickness of about 0 μm is used, it is extremely difficult to handle the first attaching step.

There are also other disadvantages. This is a problem of peeling due to shear stress applied between the insulator substrate and the semiconductor substrate. Each time the silicon substrate is ground and thinned, a large shear stress is applied to the bonding interface between the support substrate and the silicon substrate. Actually, since the silicon substrate is ground or polished until it becomes a thin film of several μm, a considerably large shear stress is applied to the bonding interface. Further, at the bonding surface between the two substrates, the bonding at the bonding interface becomes weaker each time the substrate is ground. In order to solve this problem, there is a method of repeating thinning by grinding the substrate and high-temperature heat treatment so that the bonding force at the interface is not weakened. However, this method requires a long process and is not suitable for mass production.

Another disadvantage is that a single-crystal silicon thin film is formed by polishing, so that a special apparatus and very precise control are required to obtain uniform film thickness.

In order to manufacture an SOI substrate by another method, a semiconductor film may be directly deposited on an insulator substrate.
The semiconductor thin film does not crystallize well on the insulator substrate, and it is impossible to form a single crystal semiconductor thin film.

[0015]

As described above, in the conventional "bonded SOI substrate", a sufficient bonding force cannot be obtained between the insulator substrate and the silicon substrate unless heat treatment is performed. However, on the other hand, as described above, a silicon substrate and a transparent substrate having a different coefficient of thermal expansion are directly bonded,
When the heat treatment is performed, the above-described problems of cracking and warping of the substrate appear. In order to solve such a problem, conventionally, the heat treatment temperature has been delicately adjusted under the condition that a bonding force that can withstand a shear stress is maintained and a problem of cracking or warping does not occur. However, this adjustment is difficult because it requires extremely fine adjustment. In practice, complicated steps such as performing heat treatment in multiple stages from a low temperature to a high temperature must be performed.
For this reason, this method cannot produce an SOI substrate that can be mass-produced. In order to solve such a problem, it is desired to obtain an SOI substrate by polishing without a heat treatment step. Furthermore, even with other methods, a technique capable of providing an SOI substrate sufficient for manufacturing a high-performance electronic element with high productivity has not yet been achieved.

On the other hand, when a single-crystal semiconductor substrate is manufactured by a conventional method for forming a deposited film, not a small number of stacking faults may occur in the single-crystal deposited film. In this case, stacking faults increase as the deposited film grows. FIG. 10 illustrates this. 1000 is a semiconductor substrate such as silicon; 1002 is an epitaxial growth layer;
009 is a stacking fault. There may be a point defect, dust, oxide residue, or the like on the surface of the substrate 1000, which causes a stacking fault. As the semiconductor single crystal layer 1002 is epitaxially grown, a stacking fault grows divergently and grows in the epitaxial layer due to a point defect, dust, a residue of an oxide film, and the like. Therefore, the epitaxial layer 100
On the surface of No. 2, stacking faults greatly spread.

[0017]

Accordingly, in the present invention, a single-crystal silicon substrate having a significantly different coefficient of thermal expansion is bonded to a transparent insulator substrate to form a single substrate. It is an object of the present invention to manufacture a high-performance, high-performance SOI substrate by a simplified method that is performed only once even if a process is not performed or a heat treatment is performed.

Another object of the present invention is to produce a semiconductor substrate in which even if stacking faults occur in single crystal silicon for forming a device, the stacking faults do not adversely affect the device.

The present inventors have made intensive efforts in view of the above problems and disadvantages, and have obtained the following findings. That is, a single-crystal silicon layer is epitaxially grown on a porous silicon surface of a silicon substrate having a porous surface layer.
The silicon substrate portion is removed by wet etching with an etching solution, followed by selective etching of the porous portion, without performing heat treatment to minimize the influence of stress. If a crystalline silicon thin film is formed over an insulator substrate, an SOI substrate that solves the above problems can be manufactured.

Since wet etching of the silicon substrate takes time, instead of etching, a portion of the silicon substrate is first ground by grinding until the silicon substrate is still thick enough and the shear stress at the interface between the substrates is not a problem. The above problem can also be solved by a method of removing the silicon substrate portion removed by grinding after the removal by wet etching with an etching solution.
An I substrate can be manufactured.

Furthermore, a part of the silicon substrate portion is removed by grinding, and then only a single heat treatment is performed on the whole to strengthen the bonding between the substrates, and the silicon substrate portion remaining in the first grinding is removed by grinding. The method can also manufacture an SOI substrate that solves the above problems.

Further, by using this method, the conventional semiconductor single crystal deposited film is epitaxially grown, and as the deposited film becomes thicker, the stacking faults which have spread greatly on the surface of the semiconductor deposited film and grown and grown are directed to the opposing bonded substrate side. Can be transcribed. Therefore, only a small area stacking fault in the initial stage of the growth of stacking faults appears on the surface of the semiconductor substrate which is important for fabricating an element in the future. This is not limited to the fabrication of an SOI substrate, and the same effect can be obtained with a semiconductor substrate that forms an epitaxial growth layer on a semiconductor substrate.

Hereinafter, embodiments of the present invention will be described in detail. A first aspect of the method of the present invention is a method for manufacturing a semiconductor substrate, which comprises sequentially performing the following steps.

A) forming a porous single-crystal semiconductor layer on the non-porous single-crystal semiconductor region by anodizing a surface layer on one surface of the single-crystal semiconductor substrate; epitaxially growing a non-porous monocrystalline semiconductor layer on a single crystal semiconductor layer, c) wherein the single crystal semiconductor substrate insulating substrate nonporous
A step of laminating the non-porous single-crystal semiconductor regions after the superposing so that the porous single-crystal semiconductor layers are positioned inside, and substantially removing the non-porous single-crystal semiconductor regions. Grinding the non-porous single-crystal semiconductor region, e) removing the non-porous single-crystal semiconductor region and exposing the porous single-crystal semiconductor layer, the non-porous single crystal remaining in the step d) Etching a semiconductor region; f) selectively etching the porous single crystal semiconductor layer to remove the porous single crystal semiconductor layer.

At this time, after the non-porous single-crystal semiconductor region is ground and a part of the non-porous single-crystal semiconductor region is removed, the whole is subjected to a heat treatment so that the non-porous single-crystal semiconductor layer and the insulator substrate are removed. May be added. Further, at this time, the non-porous single-crystal semiconductor layer remaining in the grinding step is etched to remove all of the non-porous single-crystal semiconductor layer and expose the porous single-crystal semiconductor layer. It is desirable to carry out the reaction in any of a solution, an organic alkali solution, and an acid solution containing hydrofluoric acid and nitric acid. Further, at this time, the step of grinding the non-porous single-crystal semiconductor region to remove a part of the non-porous single-crystal semiconductor region is preferably performed while leaving the non-porous single-crystal semiconductor region at a thickness of 100 μm or more. desirable.

A second aspect of the method of the present invention is a method for manufacturing a semiconductor substrate, which comprises sequentially performing the following steps.

A) forming a porous single-crystal semiconductor layer on the non-porous single-crystal semiconductor region by anodizing a surface layer on one surface of the single-crystal semiconductor substrate; epitaxially growing a non-porous monocrystalline semiconductor layer on a single crystal semiconductor layer, c) wherein the single crystal semiconductor substrate insulating substrate nonporous
A step of laminating the porous single crystal semiconductor layers so that the porous single crystal semiconductor layers are positioned inside, and then bonding the two without substantially performing heat treatment; e) removing the non-porous single crystal semiconductor region and removing the porous single crystal semiconductor Etching the non-porous single-crystal semiconductor region to expose a layer; and f) selectively etching the porous single-crystal semiconductor layer to remove the porous single-crystal semiconductor layer.

At this time, the step of etching the non-porous single-crystal semiconductor region to remove all of the non-porous single-crystal semiconductor region and exposing the porous single-crystal semiconductor layer includes the steps of: It is desirable to carry out the reaction in any of a solution, an acid solution containing hydrofluoric acid and nitric acid.

A third aspect of the method of the present invention is a method for manufacturing a semiconductor substrate, which comprises sequentially performing the following steps.

A) forming a porous single-crystal semiconductor layer on the non-porous single-crystal semiconductor region by anodizing a surface layer on one surface of the single-crystal semiconductor substrate; epitaxially growing a non-porous monocrystalline semiconductor layer on a single crystal semiconductor layer, c) wherein the single crystal semiconductor substrate insulating substrate nonporous
A step of laminating the non-porous single-crystal semiconductor regions after the superposing so that the porous single-crystal semiconductor layers are positioned inside, and substantially removing the non-porous single-crystal semiconductor regions. Grinding the non-porous single-crystal semiconductor region; d2) heat-treating the whole to strengthen the bond between the non-porous single-crystal semiconductor layer and the insulator substrate; d3) the non-porous single crystal Grinding the non-porous single-crystal semiconductor region remaining in step d) to remove the semiconductor region and expose the porous single-crystal semiconductor layer; f) removing the porous single-crystal semiconductor layer Selectively etching the porous single crystal semiconductor layer.

At this time, the step of grinding the non-porous single-crystal semiconductor region to remove a part of the non-porous single-crystal semiconductor region may include removing the non-porous single-crystal semiconductor region to a thickness of 10%.
It is desirable to carry out the process while leaving 0 μm or more.

Further, the method of manufacturing a semiconductor substrate according to the present invention comprises:
Non-porous monocrystalline step of preparing a first substrate having a non-porous monocrystalline semiconductor layer through the porous monocrystalline semiconductor layer on a semiconductor region on the a first substrate and a second substrate an insulator The substrate is substantially non-porous without heat treatment.
A bonding step of bonding the single crystal semiconductor layer so that the single crystal semiconductor layer is positioned inside, a grinding step of grinding a part of the non-porous single crystal semiconductor region, the grinding of a part of the non-porous single crystal semiconductor region; A step of heat-treating the entire first substrate and the second substrate, and a step of selectively etching the porous single-crystal semiconductor layer to remove the porous single-crystal semiconductor layer. Features. Also,
In the method of the present invention, through the first to third aspects,
Before the removal of the non-porous single-crystal semiconductor region, a step of applying pressure to the adhered substrate may be added. Further, a step of oxidizing the surface of the non-porous single-crystal semiconductor layer and bringing the surface of the surface oxide layer into close contact with the insulator substrate may be added. Still further, the selective etching of the porous single crystal semiconductor layer is performed with a mixed etching solution of hydrofluoric acid and hydrogen peroxide, and the insulating substrate is performed with a light-transmitting insulating substrate mainly composed of SiO 2. It is desirable. Further, the single crystal semiconductor substrate preferably contains silicon as a main component.

The present invention also includes a semiconductor substrate. That is, the substrate of the present invention is a semiconductor substrate in which a single crystal semiconductor layer is provided over a substrate, and a region where stacking faults in the single crystal semiconductor layer are spread is not a surface of the single crystal semiconductor substrate,
A defect region in the single crystal semiconductor layer near the bonding surface with the substrate and having a small defect region in the initial stage of the growth of the stacking fault is located on the single crystal semiconductor surface. At this time, the substrate may be a light-transmitting insulator substrate containing SiO ₂ as a main component. Further, the single crystal semiconductor substrate preferably contains silicon as a main component. Further, the substrate may be a semiconductor substrate, particularly a single crystal silicon substrate.

In the first embodiment of the present invention, in which the single-crystal silicon portion is first partially removed by grinding, and then the remaining single-crystal silicon portion is entirely removed by etching, the first grinding is usually performed for 500 minutes. This is because it takes a considerable time to reduce the thickness of the substrate having a thickness of ６００600 μm or more to several tens μm or several μm only by wet etching. In addition, grinding only a part of the silicon substrate instead of removing only all the silicon substrate part is because grinding exerts a considerable shear stress on the bonding interface, and if the substrate is cut beyond a certain amount, the interface will be removed. This is because a large force is applied and peeling or destruction occurs. Therefore, the minimum remaining thickness of the silicon substrate is about 100 μm, depending on the flatness of the substrate and the cleaning method. Left thickness 100μ
Up to m, Van der without heat treatment after bonding
It is possible to withstand grinding only with Waals force.
Then, when the remaining thickness of the silicon substrate reaches 100 μm, it is necessary to switch to etching with a solution so that no stress is applied thereafter. The remaining thickness is 100 μm
When the heat treatment is performed once, when the final porous silicon layer is selectively wet-etched,
It is also known that a high yield can be obtained stably.

The reason why the single-crystal silicon substrate is removed only by wet etching in the second embodiment of the method of the present invention is to eliminate a heat treatment step which is indispensable when the method is performed only by grinding. Here, since no grinding step is required, the number of processes can be reduced, and polishing equipment and abrasives are not required.

The third embodiment of the present invention, in which all the silicon substrate portions are divided into two portions instead of being removed at once, is that grinding exerts a considerable shear stress on the bonding interface and a certain constant This is because if the substrate is cut in excess of the amount, a large force is applied to the interface to cause peeling or destruction. In other words, it is important that the first grinding is completed when the shear stress applied to the interface is still small. At this time, even if the thinned silicon substrate is subjected to a certain degree of heat treatment, since the applied thermal stress is small, peeling of the bonded surfaces does not occur.

In practicing the present invention, two other important physical effects of porous silicon are utilized. One is the etching characteristics of porous silicon. Normally, silicon is hardly wet-etched with a hydrofluoric acid solution, but by making the silicon porous, this silicon is largely wet-etched with a hydrofluoric acid solution. In particular, when a mixed etching solution of hydrofluoric acid and hydrogen peroxide solution is used in this hydrofluoric acid solution, an etching rate of about 10 times as high as that of a nonporous porous material can be obtained. Therefore, it is possible to perform selective etching that leaves even a thin silicon layer of about 1 μm with good controllability.

Another effect is epitaxial growth characteristics. Porous silicon has a single crystal structure as its crystal structure, and has a thickness of several tens to several hundreds of square meters from the surface to the inside.
The holes having a large diameter exist at a high density. The epitaxial layer grown on this surface has the property that the same crystallinity as that of the epitaxial layer on the non-porous single crystal substrate can be obtained. However, as a feature of epitaxial growth on porous material, stacking faults may be generated from the growth interface although the density is very low.

From the above physical characteristics, it becomes possible to use a single crystal thin film equivalent to an epitaxial layer on a single crystal silicon substrate having high reliability as an active layer, and the conventional SO
An SOI substrate having better crystallinity than an I substrate can be provided. Since the stacking faults generated during the epitaxial growth are transferred to the other substrate by bonding, the stacking faults observed in the resulting silicon film of the SOI substrate appear to be in the opposite direction to the normal.

Further, according to the present invention, it is possible to extremely reduce the probability of causing “peeling” during etching or grinding by applying pressure to the adhered substrates after bonding the two substrates at room temperature. became.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS.

(FIG. 1 a) A single-crystal silicon substrate 100 is anodized to form porous silicon 101. At this time, the thickness for making the substrate porous may be several μm to several tens μm on one side surface layer of the substrate. Alternatively, the entire substrate may be anodized. A method for forming porous silicon will be described with reference to FIG. First, a P-type single crystal silicon substrate 600 is prepared as a substrate. Although it is not impossible even with an N-type, in that case, it is necessary to limit the substrate to a low-resistance substrate or to irradiate light to the substrate surface to promote generation of holes. The substrate 600 is set in an apparatus as shown in FIG. That is, one side of the substrate is a hydrofluoric acid-based solution 604.
, A negative electrode 606 is provided on the solution side, and the opposite side is in contact with the positive metal electrode 605. As shown in FIG. 6b, the positive electrode side 605 'may also take the potential via the solution 604'. In any case, porosity occurs from the negative electrode side in contact with the hydrofluoric acid-based solution. As the hydrofluoric acid-based solution 604, generally, concentrated hydrofluoric acid (49% H
Use F). Diluting with pure water (H ₂ O) is not preferable because etching occurs at a certain concentration, depending on the value of the current flowing. In addition, bubbles may be generated from the surface of the substrate 600 during anodization, and alcohol may be added as a surfactant for the purpose of efficiently removing the bubbles. Methanol, ethanol, as alcohol
Propanol, isopropanol and the like are used. Alternatively, anodizing may be performed while stirring the solution using a stirrer instead of the surfactant. For the negative electrode 606, a material that is not eroded by the hydrofluoric acid solution, for example, gold (Au), platinum (Pt), or the like is used. The material of the positive electrode 605 may be a commonly used metal material, but the hydrofluoric acid-based solution 604 reaches the positive electrode 605 when the anodization is performed on all the substrates 600. It is preferable to coat a metal film resistant to hydrofluoric acid solution. The current value for anodizing is up to several hundred m.
A / cm ² , and the minimum value may not be zero. This value is determined within a range where good quality epitaxial growth can be performed on the surface of the porous silicon. Usually, when the current value is large, the rate of anodization increases, and at the same time, the density of the porous silicon layer decreases. That is, the volume occupied by the holes increases. This changes the conditions for epitaxial growth.

(FIG. 1b) A non-porous single-crystal silicon layer 102 is formed on the porous layer 101 formed as described above.
Is epitaxially grown. Epitaxial growth is performed by general thermal CVD, low pressure CVD, plasma CVD, molecular beam epitaxy, sputtering, or the like. The growing film thickness is S
The value may be the same as the design value of the OI layer, but is preferably 2 μm.
m or less is good. This is because when a single-crystal silicon film having a thickness of 2 μm or more is in close contact with an insulating substrate containing SiO ₂ as a main component, if this is heat-treated in a device process, the difference in the thermal expansion coefficient between the two materials will result in a bonding interface. This is because a large stress is generated, which causes breakage of the silicon film, warpage of the substrate, or separation at the interface. The film thickness is 2
If it is less than μm, the stress is relatively small,
Peeling, warping, etc. are unlikely to occur. More preferably, 0.5
μm or less. This is because if the film thickness is 0.5 μm or more, slip lines are likely to be generated in the crystal in a minute region even if peeling, destruction, or the like does not occur during subsequent annealing.

It is preferable that the surface of the epitaxial layer 102 is thermally oxidized. This is because if an epitaxial layer of single crystal silicon is left deposited, the number of dangling bonds of atoms at the interface increases. Therefore, when the substrate is directly bonded to the supporting substrate in the next step performed in the air, impurities are easily segregated at the bonding interface. This segregation of impurities becomes a factor that destabilizes the characteristics of the thin film device.

In the epitaxial layer 102, a stacking fault 109 may be generated from the growth interface.

(FIG. 1c) The grown epitaxial surface or oxidized epitaxial surface is bonded to an insulating substrate 110 mainly composed of SiO ₂ as a supporting substrate. This bonding is performed after both substrates are washed with a mixed solution of hydrochloric acid and a hydrogen peroxide solution or a mixed solution of sulfuric acid and a hydrogen peroxide solution. That is, both surfaces of the substrate can be treated to be hydrophilic by this washing, and the Van der Waals binding force increases via water at the bonding interface. Even if the substrate has been subjected to hydrophobic cleaning with a hydrofluoric acid solution or the like, the bonding can be sufficiently performed if the bonding surface has good flatness. Here, the insulating substrate 110 can be made of almost any ceramics in general, and is selected from fused quartz, synthetic quartz, high melting point glass, and the like, especially when importance is placed on optical transparency.

In the case of a general method, a heat treatment at about 1000 ° C. is then performed, but this is not performed in the present invention. In order to strengthen the bonding of the bonded substrates, the substrate may be pressurized here. The pressure is completely arbitrary, for example, 5
When a pressure of several tons to several tens of tons is applied to the entire surface of the inch substrate,
The probability that the substrate will peel off during the etching or polishing process is significantly reduced. The time for pressurizing may be about several minutes to one hour.

(FIG. 1d) Next, the epitaxial growth layer 1
02, the silicon substrate portion 100 and the porous portion 10
1 is selectively removed. First, the silicon substrate portion is removed in two stages of grinding and etching. The first grinding is preferably completed at a position where the remaining silicon substrate thickness is at least 100 μm, preferably about 150 μm. Next, the remaining silicon substrate is made of potassium hydroxide (KO).
H), etching with an alkaline solution such as aqueous ammonia or an organic alkaline solution such as trimethylammonium. This etching is effectively performed in a warm solution. Alkali-based solutions are often used for supporting substrates.
Since almost no O ₂ component is etched, only the silicon portion can be selectively etched. Also, hydrofluoric acid and nitric acid,
Alternatively, it can be removed by etching with a mixed solution obtained by adding acetic acid or the like thereto. However, since the hydrofluoric-nitric acid-based etchant may slightly etch the support substrate, it is better to avoid using it for a long time. If a heat treatment at about 300 ° C. is performed before the etching after the grinding, the occurrence of defective products such as film peeling in a later step is reduced. The temperature of the heat treatment depends on the material of the insulating substrate, the diameter and thickness of the substrate, the surface properties,
It depends on the thickness of the remaining silicon substrate. For example, when a standard 5-inch quartz substrate having a thickness of 625 μm is bonded to a silicon substrate having the same diameter, the remaining silicon thickness is 1 mm.
Withstands heat treatment at about 300 ° C. at 50 μm. If the remaining silicon thickness is 100 μm, it can withstand heat of about 350 to 400 ° C.
Exceeding this temperature causes peeling or destruction due to stress.

The entire silicon substrate portion 100 is etched, and the etching is terminated when the porous portion 101 is exposed. The subsequent porous portion 101 is selectively etched in a hydrofluoric acid solution. The non-porous single crystal epitaxially grown portion 102 hardly reacts with hydrofluoric acid and remains as a thin film. Of course, since the supporting substrate 110 contains SiO ₂ as a main component and easily reacts with a hydrofluoric acid-based solution, it is not preferable to immerse the substrate in a hydrofluoric acid solution for a long time, but the porous silicon layer is thin. If so, you don't have to worry about it because it doesn't take much time to etch it. If the support substrate
If it is not desired to etch even a small amount of 110, a silicon nitride film or another substance which does not easily react with hydrofluoric acid may be deposited on the surface opposite to the bonding surface by CVD or the like in advance.
Alternatively, if the porous portion 101 is thinned to some extent with an alkaline solution, an organic alkali solution, or a hydrofluoric-nitric acid solution before dipping the substrate in the etching solution, the time required for selective etching of the epitaxial layer and the porous layer is reduced. The support substrate does not react so much.

The hydrofluoric acid solution used for selective etching of the epitaxial film 102 and the porous layer 101 is a mixture of hydrofluoric acid and a hydrogen peroxide solution (H ₂ O ₂ ). Selective etching of porous silicon is possible with hydrofluoric acid and nitric acid or a mixed solution of acetic acid and acetic acid.However, in this case, the selectivity is not so high, and the single-crystal silicon thin film to be left is slightly etched. Therefore, it is necessary to precisely control time and the like.

By performing the above steps, a single-crystal silicon thin film can be obtained on an insulator substrate. If a stacking fault 109 occurs in the growth layer during epitaxial growth on porous silicon, the stacking fault will be present on the insulator substrate 110 in a direction opposite to the normal direction by bonding. After that, when moving to the device fabrication process, 800
It is preferable to carry out a heat treatment at a temperature of at least about ° C. Alternatively, there is no problem even if a thermal step (oxidation or the like) of the device process replaces this.

The first embodiment of the present invention is the same as the above-described second embodiment of the present invention, except that all the steps of removing the non-porous silicon substrate are performed by etching.

The third embodiment of the present invention is the same as the above-described embodiment of the present invention except that the step of removing the non-porous silicon substrate is performed by grinding divided into two times, and after the first removal, a heat treatment step is included. Is similar to the second embodiment.

According to the first aspect of the method of the present invention, the single crystal silicon portion is first partially removed by grinding while the substrate interface shear stress can be endured, and the single crystal silicon portion becomes sufficiently thin. When the danger of peeling is reached, the removal of the single crystal silicon portion is switched to wet etching, so that there is an effect that an SOI substrate can be manufactured at high speed without performing heat treatment.

According to the second aspect of the method of the present invention, since the single crystal silicon substrate is removed only by wet etching, the heat treatment step which is indispensable when only the grinding method is used can be eliminated. The number of processes is reduced as compared with the first embodiment. Therefore, there is an effect that it is not necessary to prepare a lot of equipment and materials when performing the process.

In the third embodiment of the method of the present invention, the silicon substrate portion is not removed all at once, but is divided into two portions, so that the silicon substrate portion is removed only by performing one heat treatment in the meantime. can do. Therefore, there is no need for a step of performing wet etching of the non-porous silicon substrate portion, so that there is an effect that the SOI substrate can be manufactured at high speed.

[0057]

【Example】

(Embodiment 1) The first embodiment of the present invention will be described in detail with reference to FIGS.

(FIG. 1a) A 5-inch P-type (100) single crystal silicon substrate having a thickness of 625 microns (0.1
.About.0.2 .OMEGA.cm), which was set in an apparatus as shown in FIG.
The surface of No. 0 was made porous silicon 101 by 20 μm.
At this time, the solution 604 was a 49% HF solution, and the current density was 100 mA / cm 2. At this time, the rate of making porous is 8.4 μm / min. And a porous layer having a thickness of 20 μm was obtained in about 2.5 minutes.

(FIG. 1B) A single-crystal silicon layer 102 is formed on the porous silicon 101 by a CVD method to a thickness of 0.5 μm.
m epitaxial growth. The deposition conditions are as follows.

Gas used: SiH ₄ / H ₂ gas flow rate: 0.42 / 140 (l / min) Temperature: 750 ° C. Pressure: 80 Torr Growth rate: 0.08 μm / min. At this time, stacking faults 109 occurred.

(FIG. 1c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed with the same method as above. The substrate was brought into close contact with the substrate 110 at room temperature.

(FIG. 1d) The silicon substrate side of the bonded substrate was first ground by 475 μm with a surface grinding device to reduce the remaining thickness of the silicon substrate to about 150 μm (the single crystal substrate portion was 130 μm, the porous silicon portion was 20 μm, and the The portion was 0.5 μm). Subsequently, this substrate was immersed in a stock solution of a commercially available developing solution SD-1 (manufactured by Tokuyama Soda: tetramethylammonium hydroxide aqueous solution),
It was kept at a temperature of 90 ° C. for 140 minutes. As a result, the quartz substrate 110 is hardly etched, but the silicon substrate 10
0 was entirely etched by about 130 μm, and the porous silicon layer 101 was etched and exposed by about 10 μm. The substrate was subsequently immersed in a selective etching solution, and only the porous portion 101 was selectively and entirely etched. At this time, the composition of the selective etching solution and the etching rate for porous silicon were as follows: HF: H ₂ O ₂ = 1: 5 1.6 μm / mi
n. Met. Therefore, the porous portion of 10 μm was completely etched in about 7 minutes. Incidentally, the etching rate of the single crystal silicon layer 102 at this time is 0.0006 μm / h.
and remained almost without being etched. The quartz substrate 110 has an etching rate of about 0.5 μm / min. Therefore, about 4 μm was etched during the etching time. Since the original thickness of the quartz substrate was 625 μm, it has been reduced to about 621 μm.

As a result, an SOI substrate having a single-crystal silicon thin film having a thickness of 0.5 μm on a transparent substrate was obtained. The stacking fault 109 was formed on the transparent substrate in the opposite direction. This substrate was annealed in a nitrogen atmosphere at 1000 ° C. for 1 hour to perform a heat treatment for increasing the bonding force at the bonding interface. Cracks, slip lines, and the like were not generated in the single crystal silicon film by annealing.

(Embodiment 2) A second embodiment of the present invention will be described in detail with reference to FIG.

(FIG. 2A) A 4-inch P-type (100) silicon substrate 200 having a thickness of 300 μm and a resistivity of 0.01 Ω · cm is prepared, and its surface layer is made porous by 20 μm in the same manner as in the first embodiment. Silicon 201 was used.

(FIG. 2B) An epitaxial layer 202 of 0.5 μm was formed on the obtained porous surface in the same manner as in the first embodiment.
Formed to a thickness of

(FIG. 2c) A 4-inch fused quartz substrate washed with the above-prepared method with a 1:40 mixed solution of hydrofluoric acid / water, rinsed with pure water and dried with the same method. 210 and room temperature. Further, a pressure of 60 tons was applied to the entire surface of the 4-inch substrate using a press machine, and the substrate was held for 10 minutes.

(FIG. 2d) First, 180 μm of the silicon substrate portion 200 having a size of 280 μm is ground by a surface grinding device.
Remaining silicon thickness is about 100 μm (80 μm for single crystal silicon part, 20 μm for porous part, 0.5 μm for epi part)
m). Subsequently, 1: 10: 1 of hydrofluoric acid / nitric acid / acetic acid
Etching was performed with a mixed solution of 0. Then, when the porous silicon layer 201 was exposed on the surface, the porous layer 201 was selectively switched to etching with a 1: 5 mixed solution of hydrofluoric acid / hydrogen peroxide. At this time, the etching rate of hydrofluoric acid / nitric acid / acetic acid with respect to single crystal silicon was about 2 μm / min, so that it was about 40 minutes, and the etching rate of hydrofluoric acid / hydrogen peroxide with porous silicon was about 1.6 μm / min.
, The entire porous layer could be etched in about 13 minutes. The quartz substrate 210 was only etched by a few μm.

(FIG. 2E) The single-crystal silicon thin film 202 on the quartz substrate 210 obtained by the above process was patterned in an island shape in accordance with the designed area, shape and arrangement of the element. For example, channel length / channel width is 2 μm /
At the position where the 4 .mu.m MOS transistor was designed, an island of 4.times.10 .mu.m @ 2 including the source / drain regions was patterned at the designed position.

After patterning, in a nitrogen atmosphere, 1000
Heat treatment for 2 hours at a temperature of 0.5μ on a transparent substrate.
Thus, an SOI substrate provided with a single-crystal silicon thin film of m was obtained.

(Embodiment 3) A third embodiment of the present invention will be described in detail with reference to FIG.

(FIG. 3a) A 5-inch P-type (100) silicon substrate 300 having a thickness of 400 μm and a resistivity of 0.01 Ω · cm was prepared, and a porous layer 301 having a thickness of 20 μm was formed from the surface thereof.

(FIG. 3B) The epitaxial layer 302 is placed on the porous surface of the obtained substrate in the same manner as in the first embodiment.
It was formed to a thickness of 5 μm. Further, the surface of the epitaxial layer 302 of the same substrate was oxidized in water vapor at 1000 ° C. by 0.2 μm to obtain a SiO ₂ layer 303. As a result, the silicon single crystal portion of the epitaxial layer had a thickness of 0.4 μm, and the oxide film portion had a thickness of 0.2 μm.

(FIG. 3c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method. The substrate was brought into close contact with the substrate 310 at room temperature.

(FIG. 3d) In the same manner as in the first embodiment,
After the silicon substrate portion was ground to 230 μm by a surface grinding device to make the remainder 150 μm, the silicon substrate portion 300 was entirely etched by SD-1 to obtain a porous portion 30.
1 was exposed. Subsequently, the porous portion 301 was selectively etched with a hydrofluoric acid / hydrogen peroxide aqueous solution.

(FIG. 3E) The single-crystal silicon thin film 302 on the quartz substrate 310 obtained by the above process is formed into an island shape according to the designed area, shape and arrangement of the element in the same manner as in the second embodiment. Patterned.

After patterning, each island-shaped region is formed in a 0.1 ° C.
It was oxidized by 05 μm. Therefore, this oxidation step was also used as heat treatment, and as a result, an SOI substrate having a single-crystal silicon thin film having a thickness of about 0.4 μm on a transparent substrate was obtained.

(Embodiment 4) The fourth embodiment of the present invention will be described in detail with reference to FIG.

(FIG. 4a) A 5-inch P-type (100) silicon substrate 400 having a thickness of 600 μm and a resistivity of 0.01 Ω · cm was prepared, and a porous layer 101 having a thickness of 20 μm was formed from the surface thereof.

(FIG. 4b) The epitaxial layer 402 is placed on the porous surface of the obtained substrate in the same manner as in the first embodiment.
It was formed to a thickness of 5 μm.

(FIG. 4 c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method. The substrate was brought into close contact with the substrate 110 at room temperature.

(FIG. 4d) The silicon substrate portion 400 was ground using a surface grinding device while leaving 150 μm. The substrate obtained here was heat-treated at 300 ° C. for 24 hours.

(FIG. 4e) Thereafter, as in the first embodiment, S
After the remaining silicon substrate portion 400 was completely etched by D-1, the porous portion 401 was selectively etched with hydrofluoric acid / hydrogen peroxide aqueous solution.

Through the above steps, an SOI substrate provided with a single crystal silicon thin film on the quartz substrate 410 was obtained.

(Embodiment 5) The details of a fifth embodiment of the present invention will be described with reference to FIG.

(FIG. 5a) A 5-inch P-type (100) silicon substrate 500 having a thickness of 600 μm and a resistivity of 0.01 Ω · cm was prepared, and a porous layer 501 having a thickness of 20 μm was formed from the surface thereof.

(FIG. 5B) An epitaxial layer 502 is formed on the porous surface of the obtained substrate in the same manner as in the first embodiment.
It was formed to a thickness of 5 μm.

(FIG. 5C) The surface of the epitaxial layer 502 was oxidized to form a 0.1 μm SiO ₂ layer 503.

(FIG. 5d) The above substrate was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method as above.
And at room temperature.

Further, the adhered substrate was pressed at a pressure of 20 tons for 5 minutes.

(FIG. 5E) The surface grinding device was used to grind the silicon substrate portion 500 except for 150 μm.

(FIG. 5f) A heat treatment was performed at 300 ° C. for 10 hours, and then the remaining silicon substrate was etched using SD-1 in the same manner as in the first embodiment to remove the entire silicon substrate. .

Thereafter, as in the first embodiment, the porous portion 501 was selectively etched with a hydrofluoric acid / hydrogen peroxide aqueous solution.

Through the above steps, a semiconductor substrate having a single-crystal silicon thin film on a quartz substrate 510 was obtained by only one heat treatment.

(Embodiment 6) A sixth embodiment of the present invention will be described in detail with reference to FIGS.

(FIG. 1a) A 5-inch P-type (100) single crystal silicon substrate having a thickness of 625 microns (0.1
.About.0.2 .OMEGA.cm), which was set in an apparatus as shown in FIG.
The surface of No. 0 was made porous silicon 101 by 20 μm.
At this time, a 49% HF solution was used as the solution 404, and the current density was 100 mA / cm 2. At this time, the rate of making porous is 8.4 μm / min. And a porous layer having a thickness of 20 μm was obtained in about 2.5 minutes.

(FIG. 1B) A single-crystal silicon layer 102 is formed on the porous silicon 101 by a CVD method to a thickness of 0.5 μm.
m epitaxial growth. The deposition conditions are as follows.

Gas used: SiH ₄ / H ₂ gas flow rate: 0.62 / 140 (l / min) Temperature: 750 ° C. Pressure: 80 Torr Growth rate: 0.12 μm / min. At this time, stacking faults 109 occurred.

(FIG. 1c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method. The substrate was brought into close contact with the fused quartz substrate 110 at room temperature.

(FIG. 1d) The bonded substrate was first immersed in a stock solution of a commercially available developer SD-1 (aqueous tetramethylammonium hydroxide solution manufactured by Tokuyama Soda), and kept at a temperature of 85 to 90 ° C. for 10 hours. . As a result, the quartz substrate 110 was hardly etched, but the silicon substrate 100 was entirely etched by about 600 μm, exposing the porous silicon layer 101. The substrate was subsequently immersed in a selective etching solution, and only the porous portion 101 was selectively and entirely etched. At this time, the composition of the selective etching solution and the etching rate for porous silicon were as follows: HF: H ₂ O ₂ = 1: 5 1.6 μm / mi
n. Met. Therefore, the porous portion of 20 μm was completely etched in about 13 minutes. Incidentally, the etching rate of the single crystal silicon layer 102 at this time is 0.0006 μm /
Hour and remained almost without being etched. The quartz substrate 110 has an etching rate of about 0.5 μm / min. Therefore, about 7 μm was etched during the etching time. Since the original thickness of the quartz substrate was 625 μm, it was reduced to about 618 μm.

As a result, an SOI substrate having a single-crystal silicon thin film having a thickness of 0.5 μm on a transparent substrate was obtained. The stacking fault 109 was formed on the transparent substrate in the opposite direction. This substrate was annealed in a nitrogen atmosphere at 1000 ° C. for 1 hour to perform a heat treatment for increasing the bonding force at the bonding interface. Cracks, slip lines, and the like were not generated in the single crystal silicon film by annealing.

(Embodiment 7) A seventh embodiment of the present invention will be described in detail with reference to FIG.

(FIG. 2a) A 4-inch P-type (100) silicon substrate 200 having a thickness of 300 μm and a resistivity of 0.01 Ω · cm is prepared, and its surface layer is made porous by 20 μm in the same manner as in the first embodiment. Silicon 201 was used.

(FIG. 2B) An epitaxial layer 202 of 0.5 μm was formed on the obtained porous surface in the same manner as in the first embodiment.
Formed to a thickness of

(FIG. 2c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method. The substrate was brought into close contact with the fused quartz substrate 210 at room temperature.

(FIG. 2D) First, a silicon substrate portion 200 having a size of 280 μm was subjected to hydrofluoric acid / nitric acid / acetic acid 1:10:10.
Etching was performed with the mixed solution. Then, when the porous silicon layer 201 was exposed on the surface, the porous layer 201 was selectively etched with a 1: 5 mixed solution of hydrofluoric acid / hydrogen peroxide. At this time, the etching rate of hydrofluoric acid / nitric acid / acetic acid with respect to single crystal silicon was about 2 μm / min, so that it was about 140 minutes, and the etching rate of hydrofluoric acid / hydrogen peroxide with porous silicon was about 1.6 μm / min. , The entire porous layer could be etched in about 13 minutes. The quartz substrate 210 was only etched by a few μm.

(FIG. 2E) The single-crystal silicon thin film 202 on the quartz substrate 210 obtained by the above process was patterned into an island shape in accordance with the designed area, shape and arrangement of the element. For example, channel length / channel width is 2 μm /
At the position where the 4 μm MOS transistor was designed, 4 × 10 μm ² islands including the source / drain regions were patterned at the design position.

After patterning, in a nitrogen atmosphere, 1000
Heat treatment for 2 hours at a temperature of 0.5μ on a transparent substrate.
Thus, an SOI substrate provided with a single-crystal silicon thin film of m was obtained.

(Eighth Embodiment) An eighth embodiment of the present invention will be described in detail with reference to FIG.

(FIG. 3a) A 5-inch P-type (100) silicon substrate 300 having a thickness of 400 μm and a resistivity of 0.01 Ω · cm was prepared, and a porous layer 301 having a thickness of 20 μm was formed from the surface thereof.

(FIG. 3b) An epitaxial layer 302 was placed on the porous surface of the obtained substrate in the same manner as in the first embodiment.
It was formed to a thickness of 5 μm. Further, the surface of the epitaxial layer 302 of the same substrate was oxidized by 0.2 μm in steam at 1000 ° C. to obtain a SiO ₂ layer 303. As a result, the silicon single crystal portion of the epitaxial layer had a thickness of 0.4 μm, and the oxide film portion had a thickness of 0.2 μm.

(FIG. 3c) The substrate prepared by the above method was washed with a diluted hydrofluoric acid solution, dried with pure water, and then brought into close contact with a 5-inch synthetic quartz substrate 310 washed by the same method at room temperature. .

(FIG. 3d) In the same manner as in the first embodiment,
After the entire silicon substrate portion 300 was etched by SD-1, the porous portion 301 was selectively etched with hydrofluoric acid / hydrogen peroxide aqueous solution.

(FIG. 3E) The single-crystal silicon thin film 302 on the quartz substrate 310 obtained by the above process is formed into an island shape according to the designed area, shape and arrangement of the element in the same manner as in the first embodiment. Patterned.

After patterning, each island-shaped region is formed in a 0.1 ° C. oxygen atmosphere as a first step of element formation.
It was oxidized by 05 μm. Therefore, this oxidation step was also used as heat treatment, and as a result, an SOI substrate having a single-crystal silicon thin film having a thickness of about 0.4 μm on a transparent substrate was obtained.

(Embodiment 9) A ninth embodiment of the present invention will be described in detail with reference to FIGS.

(FIG. 7A) A 5-inch P-type (100) single crystal silicon substrate having a thickness of 625 μm (0.1
.About.0.2 .OMEGA.cm), which was set in an apparatus as shown in FIG.
The surface of No. 0 was made porous silicon 701 by 20 μm.
At this time, a 49% HF solution was used as the solution 604, and the current density was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / min. And a porous layer having a thickness of 20 μm was obtained in about 2.5 minutes.

(FIG. 7B) A single-crystal silicon layer 102 is deposited on the porous silicon 701 by CVD to a thickness of 0.5 μm.
m epitaxial growth. The deposition conditions are as follows.

Gas used: SiH ₄ / H ₂ gas flow rate: 0.42 / 140 (l / min) Temperature: 750 ° C. Pressure: 80 Torr Growth rate: 0.08 μm / min. At this time, stacking faults 109 occurred.

(FIG. 7c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method. The substrate was brought into close contact with the substrate 710 at room temperature.

(FIG. 7D) The silicon substrate side of the bonded substrate was ground by 475 μm with a surface grinding device to reduce the remaining thickness of the silicon substrate to about 150 μm (the single crystal substrate portion was 13 μm).
0 μm, the porous silicon portion was 20 μm, and the epi portion was 0.5 μm). Here, the substrate is heated at 300 ° C. for 24 hours.
Heat treatment for one hour and then grinding to remove the remaining silicon part 1
30 μm was removed.

(FIG. 7E) The substrate on which the porous layer 701 was exposed was successively immersed in a selective etching solution to selectively etch only the porous portion 701 entirely. At this time, the composition of the selective etching solution and the etching rate for porous silicon were as follows: HF: H ₂ O ₂ = 1: 5 1.6 μm / mi
n. Met. Therefore, the porous portion of 20 μm was completely etched in about 13 minutes. Incidentally, the etching rate of the single crystal silicon layer 102 at this time is 0.0006 μm /
Hour and remained almost without being etched. The quartz substrate 710 has an etching rate of about 0.5 μm / min. Therefore, about 7 μm was etched during the etching time. Since the original thickness of the quartz substrate was 625 μm, it has been reduced to about 618 μm.

As a result, an SOI substrate having a single-crystal silicon thin film having a thickness of 0.5 μm on a transparent substrate was obtained. The stacking fault 109 was formed on the transparent substrate in the opposite direction. This substrate was annealed in a nitrogen atmosphere at 1000 ° C. for 1 hour to perform a heat treatment for increasing the bonding force at the bonding interface. Cracks, slip lines, and the like were not generated in the single crystal silicon film by annealing.

(Embodiment 10) The first embodiment of the present invention will be described with reference to FIG.
Example 0 will be described in detail.

(FIG. 8A) A 4-inch P-type (100) silicon substrate 800 having a thickness of 300 μm and a resistivity of 0.01 Ω · cm is prepared, and its surface layer is made porous by 20 μm in the same manner as in the first embodiment. Silicon 801 was used.

(FIG. 8B) An epitaxial layer 802 having a thickness of 0.5 μm was formed on the obtained porous surface in the same manner as in the first embodiment.
Formed to a thickness of

(FIG. 8c) The substrate prepared by the above method was washed with a 1:40 mixed solution of hydrofluoric acid / water, rinsed with pure water, dried with water, and then washed by the same method. 810 at room temperature. Further, using a press machine,
A pressure of 60 tons was applied to the entire surface of the inch substrate and held for 10 minutes.

(FIG. 8D) First, 180 μm of the silicon substrate portion 800 having a size of 280 μm is ground by a surface grinding device.
Remaining silicon thickness is about 100 μm (80 μm for single crystal silicon part, 20 μm for porous part, 0.5 μm for epi part)
m). Subsequently, this substrate was heat-treated at 300 ° C. for 10 hours. Then, grinding was performed again to remove the remaining silicon substrate portion of 80 μm.

(FIG. 8E) When the porous silicon layer 201 is exposed, the substrate is subjected to hydrofluoric acid / hydrogen peroxide solution at a ratio of 1: 5.
The mixture was selectively immersed in the etching solution. Since the etching rate for porous silicon of hydrofluoric acid / hydrogen peroxide was about 1.6 μm / min, the entire porous layer could be etched in about 13 minutes. The quartz substrate 210 was only etched by a few μm.

The single-crystal silicon thin film 802 on the quartz substrate 810 obtained by the above-described process is applied to the area of the designed element,
It was patterned in an island shape according to the shape and arrangement. For example, MOS having channel length / channel width of 2 μm / 4 μm respectively
At the position where the type transistor was designed, 4 × 10 μm ² islands including the source / drain regions were patterned at the design position.

After patterning, in a nitrogen atmosphere, 1000
Heat treatment for 2 hours at a temperature of 0.5μ on a transparent substrate.
Thus, an SOI substrate provided with a single-crystal silicon thin film of m was obtained.

(Embodiment 11) The first embodiment of the present invention will be described with reference to FIG.
One embodiment will be described in detail.

(FIG. 3A) A 5-inch P-type (100) silicon substrate 300 having a thickness of 400 μm and a resistivity of 0.01 Ω · cm was prepared, and a porous layer 301 having a thickness of 20 μm was formed from the surface thereof.

(FIG. 3B) An epitaxial layer 302 was formed on the porous surface of the obtained substrate in the same manner as in the first embodiment.
It was formed to a thickness of 5 μm. Further, the surface of the epitaxial layer 302 of the same substrate was oxidized by 0.2 μm in steam at 1000 ° C. to obtain a SiO ₂ layer 303. As a result, the silicon single crystal portion of the epitaxial layer had a thickness of 0.4 μm, and the oxide film portion had a thickness of 0.2 μm.

(FIG. 3c) The substrate prepared by the above method was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water, dried, and then washed by the same method. The substrate was brought into close contact with the substrate 310 at room temperature.

(FIG. 3D) In the same manner as in the first embodiment,
After the silicon substrate portion was ground to 230 μm by a surface grinding device to make the remainder 150 μm, heat treatment was performed at 300 ° C. for 24 hours. Subsequently, all the remaining silicon substrate portion 300 was removed by grinding, and the porous portion 301 was removed. Exposed. Subsequently, the exposed porous portion 301 was selectively etched with a hydrofluoric acid / hydrogen peroxide aqueous solution.

(FIG. 3E) The single-crystal silicon thin film 302 on the quartz substrate 310 obtained by the above process is formed into an island shape according to the designed area, shape and arrangement of the element in the same manner as in the second embodiment. Patterned.

After patterning, each island-shaped region is formed in a 0.1 ° C. oxygen atmosphere as a first step of element formation.
It was oxidized by 05 μm. Therefore, this oxidation step was also used as heat treatment, and as a result, an SOI substrate having a single-crystal silicon thin film having a thickness of about 0.4 μm on a transparent substrate was obtained.

(Embodiment 12) The first embodiment of the present invention will be described with reference to FIG.
The details of the second embodiment will be described.

(FIG. 9A) A 5-inch P-type (100) silicon substrate 900 having a thickness of 600 μm and a resistivity of 0.01 Ω · cm was prepared, and a porous layer 901 having a thickness of 20 μm was formed from the surface thereof.

(FIG. 9B) An epitaxial layer 902 was placed on the porous surface of the obtained substrate in the same manner as in the first embodiment.
It was formed to a thickness of 5 μm. Subsequently, the epitaxial layer 90
2 was oxidized to form a 0.1 μm SiO ₂ layer 903.

(FIG. 9c) The above substrate was washed with a mixed solution of hydrochloric acid / hydrogen peroxide / water, rinsed with pure water and dried, and then washed by the same method to form a 5-inch fused quartz substrate 910.
And at room temperature.

Further, the substrate was brought into close contact with the substrate at a pressure of 20 tons.
Pressurized for minutes.

(FIG. 9D) The silicon substrate portion 900 was ground using a surface grinding apparatus while leaving 150 μm.

(FIG. 9E) Here, a heat treatment was performed at 300 ° C. for 10 hours. Subsequently, the remaining silicon substrate portion was ground, and the entire silicon substrate portion was removed.

Thereafter, as in the first embodiment, the porous portion 901 was selectively etched with a hydrofluoric acid / hydrogen peroxide aqueous solution.

According to the above process, a semiconductor substrate having a single-crystal silicon thin film on a quartz substrate 910 was obtained by only one heat treatment.

[0148]

As described in detail above, a conventional heat treatment was essential in producing a conventional "bonded SOI". However, by practicing the present invention, no heat treatment is performed, or by performing a single low-temperature heat treatment, a thin film is broken or peeled off as in the case of bonding substrates having different conventional thermal expansion coefficients, or It has become possible to form an SOI substrate without warping the substrate significantly. At the same time, it is easy to control the film thickness distribution of the epitaxially grown layer.
The distribution of the silicon film thickness of the OI substrate is also very good. According to this method, a light-transmitting SOI can be easily manufactured, so that it is possible to design a functional device utilizing this property, and to manufacture a large-scale integrated circuit having an SOI structure. For expensive SOS and SIM
It has become possible to provide a semiconductor substrate that can replace OX.

[Brief description of the drawings]

FIG. 1 shows a schematic cross section for explaining a process of the present invention, and an explanatory diagram of a first embodiment and a sixth embodiment of the present invention.

FIG. 2 is an explanatory view of a second embodiment and a seventh embodiment of the present invention.

FIG. 3 is an explanatory diagram of a third embodiment, an eighth embodiment, and an eleventh embodiment of the present invention.

FIG. 4 shows an explanatory diagram of a fourth embodiment of the present invention.

FIG. 5 is an explanatory view of a fifth embodiment of the present invention.

FIG. 6 is an explanatory view of an apparatus for making a silicon substrate porous.

FIG. 7 shows an explanatory diagram of a ninth embodiment of the present invention.

FIG. 8 is an explanatory view of a tenth embodiment of the present invention.

FIG. 9 is an explanatory view of a twelfth embodiment of the present invention.

FIG. 10 is an explanatory diagram showing the growth of stacking faults.

[Explanation of symbols]

100, 200, 300, 400, 500, 600, 7
00, 800, 900 single crystal silicon substrates 101, 201, 301, 401, 501, 701, 8
01,901 Porous silicon substrate 102,202,302,402,502,702,8
02, 902, 1002 Epitaxially grown layers 109, 709, 1009 Stacking faults 303, 505 Epi oxide films 110, 210, 310, 410, 510, 710, 8
10, 910 Transparent insulator substrate 604, 604 'Etching solution 605, 605' Positive electrode 606, 606 'Negative electrode 1000 Single crystal silicon substrate or insulator substrate

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-175469 (JP, A) JP-A-4-286310 (JP, A) JP-A-5-275664 (JP, A) JP-A-5-275664 217821 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/12 H01L 21/02 H01L 21/304 H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (15)

(57) [Claims] 1. A method for manufacturing a semiconductor substrate, comprising the steps of: a) a step of anodizing a surface layer on one surface of a single crystal semiconductor substrate to form a porous single crystal semiconductor layer on the non-porous single crystal semiconductor region; b) the porous single crystal semiconductor epitaxially growing a non-porous single-crystal semiconductor layer over the layer, c) it said and said single crystal semiconductor substrate insulating substrate nonporous
A step of laminating the non-porous single-crystal semiconductor regions after the superposing so that the porous single-crystal semiconductor layers are positioned inside, and substantially removing the non-porous single-crystal semiconductor regions. Grinding the non-porous single-crystal semiconductor region; d2) heat-treating the whole to strengthen the bond between the non-porous single-crystal semiconductor layer and the insulator substrate; e) the non-porous single-crystal semiconductor Etching the non-porous single-crystal semiconductor region remaining in step d) to remove the region and expose the porous single-crystal semiconductor layer; f) removing the porous single-crystal semiconductor layer; Selectively etching the porous single crystal semiconductor layer. 2. A method for manufacturing a semiconductor substrate, comprising the steps of: a) a step of anodizing a surface layer on one surface of a single crystal semiconductor substrate to form a porous single crystal semiconductor layer on the non-porous single crystal semiconductor region; b) the porous single crystal semiconductor epitaxially growing a non-porous single-crystal semiconductor layer over the layer, c) it said and said single crystal semiconductor substrate insulating substrate nonporous
A step of laminating the porous single crystal semiconductor layers so that the porous single crystal semiconductor layers are positioned inside, and then bonding the two without substantially performing heat treatment; e) removing the non-porous single crystal semiconductor region and removing the porous single crystal semiconductor Etching the non-porous single-crystal semiconductor region to expose a layer; and f) selectively etching the porous single-crystal semiconductor layer to remove the porous single-crystal semiconductor layer. 3. In the step e), etching is performed for 10 minutes.
3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the method is performed in an alkali solution at 0 ° C. or lower, an organic alkali solution, or an acid solution containing hydrofluoric acid and nitric acid. 4. 4. A method for manufacturing a semiconductor substrate, comprising the steps of: a) a step of anodizing a surface layer on one surface of a single crystal semiconductor substrate to form a porous single crystal semiconductor layer on the non-porous single crystal semiconductor region; b) the porous single crystal semiconductor epitaxially growing a non-porous single-crystal semiconductor layer over the layer, c) it said and said single crystal semiconductor substrate insulating substrate nonporous
A step of laminating the non-porous single-crystal semiconductor regions after the superposing so that the porous single-crystal semiconductor layers are positioned inside, and substantially removing the non-porous single-crystal semiconductor regions. Grinding the non-porous single-crystal semiconductor region; d2) heat-treating the whole to strengthen the bond between the non-porous single-crystal semiconductor layer and the insulator substrate; d3) the non-porous single crystal Grinding the non-porous single-crystal semiconductor region remaining in step d) to remove the semiconductor region and expose the porous single-crystal semiconductor layer; f) removing the porous single-crystal semiconductor layer Selectively etching the porous single crystal semiconductor layer. 5. The method according to claim 1, wherein the non-porous single-crystal semiconductor region is left in a thickness of 100 μm or more in the step d). 6. In the step (c), the insulating substrate and the substrate including the non-porous single-crystal semiconductor layer are connected to each other to strengthen the bond between the insulating substrate and the non-porous single-crystal semiconductor layer. The method for manufacturing a semiconductor substrate according to claim 1, wherein both are pressed with each other. 7. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the step (f), the selective etching is performed using a mixed etching solution of hydrofluoric acid and hydrogen peroxide. 8. After the step b), the surface of the non-porous single-crystal semiconductor layer is oxidized to form a surface oxide layer on the non-porous single-crystal semiconductor layer. The method for manufacturing a semiconductor substrate according to claim 1, wherein the surface oxide layer and the insulator substrate are overlapped. 9. The method according to claim 1, wherein the insulator substrate is a light-transmitting insulator substrate. 10. The method according to claim 1, wherein the light-transmitting insulator substrate is mainly composed of SiO 2. 11. The method for manufacturing a semiconductor substrate according to claim 1, wherein the single crystal semiconductor substrate contains silicon as a main component. 12. A step of preparing a first substrate having a non-porous single crystal semiconductor layer over a non-porous single crystal semiconductor region with a porous single crystal semiconductor layer interposed therebetween, wherein the first substrate and the second substrate The non-porous single-crystal semiconductor without substantially heat-treating the insulator substrate, which is a substrate,
A bonding step of bonding the layers so that the layer is located inside; a grinding step of grinding a part of the non-porous single crystal semiconductor region; the first step in which a part of the non-porous single crystal semiconductor region is ground Heat treating the entire substrate and the second substrate; and selectively etching the porous single crystal semiconductor layer to remove the porous single crystal semiconductor layer. A method for manufacturing a semiconductor substrate. 13. The semiconductor substrate according to claim 12, wherein the first substrate has an insulating film on the non-porous single-crystal semiconductor layer, and the insulating film and the second substrate are bonded to each other. Production method. 14. The method according to claim 13, wherein the insulating film is a silicon oxide film. 15. The method according to claim 12, wherein the remaining thickness of the non-porous single crystal semiconductor region after the grinding step is 100 μm or more.