JP3260874B2 - 1 / 4πQPSK modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a modulator, and more particularly, to a baseband filter used in a 1 / 4πQPSK modulation system or the like.

[0002]

2. Description of the Related Art As a feature of a second generation digital cordless telephone, a 1 / 4.pi.
hase shift keying "Quadrature phase shift keying"), TDMA
-TDD (time division multiple access-time divis
ion duplex (time division multiple access-time division duplex)).

In the 1 / 4πQPSK modulation method, as shown in FIG. 7, binary serial data is converted into 2-bit parallel data (Xk, Yk) by a serial / parallel converter 1, and the parallel data (Xk, Yk) is converted. Is divided into Ik (cos component) and Qk (sin component) having relative phase change information by the differential conversion unit 2 and the baseband unit 3
In the above, the signal subjected to the band limitation and the carrier 4 are multiplied to perform quadrature modulation to modulate the RF signal.

If the frequency of the carrier is f _c (= 2πω _c ),
Let f (= 2π) be the frequency that is band-limited in the baseband unit.
ω), the frequency spectrum of the 1 / 4πQPSK modulated signal is a spectrum up and down ω centering on ω _c as shown in FIG. Further, since the demodulated signal can be demodulated if it has a component up to a frequency f which is 1/2 of the modulation rate, the band is limited to this frequency, and the frequency interval between adjacent channel carriers is set to be about four times this frequency. You.

FIG. 9 shows an example of occurrence of adjacent channel noise. This is an example in which the band limitation of the baseband section is insufficient, the band of an adjacent channel enters, and the signal is demodulated as noise. Originally, the spectral band should be limited to ω above and below the carrier frequency f _c (= 2πω _c ).
_c2 ± ω), which occurs as noise on adjacent channels. Therefore, it is necessary to limit the band of the baseband portion of the modulator with a considerably steep low-pass filter in order to prevent noise leakage from an adjacent channel. For example, an FIR (finite-length impulse response) filter is used.

[0006] The FIR filter accumulates and multiplies an input by multiplying an impulse response obtained by inverse Fourier transform of a filter characteristic, and this is called convolution. In order to approach the ideal filter characteristics, it is necessary to increase the number of convolutions and the number of calculation bits. In the conventional technique, a multiplier and an accumulator are required to realize the convolution of the FIR filter, and moreover, a calculation cycle corresponding to the number of convolutions is required. Further, when quadrature modulation is performed, it is necessary to limit the band of two signals of the I component and the Q component, and it is necessary to double the circuit scale or double the calculation cycle and perform the calculation in time division. In particular, the circuit scale of the multiplier and the arithmetic processing time are proportional to the square of the number of calculation bits, and it is necessary to increase the circuit scale in order to approach the ideal filter characteristics, making it difficult to increase the modulation rate. ing. In addition, an increase in circuit scale has led to an increase in power consumption.

Further, in time division multiple access, it is necessary to realize a smooth transmission transient characteristic at the rise and fall of a burst in order to smoothly execute channel switching. For this reason, a transmission power control circuit separate from the modulator has been used. That is, as shown in FIG.
The output signal of the IR filter 5 is converted into a D / A signal by the D / A converter 6.
After the A-conversion, the analog output signal is multiplied by the envelope signal generated by the envelope signal generation circuit 7, or the digital output signal of the FIR filter before the D / A conversion is multiplied by a signal having an envelope characteristic as shown in FIG. However, a method of performing D / A conversion of this and performing power control of the transmission output has been used. In any of the methods, the burst response is calculated for the output signal of the modulator, and a transmission power control circuit different from the modulator is required.

[0008]

As described above, the conventional circuit has a problem that the circuit scale and the arithmetic processing capability are greatly increased and the power consumption is increased. SUMMARY OF THE INVENTION It is an object of the present invention to provide a modulator with high speed operation and low power consumption by simplifying a circuit without separately providing a transmission power control circuit.

[0009]

In order to solve the above-mentioned problems, the present invention comprises an FIR filter to which binary data is input, and reduces rising and falling transmission power at the time of data transmission by a burst signal. Control
In the 1 / 4πQPSK modulator, the input
+1, −1, 0, + 1 / √2,
Converts to the state information of −1 / √2, and according to the information
Means for generating an address by means of
In this case, the first storage circuit is configured to multiply the +1 and 0 by the impulse response of the FIR filter and store the added data in each of a steady state and a data rising or falling state. And the status information is -1 and 0
A second storage circuit for multiplying the -1 and 0 by the impulse response of the FIR filter and storing the added data for each steady state, data rising or falling state, and the state information Is + 1 / √2
In the case of −1 / √2, the + 1 / √2 and -1 / √2
The impulse response of the FIR filter are multiplied, for each steady state was summed data, a third storage circuit for storing for each state at the falling data rising or falling, of the memory circuit in response to the burst signal state a control circuit for selectively outputting the data, the address
Output of the first, second and third storage circuits
1, characterized by comprising means for adding the signals, the
/ 4πQPSK modulator.

[0010]

According to the present invention, the data obtained by multiplying the coefficient of the impulse response of the FIR filter by the input data to the FIR filter is stored in the storage circuit (ROM) at each rising, steady, and falling time. Since the data is selectively output by the control circuit, the circuit can be simplified without using a multiplier without separately providing a transmission power control circuit,
Low power consumption can be achieved by high-speed operation.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings, taking a 1 / 4πQPSK modulation circuit as an example. The FIR filter according to the present embodiment has four symbols before and after (T = 0 to T = 0).
7), 64 times of 8 times oversampling (n = 0 to 7)
Tap. First, the modulation method of 1 / 4πQPSK modulation and the operation of the FIR filter will be briefly described, and then the present invention will be described.

FIG. 3 shows a 1 / 4πQPSK signal constellation. In the figure, among input data, ● indicates an odd symbol, and ○ indicates an even symbol (an even number indicates the order of input data, and odd and even numbers are input alternately), and each symbol has (0, 0, 0). ). State each represent a _{Z 2, Z 1, Z 0} , Z 2 represents whether the negative or Q component is positive, Z ₁
Indicates whether the I component is positive or negative. Z ₀ is ± 90 °, 0 °, 180 ° or ± 45 °, ± 13
Indicates 5 °. As shown in FIG. 3, the phase angle is 45
° and the I and Q values are multiples of 1 (+1, 0, −
1) and multiples of 1 / √2 (+ 1 / √2, -1 / √2) are repeated. Therefore, the input data of the FIR is a multiple of 1 and 1
/ √2 only.

The left column of FIG. 4 shows numerical values at the time of I / Q corresponding to data Z ₂ , Z ₁ and Z ₀ . For example,
When Z ₂ = 0, Z ₁ = 0, and Z ₀ = 0, the I component is 1 and the Q component is 0. Also, Z ₂ = 0, Z ₁ = 0, Z
_{When 0} = 1, the I component is + 1 / √2 and the Q component is +
1 / √2. FIG. 5 shows the relationship between the impulse response of the FIR filter and input data.

As described above, the FIR filter obtains desired characteristics by convolving the impulse response coefficient h (nT) and the input data D (T), and is expressed by the following equation (1).

[0015]

Y = {h (nT) × D (T)} n = 0 to 7 T = 0 to 7 That is, the input 8 symbols are multiplied by a coefficient corresponding to each T, and the input symbol is further increased by 8 times. To make a sample,
Each T is multiplied eight times, n = 0-7. Therefore, 64
Are added to obtain the output of the FIR filter.

Here, the input data is divided into a group of p = (+ 1, 0), a group of m = (-1, 0), and a group of r = (+
1 / √2, -1 / √2), the input data repeats a multiple of 1 and a multiple of 1 / √2 as described above.

[0017]

Y = {h (n (2T)) × Dp (2T)} + {h (n (2T)) × Dm (2T)} + 1 / √2 × Σ ｛h (n (2T−1 ) × Dr (2T−1)｝ = Yp + Ym + Yr or

[0018]

Y = {h (n (2T−1)) × Dp (2T−1)} + {h (n (2T−1)) × Dm (2T−1)} + 1 / {2 ×} {H (n (2T) × Dr (2T)} = Yp ′ + Ym ′ + Yr ′, where Dp (T) and Dm (T) are +1, 0
Only, and Dr (T) takes values of only +1 and -1. Yp, Ym, and Yr are the results of separately convolving the terms of +1, -1, and 1 / √2. Therefore, by storing this value in a storage circuit such as a ROM and adding the values, the FIR filter can be realized only by the storage circuit and the adder.

Further, in the conventional FIR filter, calculation cycles for the number of symbols (eight times in this example) are required, but in this embodiment, it is possible in one calculation cycle.
Therefore, the calculation is fast, and it is possible to cope with a modulator having a high modulation rate. Next, data of Yp, Ym, and Yr will be described with reference to FIG. In the figure, the input D (T)
(However, T = 0-7, D (T) = Z ₂ , Z ₁ ) and 8
Assuming double oversampling, the impulse response coefficients are h (0) to h (63). If this is divided into Yp, Ym, and Yr as described above,

[0020]

Yp = h (n + 8) × Dp (2) + h (n + 24) × Dp (4) + h (n + 40) × Dp (6) + h (n + 56) × Dp (8) Ym = − (h (n + 8) ) × Dm (2) + h (n + 24) × Dm (4) + h (n + 40) × Dm (6) + h (n + 56) × Dm (8)) Yr = 1 / √2 × (h (n) × Dm (1) + H (n + 16) × Dm (3) + h (n + 32) × Dm (5) + h (n + 48) × Dm (7)) n = 0 to 7 and

[0021]

Yp ′ = h (n) × Dp (1) + h (n + 16) × Dp (3) + h (n + 32) × Dp (5) + h (n + 48) × Dp (7) Ym ′ = − (h ( n) × Dm (1) + h (n + 16) × Dm (3) + h (n + 32) × Dm (5) + h (n + 48) × Dm (7)) Yr ′ = 1 / √2 ×
(H (n + 8) × Dm (2) + h (n + 24) × Dm
(4) + h (n + 40) × Dm (6) + h (n + 56)
× Dm (8)) n = 0 to 7. Thus, Yp, Y
m, Yr, Yp ', Ym', and Yr 'are the sum of four values.
m, Yr, Yp ′, Ym ′ and Yr ′ are each 2 ⁴ × 8
(= N) = 128 patterns, and this value is used as an address of a ROM or the like. Therefore, the FIR filter has 128 × 2 =
Three 256-word ROMs, that is, 256 × 3
= 768 words using a ROM. The addresses Ap, Am, Ar are as shown in FIG.
The output values corresponding to the respective input data Z ₂ and Z ₁ are grouped into +1 and 0, −1 and 0, + 1 / √2 and -1 / 、 2, respectively. I just need.

Yp, Ym and Yr are defined as follows.

[0023]

Yp (n, Dp (2), Dp (4), Dp (6), Dp (8)) = Yp (n, AP [1: 4]) Ym (n, Dm (2), Dm (4), Dm (6), Dm (8)) = Ym (n, AP [1: 4]) Further, the address of Yr is 1 when Dr = 1, and Dr =
If the time of -1 is 0,

[0024]

Yr (n, Dr (1), Dr (3), Dr (5), Dr (7)) = Yr (n, AP [1: 4]). For example, as shown in FIG. 5, when n = 0, inputs D (0) to D (7) are respectively 1 / √2,
0, -1 / √2, 1, -1 / √2, 0, -1 / √2,-
Assuming 1

[0025]

Y (0) = Yp (0,0100) + Ym (0,0001) + Yr (0,1000)

Since the impulse response of the FIR filter is symmetric with respect to the time axis,

[0027]

H (x) = h (64−x), and in Yp ′,

[0028]

Yp ′ = h (n) × Dp (1) + h (n + 16) × Dp (3) + h (n + 32) × Dp (5) + h (n + 48) × Dp (7) = h (64-n) × Dp (1) + h (48−n) × Dp (3) + h (32−n) × Dp (5) + h (16−n) × Dp (7) = h (n ′ + 8) × Dp (7 + H (n ′ + 24) × Dp (5) + h (n ′ + 40) × Dp (3) + h (n ′ + 56) × Dp (1) n = 0 to 7, n ′ = 7 to 0 This is for Yp (n, AP [1: 4]):
The order of n is reversed, and Dp (7) to Dp (1) are input instead of Dp (2) to Dp (8). That is,

[0029]

Yp ′ (n, Dp (1), Dp (3), Dp (5), Dp (7)) = Yp ′ (n, AP [1: 4]) = Yp (n ′, AP [ 4: 1]). The same applies to Ym and Yr. Therefore, by replacing the address by the input data D and reversing the order of the oversampling time n, the above Yp ′, Yp
A result similar to m 'and Yr' is obtained, and the number of data in the ROM can be halved. In the above case, an FIR filter can be realized with three 128-word ROMs in total, that is, 374 words.

Next, transmission power control will be described. FIG. 6 shows the concept of transmission power control. In the example of FIG. 6, the power of the output data is obtained by multiplying the two rising burst symbols by a power multiplier.

[0031]

[Mathematical formula-see original document] P = (1-cos [theta]) / 2

[0032]

The transmission transient response of P = (1 + cos θ) / 2 = (1−cos (2π−θ)) / 2. Therefore, when falling,
Proceed in the reverse order of rising. It should be noted that the steady state, that is, when P = 1, is N. The output at this time is

[0033]

Yk = P × Y = P × (Yp + Ym + Yr) = P × Yp + P × Ym + P × Yr For example, in Yp,

[0034]

Ykp (nXXXX) = (1−cos ((2n + 1) π / 16) / 2 × Ykp (nXXXX) where n = 0 to 15. Here, k is 1, 1 of the states R1 and R2, respectively. Equivalent to 2.

Here, at the time of rising, the states R1 and R2 are advanced in the order of Expressions 2 and 3, and the power multiplier P is different.
Different calculation results Ykp are required. The state N
If the number of symbols is even, the state R
2, R1 proceeds in the order of Equations 2 and 3. Therefore, the impulse response coefficient hr at the time of rising and the impulse response coefficient hr at the time of falling can be shared, and only two types of data Ypk required for power control are required, R1 and R2.
In addition to the steady state N, three types may be used. Therefore, if this data is stored in the ROM, the power control of the burst transmission transient response can be performed only by designating the state transition. The same applies to Ym, Yr, Yp ', Ym', and Yr '. Therefore, the number of words in the ROM is 128 × 3 = 3
84 words is sufficient.

Next, an embodiment of the above invention will be described below. FIG. 1 is a diagram showing an embodiment of the modulator of the present invention. In the figure, 11 is a phase angle converter, 12 is a phase angle register, 1
3 is a mapping / address generator, 14 is an adder, 15
Denotes an output register, 16 denotes a control unit, 17a to 17
c is a storage unit.

The phase angle converter 11 converts input data into phase angle data according to the 1 / 4πQPSK modulation method, and stores the data Z ₁ and Z ₂ in a phase angle register. In the present embodiment, since the phase angle data Z ₀ repeats “0” and “1”, the phase angle data Z ₀ is not used in the calculation of the FIR filter. The phase angle register 12 stores the data converted by the phase angle converter 11, and the number of stages of the register is determined by the impulse length of the FIR filter. FI in this embodiment
Since the R filter has 8 symbols of 4 symbols before and after,
The number of register stages is eight. The output timing and the output order of the odd / even symbols are controlled by a control signal from the control unit 16. In the present embodiment, every other two bits of the data Z ₁ and Z ₂ are divided into two sets of odd-numbered and even-numbered, and 2 × 4 bits and 2 × 4 bits are mapped to the mapping / address generator 13.
Output to

The mapping / address generator 13 generates addresses Ap, Am and Ar based on 2 × 4 bits of data from the phase angle register 12. These addresses Ap, Am and Ar are stored in the control unit 1
The signals are alternately output in a time-sharing manner by the I / Q signals from 6.
FIG. 2 shows an example of such a mapping / address generation circuit. In FIG. 2, reference numeral 20 denotes an address generation unit that determines an address of the storage unit 17c, and 30 denotes a storage unit 1
An address generator for determining addresses of 7a and 17b, respectively, from an I / Q signal and input data Z ₂ and Z ₁ , a logical product (AND) circuit, a logical sum (NOR) circuit, and an exclusive logical sum (EX) -OR) circuit.

The control section 16 receives the burst signal and outputs odd / even symbols, R1, R2, N
Determine the state of. In addition, the control unit 16 has an I / Q
The signal and the oversampling number n of the FIR filter are determined, and an output timing signal of the phase angle register 12 is generated. The storage units 17a to 17c can use, for example, a read-only memory (ROM), and have data of an oversampling number n for each of three states R1, R2, and N.
1, R2, N, and outputs data corresponding to the addresses with addresses Ap, Am, and Ar as addresses.

The adder 14 adds the outputs of the storage units 17a to 17c and outputs the result of the FIR filter. The output register 15 converts the output data of the adder 14 into a parallel /
After serial conversion, I data and Q data are output in a time-division manner. This data is D / A converted to be output from the baseband section of the modulator.

Next, the operation of the circuit of this embodiment will be described with reference to FIG. When binary data, which is input data, is input to the phase angle conversion unit 11, the input data is converted into phase angle data Z ₁ and Z ₂ according to the １ ／ πQPSK modulation method. Data Z ₁ and Z ₂ are stored in phase angle register 12. The phase angle register 12 stores eight symbols before and after necessary for the operation of the FIR filter. The output timing is controlled by a control signal from the control unit 16, and the two bits of the data Z ₁ and Z ₂ are set to one. Every other, that is, 2 ×
4 bits and 2 × 4 bits are output to the mapping / address generation unit 13. Each data is output in the order of odd number and even number in reverse order.

The mapping / address generator 13 generates addresses Ap, Am, and Ar based on 2 × 4 bits of data from the phase angle register 12. The addresses Ap, Am, and Ar correspond to the I
/ Q signals are output alternately in a time-division manner. At the same time, from the control unit 16, the state of R1, R2, or N,
The number n of oversampling of the FIR filter is output.

The storage units 17a to 17c output predetermined data based on the above-mentioned addresses, and
The outputs of 7a to 7c are added to obtain the output of the FIR filter. Finally, the output register 15 converts the output data of the adder 14 from parallel to serial and outputs I data and Q data in a time-division manner. D /
By performing the A conversion, the output can be obtained from the baseband unit of the modulator.

In the power control, the circuit of FIG. 1 operates in the same manner as the operation in the normal state N as described above, and based on the selection signals of the states R1, R2 and N from the control unit 16, Data corresponding to each state is output from the storage units 17a to 17c, and the data is added by the adder 14, so that power control can be performed without using a power control circuit or a large-scale multiplier. it can.

Here, the power multiplier P = (1-cos
θ) / 2, but various characteristics such as linearity and exponential function can be obtained by changing the data in the ROM. If the rising and falling characteristics are symmetric, the ROM can be shared. It is possible.

[0046]

As described above, according to the present invention, a high-speed operation can be realized with a simple circuit configuration without providing a transmission power control circuit using a large-scale multiplier as in the prior art. . Therefore, the size of the wireless device can be reduced, and power consumption can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a circuit example of a mapping / address generator of FIG. 1;

FIG. 3 is a diagram showing a constellation of the 1 / 4πQPSK modulation scheme.

FIG. 4 is a diagram showing the relationship between input data to a FIR filter, possible values, and addresses.

FIG. 5 is a diagram illustrating an impulse response characteristic of an FIR filter.

FIG. 6 is a diagram illustrating transmission power control.

FIG. 7 is a diagram illustrating a 1 / 4πQPSK modulation scheme.

FIG. 8 is a conceptual diagram of a frequency spectrum of a 1 / 4πQPSK modulation signal.

FIG. 9 is a conceptual diagram illustrating adjacent channel noise.

FIG. 10 is a diagram illustrating a conventional transmission power control method.

FIG. 11 is a diagram illustrating a conventional transmission power control method.

[Explanation of symbols]

 Reference Signs List 11 phase angle conversion unit 12 phase angle register 13 mapping / address generation unit 14 adder 15 output register 16 control unit 17 storage circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-132267 (JP, A) JP-A-4-3233932 (JP, A) JP-A-3-235553 (JP, A) JP-A-4- 239245 (JP, A) JP-A-6-205056 (JP, A) JP-A-6-205057 (JP, A) JP-A-6-205058 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] An FIR filter to which binary data is input is provided, and a rising and falling transmission power during data transmission is controlled by a burst signal.
In the 1 / 4πQPSK modulator , based on the input binary data, +1 and −
Convert to status information of 1, 0, + 1 / √2, -1 / √2
Together, means for generating an address in response to the information, wherein when the state information is +1 and 0, the +1 and 0 impulse response of the FIR filter are multiplied in each steady state the added data, A first storage circuit that stores data for each state at the time of data rising or falling, and when the state information is -1 and 0, the -1 and 0 are multiplied by the impulse response of the FIR filter and added. A second storage circuit for storing data for each of a steady state, a data rising state, and a falling state, and a state where the state information is + 1 / √2 and -1 / √2,
+ / √2 and -1 / √2 are multiplied by the impulse response of the FIR filter, and the added data is stored for each steady state, data rising or falling state . a memory circuit, and a control circuit for selectively outputting the data for each state of the memory circuit in response to the burst signal, by the address
Output signal of first, second and third storage circuits to be output
And a means for adding QPSK modulator.