JP3259298B2 - Digital image signal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording apparatus for recording digital data such as digital video signals, digital audio signals, and control subcodes on a magnetic tape, and more particularly to the structure of these data. .

[0002]

2. Description of the Related Art Recently, a digital VT for digitizing a color video signal and recording it on a recording medium such as a magnetic tape.
As R, a D1 format component digital VTR and a D2 format composite digital VTR for broadcasting stations have been put to practical use.

The former digital VT of D1 format
R represents the luminance signal and the first and second color difference signals, respectively.
After performing A / D conversion at sampling frequencies of 5 MHz and 6.75 MHz, the signal is subjected to predetermined signal processing and recorded on a tape. Since the sampling frequency ratio of these component components is 4: 2: 2, the ratio is changed to 4: 1. : 2: 2 system.

The latter digital VT of D2 format
R performs sampling and A / D conversion of the composite color video signal with a signal having a frequency four times the frequency fsc of the color subcarrier signal, performs predetermined signal processing, and records the signal on a magnetic tape. I have.

[0005] Since these digital VTRs are designed on the assumption that they are used for broadcasting stations, the image quality is given top priority, and one sample has an A / D conversion of, for example, 8 bits.
The converted digital color video signal is recorded without substantial compression. In the digital VTR of the D1 format, a segment system using 10 tracks in one field in the NTSC system and 12 tracks in the PAL system is adopted as a track pattern. The segment method is adopted
It is based on the fact that it is difficult to record a large amount of recording data on one track, and that shortening the track length can reduce the effects of track linearity defects even when the track pitch is narrow.

In a digital VTR, it is necessary to record a digital audio signal, a tracking pilot signal, and the like in addition to a digital image signal on a track. In the D1 format digital VTR described above, audio data is recorded at the center of a track, and a time code and a control signal for tracking are recorded in the longitudinal direction of the tape. In D2 format,
Audio data is recorded at both ends of the track, and a time code and a control signal for tracking are recorded in the longitudinal direction of the tape in the same manner as in the D1 format.

At the time of recording / reproducing, an error occurs, so that a digital image signal, a digital audio signal,
The subcode is encoded with an error correction code. As an error correction code, a product code in which encoding is performed with separate error correction codes in a row (horizontal) direction and a column (vertical) direction of a matrix data array is known. The product code has high error correction capability because each data symbol belongs to two error correction code sequences.

[0008]

In these conventional digital VTRs, a fixed head must be disposed in the mechanism of the VTR in order to record and reproduce a tracking signal or a time code. This may be complicated, and may reduce the reliability of the tape path. Therefore, it is desirable to omit the fixed head by recording a tracking signal and control additional data in the track.

Since the data recorded in one track has a different information amount, when encoded by a product code, the size of one unit of the product code is different. Product code 1
Since a block synchronization signal is added to data and parity of a row to form a sync block, the length of the sync block differs between these data. For this reason, there has been a problem that timing control during recording and reproduction is complicated.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image signal recording apparatus capable of simplifying the timing control during recording and reproduction. Another object of the present invention is to provide a digital image signal recording apparatus which can simplify an encoder and a decoder when each of these data is encoded by a product code.

[0011]

According to the first aspect of the present invention,
Compresses and encodes the input digital image signal, the rotary drum
Digital image signals and digital audio signals encoded by the magnetic head
The data after the additional data recording process is
A digital image signal recording apparatus for recording the encoded digital image signal in a separate section of a first product code comprising an inner code and an outer code.
And Dee error correction coding, the digital audio signal,
Error correction with second product code consisting of inner code and outer code
A third code consisting of only the inner code and encoding the additional data
Error correction encoding means for error correction encoding in, an output data of the error correction encoding means, code with inner code
Means for generating a data sequence having a configuration of a sync block by adding a block synchronization signal and an ID signal to each parity of data to be converted and an parity of an inner code , the first and second product codes, That of the third sign
Parity of at least two inner codes of each inner code
The number is equal to the digital image signal, each of the sync block length of the digital audio signal and additional data is represented by an integer ratio, is set, the additional data
The sync block length of the digital image signal and digital
Shorter than the sync block length of the audio signal
And a digital image signal recording apparatus.

According to a second aspect of the present invention, a digital image signal recording apparatus is characterized in that a section length is defined by an integral multiple of a sync block length of one of a digital image signal, a digital audio signal, and additional data. It is. The invention according to claim 3 is a digital image signal,
A digital image signal recording apparatus, characterized in that a section length and a non-data section length between sections are defined by an integral multiple of a sync block length of one of a digital audio signal and additional data.

According to a fourth aspect of the present invention, the number of parities generated by a plurality of rows of the third code and one of the first product code are calculated.
A digital image signal recording apparatus characterized in that the number of parities generated by rows is set to be equal.

According to a fifth aspect of the present invention, the length of the block synchronization signal and the length of the ID signal are set to be equal between the sync blocks of the digital image signal, the digital audio signal and the additional data. And a digital image signal recording apparatus.

[0015]

A plurality of data are encoded by a product code.
The block synchronization signal and the ID signal are added to the data of each row of the product code to form a sync block. Although the size of the product code differs depending on the data and the length of the sync block, the ratio of the length of the sync block length of these data is set to an integer ratio. Therefore,
Processing such as timing control can be simplified. Also, 1
Since the length of the data section and the non-data section in the track is set to an integral multiple of the length of one sync block, the circuit can be partially used for timing control, recording processing, reproduction processing, and the like.

[0016]

An embodiment of the present invention will be described below. This description is made in the following order. a. Signal processing unit b. Channel encoder and channel decoder c. Head / tape d. Track format e. Data structure f. Audio signal interleaving and error correction g. Definition of ID data structure and post-recording area

A. First, the signal processing unit of the digital VTR in this embodiment will be described. FIG. 1 shows the configuration on the recording side as a whole. For example, three primary color signals R from a color video camera are input to input terminals denoted by 1Y, 1U, and 1V, respectively.
A digital luminance signal Y and digital color difference signals U and V formed from G and B are supplied. In this case, the clock rate of each signal is the same as the frequency of each component signal in the D1 format. That is, the respective sampling frequencies are 13.5 MHz and 6.75 MHz, and the number of bits per sample is 8 bits. The data amount is compressed by an effective information extraction circuit 2 which removes data of a blanking period from this signal and extracts only information of an effective area.

The luminance signal Y from the output of the effective information extraction circuit 2 is supplied to the frequency conversion circuit 3, and the sampling frequency is converted from 13.5 MHz to 3/4. As the frequency conversion circuit 3, for example, a thinning filter is used so that aliasing distortion does not occur. The output signal of the frequency conversion circuit 3 is supplied to the blocking circuit 5, and the order of the luminance data is converted into the order of the blocks.
The blocking circuit 5 is provided for a block coding circuit 8 provided at a subsequent stage.

FIG. 3 shows a block structure of a unit of encoding. DCT (Discrete Cosin
e Transform), ADRC (encoding adapted to a dynamic range), etc., and one block has a size of (8 × 8) pixels as shown in FIG. In FIG. 3, a solid line indicates a line of an odd field, and a broken line indicates a line of an even field.

In the output of the valid information extracting circuit 2,
After the two color difference signals U and V are supplied to the sub-sampling and sub-line circuit 4 and the sampling frequency is respectively converted from 6.75 MHz to half thereof, two digital color difference signals are alternately selected for each line, and one channel is selected. Is synthesized with the data of Therefore, the sub-sampling and sub-line circuit 4 provides a line-sequentialized digital color difference signal. FIG. 4 shows a pixel configuration of a signal sub-sampled and sub-lined by the circuit 4. In FIG. 4, ○ indicates a sampling pixel of the first chrominance signal U, △ indicates a sampling pixel of the second chrominance signal V, and × indicates a position of a pixel thinned out by sub-sampling.

A line-sequential output signal of the sub-sampling and sub-line circuit 4 is supplied to a blocking circuit 6. In the blocking circuit 6, similarly to the blocking circuit 5, the color difference data in the scanning order of the television signal is converted into the data in the block order. Like the blocking circuit 5, the blocking circuit 6 converts the color difference data into a block structure of (8 × 8) pixels. Output signals of the blocking circuits 5 and 6 are supplied to the synthesizing circuit 7.

In the synthesizing circuit 7, the luminance signal and the chrominance signal converted in the order of the blocks are converted into one-channel data, and the output signal of the synthesizing circuit 7 is supplied to a block coding circuit 8 employing, for example, DCT. . An output signal of the block encoding circuit 8 is supplied to a framing circuit 9 and is converted into data having a frame structure. This framing circuit 9
In, the switching between the image system clock and the recording system clock is performed.

A PCM audio signal is supplied from an input terminal 1A and supplied to an audio encoding circuit 15. This audio encoding circuit 15 has a DPCM
Compresses the data amount of audio data. The audio encoding circuit 15 performs interleaving in response to a mode signal from an input terminal 15a for designating a user recording mode and a soft tape mode, as described later. The output data of the audio encoding circuit 15 is supplied to a parity generation circuit 16, and a parity of a product code which is an error correction code is generated. The audio data and the parity are supplied to the mixing circuit 14.

As recording areas for audio data, two areas of audio 1 and audio 2 are prepared as described later. The audio encoding circuit 15 and the parity generation circuit 16 generate data to be recorded in these two areas. Further, when dubbing a PCM audio signal, one of the audio 1 and audio 2 areas is used. After-recording is possible in the above-described user recording mode, and after-recording is prohibited in the soft tape mode. Note that the output data of the audio encoding circuit 15 may be supplied to the framing circuit 9 and the audio data may be recorded in the recording section of the block-coded image data.

The output signal of the framing circuit 9 is supplied to an error correction code parity generation circuit 10 to generate a product code parity. The output signal of the parity generation circuit 10 is supplied to the mixing circuit 14. The output signals of the parity generation circuits 16 and 17 are supplied to the mixing circuit 14, respectively. The parity generation circuit 17 performs an error correction encoding process on the subcode from the input terminal 1S, and generates a parity. For the subcode, only the inner code of the product code having the inner code and the outer code as error correction codes is used.

This sub code is supplied from a sub code generating circuit indicated by 111. Reference numeral 112 denotes an ID signal generation circuit; 113, a synchronization signal generation circuit;
4 is a parity generation circuit, and 115 is a timing generation circuit. The subcode can be generated, for example, by a key operation of a user.

The mixing circuit 14 forms data in which these image data, audio data, and subcodes are inserted at a predetermined position of one track described later. The output signal of the mixing circuit 14 is supplied to the channel encoder 11, and channel coding is performed so as to reduce the low-frequency portion of the recording data. Channel encoder 11
Is supplied to the mixing circuit 18. Mixing circuit 18
Is supplied with a pilot signal for ATF (automatic track following control). This pilot signal is a low-frequency signal that can be separated in frequency from recording data. The output signal of the mixing circuit 18 is supplied to the magnetic heads 13A and 13B via the recording amplifiers 12A and 12B and a rotary transformer (not shown).
And recorded on a magnetic tape.

Next, the configuration on the reproducing side will be described with reference to FIG. In FIG. 2, reproduction data from the magnetic heads 13A and 13B are supplied to a channel decoder 22 and an ATF circuit 34 via rotary transformers (not shown) and reproduction amplifiers 21A and 21B, respectively. In the channel decoder 22, the channel coding is demodulated, and the output signal of the channel decoder 22 is supplied to a TBC circuit (time axis correction circuit) 23. In the TBC circuit 23, the time axis fluctuation component of the reproduction signal is removed. The ATF circuit 34 generates a tracking error signal from the level of the beat component of the reproduced pilot signal, and the tracking error signal is supplied to, for example, a phase servo circuit of a capstan servo. The operation of the ATF is basically the same as that employed in the 8 mm VTR.

The reproduced data from the TBC circuit 23 is ECC
The signals are supplied to the circuits 24, 37, and 39, where error correction using a product code and error correction for an error that cannot be corrected are performed. The ECC circuit 24 performs error correction and error correction on the image data, and
Performs error correction and error correction of audio data recorded in the audio section (audio 1 and audio 2), and the ECC circuit 39 performs error correction of the subcode. An output signal of the ECC circuit 37 is supplied to an audio decoding circuit 38. The reproduced subcode is taken out from the output terminal 33S of the ECC circuit 39. This subcode is supplied to a system controller (not shown) for controlling the operation of the entire VTR. ECC circuit 24
Is supplied to the frame decomposition circuit 25.

Each component of the block coded data of the image data is separated by the frame decomposing circuit 25, and the clock of the recording system is switched to the clock of the image system. Each data separated by the frame decomposition circuit 25 is supplied to the block decoding circuit 26, and the original data and the restored data corresponding to each block are decoded. Also, decoded data corresponding to the data recorded in the sections of audios 1 and 2 is obtained.

The audio decoding circuit 38 decodes the compression encoding of the audio signal. The decoded audio data is supplied to the synthesis circuit 36. The combining circuit 36 combines the decoded data of the audios 1 and 2 in response to the mode designation signal from the input terminal 35.
This mode designation signal is a mode ID separated by the frame decomposition circuit 25 or the audio decoding circuit 38.
It can be formed from signals. In the soft tape mode, a two-channel reproduced audio signal is obtained by synthesizing reproduced audio signals from the audio 1 and audio 2 sections. In the user recording mode, audio signals of two channels are reproduced from these sections.

The decoded data of the image data from the block decoding circuit 26 is supplied to a distribution circuit 27. In the distribution circuit 27, the decoded data is separated into a luminance signal and a color difference signal. The luminance signal and the color difference signal are supplied to block decomposition circuits 28 and 29, respectively. The block decomposing circuits 28 and 29 convert the decoded data in the block order in the order of the raster scan, contrary to the blocking circuits 5 and 6 on the transmission side.

The decoded luminance signal from the block decomposition circuit 28 is supplied to the interpolation filter 30. In the interpolation filter 30, the sampling rate of the luminance signal is from 3fs to 4fs.
(4fs = 13.5 MHz). The digital luminance signal Y from the interpolation filter 30 is taken out to an output terminal 33Y.

On the other hand, the digital color difference signals from the block separation circuit 29 are supplied to the distribution circuit 31, and the line-sequentialized digital color difference signals U and V are separated into digital color difference signals U and V, respectively. The digital color difference signals U and V from the distribution circuit 31 are supplied to the interpolation circuit 32 and are interpolated. The interpolation circuit 32 interpolates the data of the thinned lines and pixels using the restored pixel data.
Digital color difference signals U and V of fs are obtained, and are taken out to output terminals 33U and 33V, respectively.

B. Channel Encoder and Channel Decoder Next, the channel encoder 11 and the channel decoder 22 of FIG. 1 will be described. The details of these circuits are disclosed in Japanese Patent Application No. 1-143491 filed by the present applicant, and their schematic structures will be described with reference to FIGS.

In FIG. 5, reference numeral 41 denotes an adaptive scrambling circuit to which the output of the parity generation circuit 10 shown in FIG. 1 is supplied, in which a plurality of M-sequence scrambling circuits are prepared. And an M-sequence that provides an output with a small DC component is selected. Reference numeral 42 denotes a precoder for the partial response class 4 detection method, which performs an arithmetic operation of 1 / 1-D ² (D is a unit delay circuit). This precoder output is supplied to the magnetic head 13 via the recording amplifiers 12A and 12B.
Recording and reproduction are performed by A and 13B, and the reproduction output is amplified by the reproduction amplifiers 21A and 21B.

FIG. 6 showing the structure of the channel decoder 22.
In the figure, reference numeral 43 denotes an arithmetic processing circuit on the reproduction side of the partial response class 4, and 1 + D operation is performed on the outputs of the reproduction amplifiers 21A and 21B. Numeral 44 denotes a so-called Viterbi decoding circuit, which decodes data resistant to noise by an operation using the correlation and certainty of data with respect to the output of the arithmetic processing circuit 43. The output of the Viterbi decoding circuit 44 is supplied to a descrambling circuit 45, and the data rearranged by the scrambling process on the recording side is returned to the original sequence, and the original data is restored. By the Viterbi decoding circuit 44 used in this embodiment,
Compared to the case of performing decoding for each bit, 3
An improvement in dB is obtained.

C. Tape Head System As shown in FIG. 7A, the magnetic heads 13A and 13B are attached to the rotating drum 46 at 180 ° facing intervals. Alternatively, as shown in FIG. 7B, the magnetic heads 13A and 13B are attached to the drum 46 in an integrated structure. On the peripheral surface of the drum 46, 180
The magnetic tape (not shown) is obliquely wound at a winding angle slightly larger than or slightly smaller than °. FIG.
In the head arrangement shown in FIG. 7A, the magnetic heads 13A and 13B contact the magnetic tape substantially alternately, and in the head arrangement shown in FIG. 7B, the magnetic heads 13A and 13B scan the magnetic tape at the same time.

The extending directions (referred to as azimuth angles) of the gaps of the magnetic heads 13A and 13B are different. For example, as shown in FIG.
And 13B, an azimuth angle of ± 20 ° (−α, β) is set. Due to this difference in azimuth angle, a recording pattern as shown in FIG. 9 is formed on the magnetic tape. As can be seen from FIG. 9, the adjacent tracks TA and TB formed on the magnetic tape are formed by the magnetic heads 13A and 13B having different azimuth angles. Therefore, during reproduction, the amount of crosstalk between adjacent tracks can be reduced due to azimuth loss.

D. Track Format A track pattern in the above-described embodiment will be described. FIG. 10 shows an array of data recorded on one track. In the figure, the left end of the track is the head entry side, and the right end is the head separation side. Further, no data is recorded in the margin and the IBG (inter-block gap), which are hatched areas. In a preamble section (preamble or postamble) added to both ends of the data recording section, for example, a pulse signal having a frequency equal to the bit frequency of data is recorded, and a PLL provided on the reproduction side for extracting a bit clock is used. It is easy to lock.

Margins are provided at both ends of one track, and ATF pilot signals ATF1 and ATF2 are recorded adjacent to these margins. In the scanning direction of the head from the recording section of the pilot signal ATF1, the recording section of the audio signal (audio 1), the recording section of the video signal, the recording section of the audio signal (audio 2), the recording section of the subcode, the pilot signal AT
The recording section of F2 is provided in order. The effective area of one track is 16041 bytes long. At the end of the track, the contact between the head and the tape is unstable,
Pilot signals ATF1 and ATF2 are recorded. Also, at the time of high-speed reproduction in which the speed of the magnetic tape is higher than that at the time of recording, the contact at the end on the head separation side is more stable than that at the head entry side. Therefore,
The recording section of the subcode is on the side close to the end on the head separation side.

The recording data is composed of many sync blocks. A sync block has a sync block sync signal at the head thereof, an ID signal indicating the block identification and the position of the block in the screen, and a parity of data or an error correction code thereafter. It is. The length of the sync block differs between video data, audio data, and subcode, reflecting the difference in the amount of information in one track. In this example, AT
Each recording section and non-recording section of the effective area in one track other than the section (ATF1 and ATF2) of the F pilot signal is defined based on the length of the audio sync block. As shown, audio 1 and 2
Is selected as (14 × audio sync block), the video section is selected as (288 × audio sync block), and the subcode section is selected as (4 × audio sync block). Further, the lengths of the amble section and the IBG are defined as shown in the figure.

As described above, since the recording section and the non-recording section of each data are defined based on the length of the audio sync block, the timing for defining each section at the time of recording and reproduction is controlled. Can be simplified.

E. Data Structure FIG. 11A shows a data structure of video data to be recorded. One sync block length is set to 90 bytes, and a block synchronization signal (2 bytes) is positioned at the head of the sync block length.
ID data (4 bytes), data (76 bytes), and parity (8 bytes) are located. The error correction code of the video data is a product code using data of a (76 × 45) matrix arrangement. That is, for the 76-byte data included in each row, the inner code is encoded, an 8-byte parity (referred to as C1 parity) is generated, and for the 45-byte data included in each column,
The outer code is encoded, and a 3-byte parity (referred to as C2 parity) is generated. Specifically, a Reed-Solomon code can be used as the inner code and the outer code. The data shown in FIG. 11A is １ ／ of the data in one track, and the same product code configuration as shown in FIG. 11A is recorded three times in a video section in one track.

FIG. 11B shows the data structure of audio data. One sync block length is 45 bytes, a block synchronization signal (2 bytes) is located at the head thereof, and ID data (4 bytes), data (33 bytes), and parity (6 bytes) are sequentially located. As with the video data, error correction coding using a product code is performed on audio data. That is, (33 × 1
0) 3 included in each row of the matrix array data
The inner code is encoded with respect to the data of 3 bytes,
A 6-byte C1 parity is generated and 1
For the 0-byte data, the outer code is encoded,
A 4-byte C2 parity is generated.

The product code shown in FIG. 11B is applied to data recorded in an audio section (audio 1 or audio 2) per channel of audio data. In the user recording mode, one sample is 8 bits, and in the soft tape mode, one sample is 16 bits. As described later, in the soft tape mode,
In each section of audio 1 and audio 2,
One channel of L or R is recorded. One-channel data included in this recording section (audio 1 and audio 2) forms the product code in FIG. 11B. In the user recording mode, audio 1 or audio 2
, Data of two channels of L and R are recorded. In this mode, data of two channels is
Construct the product code of B. In the user recording mode, data of one channel is recorded in the first half of one audio section, and data of the other channel is recorded in the second half thereof.

FIG. 11C shows the data structure of the subcode recorded in the subcode section of one track. One sync block length is 30 bytes, a block synchronization signal (2 bytes) is located at the head thereof, and ID data (4 bytes), data (20 bytes), and parity (4 bytes) are sequentially located. For the subcode, the adjacent 2
For 40 bytes of data included in a row, error correction encoding is performed using only the inner code. That is, (20
× 6) The inner code is encoded for 40 bytes of data included in every two rows of the matrix-shaped array data, and an 8-byte C1 parity is generated. Inserted as C1 parity.

The inner code for the subcode generates parity of 8 bytes, and is therefore equal to the number of parities of the inner code for video data. Therefore, the encoder for generating the parity of the inner code or the hardware for decoding the inner code can be shared. The reason why the data of one row is 20 bytes instead of 40 bytes is to shorten the sync block length. Even during high-speed playback,
The subcode is data necessary for detecting a tape position and the like. The smallest unit that is treated as valid data in the reproduced data is the sync block.
The shorter the sync block length, the more effective subcodes can be obtained.

As described above, the sync block length of each of the video data, audio data, and subcode is set to an integer ratio of (90: 45: 30 = 6: 3: 2). Therefore, even when one block includes sync blocks of different lengths, timing control during data processing can be simplified. In addition, the block synchronization signal (2 bytes) and the ID signal (4 bytes) have the same length among these sync blocks,
Further, as described later, since the data configuration of the ID signal is also common, the circuit configuration for generating or processing these can be shared.

F. Audio signal interleave and error correction 525 line / 60 field system (eg NT
In the SC system, one frame of recording data is divided into ten (N = 5) tracks T0 to T9 and recorded as shown in FIG. As described above, in this example, sections (audios 1 and 2) in which audio data can be recorded independently in one track are provided. As an example, a PCM audio signal having a length of one frame period (sampling frequency: 48 kHz, 16-bit linear quantization, 2 channels) can be recorded in the audio 1 and 2 sections.

For each PCM audio signal in one frame period, interleave processing is performed over 2N tracks. FIG. 12 represents an L (left) channel PCM audio signal in one frame period in an analog manner. This PCM audio signal sequence for one frame period is expressed as (N =
Divide into sections of 5). A sequence including even-numbered samples in the PCM audio signal sequence included in the first section is represented by L0, and a sequence including the odd-numbered samples is represented by L1.
It expresses. Similarly, regarding the PCM audio signal sequences included in the second, third, fourth, and fifth sections, sequences L2, L4, L6,
L8 and sequences L3, L5, L including odd-numbered samples
7, L9 is formed. From the PCM audio signal of the R (right) channel in one frame period, PCM audio signal sequences R0 to
R9 is formed.

These PCM audio signal sequences are interleaved, error-correction-coded as described above, and recorded in audio 1 and audio 2 sections. PCM
As a recording mode of an audio signal, a soft tape mode used when a professional company such as a movie company produces a soft tape, and a user recording mode in which a user performs recording by himself are prepared. In soft tape mode, P
One sample of the CM audio signal is 16 bits,
In the user recording mode, one sample is 8 bits. Therefore, the data amount of the PCM audio signal in the user recording mode is half that in the soft tape mode. Not only the number of bits but also the sampling frequency may be made different in the two modes so that the data amount has the same relationship.

FIG. 14A shows a PCM in soft tape mode.
4 shows an interleaving process of an audio signal. First group of the first half of tracks T0 to T9 (tracks T0 to T9)
In the section of audio 2 in (4), (L1, L3, L5, L
7, L9) is recorded, and in the section of the audio 1,
(R0, R2, R4, R6, R8) are recorded. (R1, R3, R5, R7, R9) is recorded in the section of audio 2 of the second group of tracks T5 to T9 in the second half, and (L0, L2, L9) is recorded in the section of audio 1.
4, L6, L8) are recorded.

FIG. 14B shows the interleaving of the PCM signal in the user recording mode. In the user recording mode, as described above, since the data amount is half that of the soft tape mode, the PCM audio signal is recorded in each section of audio 1 and audio 2 in the same format as the soft tape mode. it can. Audio 1
As an example, the audio section 1 of the track T0
(L1, R0) are recorded in the tracks, and (L3, R2) (L5, R4) (L7, R6)
(L9, R8) (R1, L0) (R3, R2) (R5,
L4) (R7, L6) (R9, R8) are respectively recorded. In this case, the section of audio 1 is divided into the first half and the second half, and the upper half of the data (L
1, L3,..., R9) are recorded, and data (R0, R2,.

FIG. 15 shows another example of the interleaving in the user recording mode. The example of FIG. 15 corresponds to FIG.
L2 and L3, R2 and R3, L6 and L7, R
The recording tracks 6 and R7 are interchanged. The interleaving of FIG. 15 can be similarly applied to the soft tape mode. Also in the interleaving of FIG. 15, one and the other of a pair of data sequences obtained by dividing a PCM audio signal of one frame into N are separated into a track included in the first group and a track included in the second group. Recorded.

In a 625 line / 50 field system (for example, the PAL system), as shown in FIG. 17, one frame of recording data has (2N = 12) tracks T0 to T0.
It is divided and recorded in T11. Therefore, the PCM audio signal of one frame period is divided into (N = 6) sections over the 12 tracks, and the PCM audio signal of each section is divided into (N = 6) sections.
Interleave processing is performed in units of M audio signals.

FIG. 16 shows an analog representation of the L (left) PCM audio signal for one frame period. The PCM audio signal sequence for one frame period is divided into six sections. Sequences L0 and L in which the PCM audio signal sequence included in each section includes even-numbered samples
, L10 and a series L1, L3,..., L11 including odd-numbered samples. Similarly to the L channel, a series of R0 to R11 is formed from the R (right) channel PCM audio signal in one frame period.

As shown in FIG. 18A, in the soft tape mode, the even-numbered sequence and the odd-numbered sequence of each channel straddle tracks T0 to T11 using two audio recording sections in the track. Interleaved. This interleaving makes the even / odd interleaving and audio recording sections different between the tracks T0 to T5 and the tracks T6 to T11, as in FIG. 14A. Also, in the user recording mode, as shown in FIG. 18B, the same interleaving is performed using the first half part obtained by dividing the section of audios 1 and 2 and the latter half part.

When an error occurs in the reproduced data due to a scratch on the tape, dust or fingerprint attached to the tape,
If the error exceeds a level that can be corrected, error correction is performed on the error data to reduce the effect of the error. The above-described interleave processing is excellent in this error correction capability.

First, the error correction capability in the soft tape mode will be described with reference to FIG. As shown in FIG. 19A, it is assumed that an error (indicated by a hatched area) occurs in both the width and the length of the tape and audio data can be reproduced only from the section of audio 2. In this case, as is clear from FIG. 14A, the odd-numbered series (L1, L3, L5, L7, L9) of the L channel and R
Odd-numbered series of channels (R1, R3, R5, R
7, R9) are obtained as non-error data. Using these odd-numbered samples, even-numbered error samples can be corrected. As the retouching method, for example, a method of using an average value of samples before and after the error sample instead of the error sample can be adopted.

Next, as shown by the hatched area in FIG. 19B,
Audio 1 and audio 2 of tracks T0 to T4
Are both errors, the tracks T5 to T9
From (R1, R3, R5, R7, R9) (L0, L2,
L4, L6, L8) can be obtained as error-free data. Therefore, for the R channel, (R
0, R2, R4, R6, R8) can be average-interpolated. For the L channel, (L1, L3, L5, L5)
7, L9) can be averaged.

In the user recording mode, a high retouching ability is exhibited as in the soft tape mode. On the first record,
When the same data is recorded in audios 1 and 2, by selecting non-error data from both sections, error correction and error correction can be performed strongly. However, in this example, there is no guarantee that both data are the same, since after-recording is allowed. In such a case, error correction is performed for each of audio 1 and audio 2.

As shown by the hatched area in FIG. 20A, if a scratch in the longitudinal direction of the tape occurs due to a failure in the tape running system, the reproduced data in the first half of the audio 1 near the tape edge becomes an error. That is, PC in the lower half of FIG. 14B
M audio signals (R0, R2,..., L6, L
8) is the error data, the upper half of which (L1,
L3,..., R7, R9) are correct data.
In this case, error data can be corrected by average value interpolation using correct data.

Next, as shown in FIG. 20B, in the user recording mode, the audio PC of the tracks T0 to T4
When the M signal becomes error data, the error data can be corrected by the correct audio PCM signal from the audio 1 or 2 of the remaining tracks T5 to T9.

When data is recorded by two magnetic heads as in this embodiment, one of the magnetic heads may clog. When one of the magnetic heads logs, as shown in FIG. 21, the tracks T0, T2, T
4. Correct reproduction data cannot be obtained from T6 and T8. At the time of the head clog, in both the soft tape mode and the user recording mode, the odd-numbered sequence of the L channel and the even-numbered sequence of the R channel become error data. These error data can be interpolated as correct reproduction data from the tracks T1, T3, T5, T7, T9.

G. Configuration of ID Data and Definition of After-Recording Area An example of an ID signal inserted for each sync block will be described with reference to FIG. This ID signal is a video,
This is a common format between audio and subcode. The ID signals are ID signals ID0, ID of 1 byte each.
1, ID2 and ID3.

The ID signal ID0 is a 1-bit frame I
D (FRID), 2-bit data ID, 2-bit broadcast system ID, 2-bit post-record ID, and 1-bit mode ID. The frame ID is inverted for each frame. The data ID identifies the data type (video, audio 1, audio 2, or subcode) of the sync block. The broadcast format ID is NT (5
1 bit for distinguishing between PAL (625/50 system) and PAL (625/50 system), and HD (high resolution)
And 1 bit for identifying SD (standard resolution). The post-record ID identifies a post-record and a record that is not. The non-recording recording means both recording on an unused tape and recording in which the entire track is rewritten by overwriting. During non-recording recording, the pilot signals for tracking control at both ends of the track are always rewritten. Mode I
D identifies a soft tape mode and a user recording mode. Post-recording can be applied to any of video, audio, and subcode.

ID1 is composed of 6-bit track number data and 2-bit spare area. The track number data indicates a track number assigned to 2N tracks. In consideration of recording an image signal having an extremely large amount of information such as an HD signal, track number data is
A relatively large number of bits (6 bits) are allocated. A spare area is provided for recording data for another ID in the future.

ID2 is an 8-bit sync block number. A sync block number is added to each data sync block in one track. ID
Reference numeral 3 denotes a parity for detecting and correcting errors of ID0, ID1, and ID2 described above.

In the case of post-recording, the recording area needs to be defined with high precision. If the recording area deviates from the correct one, other recorded data is erased. To avoid this problem, it is not preferable to lengthen the non-recording section such as IBG because the recording density decreases. FIG. 23 shows an example of a configuration for generating a control pulse for defining an after-recording area using the above-mentioned after-recording ID.

As a method of defining the after-recording area, here, the end of the previous recording section is detected, and a position of a predetermined number of sync blocks from the detection is set as the start position of the after-recording area. It defines the end position of the post-recording area. For example, when dubbing video data, first, the end of the section of audio 1, more precisely, the end position of the subsequent postamble is detected. Next, the number of sync blocks is counted from the reproduced block synchronization signal, and the position of the beginning of the preamble in the video section is defined. Then, the number of sync blocks is counted, and the end position of the postamble in the video section is defined. The video section and the amble section defined in this way are an after-recording area.

As described above, when the block synchronization signal of the previous section recorded is counted and the post-recording area is defined, if the previous section has been post-recorded, the position is generally incorrect. It is. Therefore, the post-recording ID prevents the block synchronization signal in the post-recorded data from being used. If all data in the track located before the post-recording area is post-recorded data, the detection pulse of the recording section ATF1 of the pilot signal at the beginning of the track is used. Since the pilot signal has a predetermined frequency, it can be detected even if it does not have a sync block structure. Audio 1
, The detection pulse of the pilot signal is used in the same manner.

The reproduced data ID and the sync number are supplied to the decoder 51 in FIG. The data ID and the sync number are supplied to the decoder 51,
The decoder 51 generates a preset pulse in the last sync block of the recording section located before the after-recording area. Since the last sync block number differs depending on the type of data, the data ID is supplied to the decoder 51.

This preset pulse is supplied to the counter 52. The counter 52 determines the start position of the after-recording area. The output of the logic circuit 53 is supplied to the counter 52 as an enable. The after-recording ID, the detection pulse Pf of the pilot signal, and the block synchronization pulse Psy are supplied to the logic circuit 53. When the post-recording ID is at a low level, that is, in a state indicating non-post-recording, a block synchronization pulse is supplied from the logic circuit 53 to the counter 52. The logic circuit 53 defines the start position of the after-recording area based on the block synchronization pulse of the post-recorded data.

The count value of the counter 52 is
Supplied to A signal indicating the type of post-recording data is supplied to the decoder 54, and data indicating the start position of the post-recording area corresponding to the data to be post-recorded is formed by the decoder 54. The output signal of the decoder 54 is supplied to the after-recording area generating circuit 55. Dubbing area generation circuit 5
5, a signal indicating the type of post-record data is supplied.
The post-record area generation circuit 55 detects the end position of the post-record area according to the type of post-record data from the start position of the post-record area formed by the decoder 54. An after-recording area pulse Px generated by the after-recording area generating circuit 55
Rises from the post-record start position and falls at the end position according to the type of post-record data.

For example, when performing post-recording on the section of audio 2, if the preceding video section is not post-recorded, the counter 52 is preset at the end position of the postamble of the video section. Occurs, a signal indicating the start position of the after-recording area is generated at the output of the decoder 54. Further, by looking at the output of the decoder 54 and the data of the type of post-record data, the post-record area generation circuit 55 can detect the end position. Here, if the video section has been post-recorded by the post-record ID, the end position of the section is detected for the audio 1 before that. If the audio 1 is also a post-recorded audio, the detection pulse Pf of the ATF1 is used.

Although the above-mentioned post-recording area pulse Px is omitted in FIG. 1, it is supplied as a control signal to the recording amplifiers 12A and 12B, and the recording amplifiers 12A and 12B are activated during the high level period of the pulse Px. You. If necessary, the post-recording area pulse Px is reproduced by the reproduction amplifier 21A,
21B, and the reproduction amplifier 2
1A and 21B may be in a non-operation state.

[0078]

According to the present invention, since the sync block length of each of video data, audio data, and subcode is set to an integer ratio, timing control and the like are simplified, and the configuration of the processing circuit is simplified. it can. According to the present invention, since the length of each recording section and non-data section of one track is an integral multiple of the length of one sync block, the control of timing related to these sections can be simplified.
Further, according to the present invention, the subcode comprises only the inner code.
Error-correction coded with the sub-code
Sync length of video and audio data
It is set to be shorter than the block length. like this
Makes subcode efficient during high-speed playback
Can be obtained. That is, during high-speed playback,
Sub-code can only be obtained fragmentarily in block units
As a result, even if a product code is
In addition, the shorter the sync block length, the more available
An effective sub-code sync block can be obtained.
Still further, in the present invention, the inner code of video data,
Audio data inner code, subcode inner code less
In both cases, the number of parities of the two inner codes is made equal. An example
Example, disintegrate as a equal parity number generated by the plurality of rows of the product code of the sub-code is generated by one row of the product code of the video data. Thereby , hardware for parity generation and error correction can be shared.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side of a signal processing unit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration on a reproduction side of a signal processing unit.

FIG. 3 is a schematic diagram illustrating an example of a block for block encoding.

FIG. 4 is a schematic diagram used for explaining subsampling and sublines.

FIG. 5 is a block diagram schematically illustrating an example of a channel encoder.

FIG. 6 is a block diagram schematically illustrating an example of a channel decoder.

FIG. 7 is a schematic diagram used for explaining a head arrangement.

FIG. 8 is a schematic diagram used to explain azimuth of a head.

FIG. 9 is a schematic diagram used for describing a recording pattern.

FIG. 10 is a schematic diagram used for describing a data array according to an embodiment of the present invention.

FIG. 11 is an area showing a configuration of a product code of video data, audio data, and a subcode.

FIG. 12 is a schematic diagram illustrating division of one frame of audio data in the 525/60 system.

FIG. 13 is a schematic diagram showing a track pattern for segment recording of one frame of data in the 525/60 system.

FIG. 14 is a schematic diagram illustrating an example of interleaving of audio data in a 525/60 system.

FIG. 15 is a schematic diagram of another example of audio data interleaving in the 525/60 system.

FIG. 16 is a schematic diagram illustrating division of one frame of audio data in the 625/50 system.

FIG. 17 is a schematic diagram showing a track pattern of segment recording of one frame of data in the 625/50 system.

FIG. 18 is a schematic diagram illustrating an example of audio data interleaving in the 625/50 system.

FIG. 19 is a schematic diagram used to explain error correction of audio data recorded in the soft tape mode.

FIG. 20 is a schematic diagram used to explain error correction of audio data recorded in a user recording mode.

FIG. 21 is a schematic diagram used to explain error correction of audio data when one magnetic head has clogged;

FIG. 22 is a schematic diagram illustrating a configuration of an ID signal.

FIG. 23 is a block diagram illustrating an example of a configuration for generating a control signal that defines an after-recording area.

[Explanation of symbols]

 1Y, 1U, 1V Component signal input terminal 1A PCM audio signal input terminal 1S Subcode input terminal 5, 6 Blocking circuit 8 Block coding circuit 11 Channel encoder 13A, 13B Magnetic head 15 Audio coding circuit 22 Channel decoder 38 Audio decoding circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-247867 (JP, A) JP-A-60-217567 (JP, A) JP-A-2-254682 (JP, A) JP-A Sho 56- 144682 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 20/12 G11B 20/18

Claims (5)

(57) [Claims] An input digital image signal is compressed and encoded, and the encoded digital image signal and digital audio are encoded by a magnetic head mounted on a rotating drum.
The data after recording the signal and additional data for control
Each recorded in a separate section of the track on the magnetic tape
In the recording apparatus in a digital image signal so as to, a digital image signal the encoded, inner code and
The first product code Dee error correction encoding, the upper consisting of an outer code
Whether the digital audio signal is an inner code or an outer code
Error correction coding with a second product code consisting of
Error correction code with the third code consisting only of inner code
Error-correction encoding means, and output data of the error-correction encoding means,
Data to be encoded by the inner code and the parity of the inner code
Against each I, and means for generating a data sequence of the structure of a sync block by adding a block synchronizing signal and ID signal, the first and second product code and the third code of its
Parity of at least two inner codes of each inner code
Number is equal, so that the digital image signal, each of said sync block length of the digital audio signal and the additional data is represented by an integer ratio, is set, the sync block length is above Digitally of the additional data
Of the digital image signal and the digital audio signal
A digital image signal recording device characterized in that the length is shorter than the block length . 2. A digital image according to claim 1, wherein said section length is defined by an integral multiple of said sync block length of any of said digital image signal, said digital audio signal and said additional data. Signal recording device. 3. The method of claim 1, said digital image signal by an integral multiple of any of the sync block length of the digital audio signal and the additional data, non-data segment length between between the segment length and the interval A digital image signal recording device, characterized in that: 4. The apparatus according to claim 1, wherein the number of parities generated by a plurality of rows of said third code is equal to the number of parities generated by one row of said first product code. A digital image signal recording apparatus. 5. The apparatus according to claim 1, wherein the length of the block synchronizing signal is equal to the length of the ID signal among the sync blocks of the digital image signal, the digital audio signal and the additional data. A digital image signal recording apparatus characterized by being set as described above.