JP3257625B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a large capacity capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to FIGS. First, the element isolation insulating film 2 is selectively formed on the surface of the semiconductor substrate 1. Next, after forming the gate electrode 4 with the gate insulating film 3 interposed therebetween, a first diffusion layer 5 connected to the bit line and a second diffusion layer 6 connected to the capacitor are formed. Next, for example, a silicon oxide film having a thickness of 400 nm is deposited on the entire surface by a CVD (Chemical Vapor Deposition) method to form the first interlayer insulating film 7. Further, for example, a film thickness of 10
A 0 nm silicon nitride film is deposited on the entire surface to form a first etching stopper film 8. Subsequently, predetermined regions of the first interlayer insulating film 7 and the first etching stopper film 8 are opened by using photolithography,
A cell contact hole 10 and a capacity contact 11 hole are formed. Thereafter, for example, a film thickness of 40
After depositing a 0 nm polycrystalline silicon film over the entire surface, the cell contact hole 10 and the capacity contact hole 11 are buried with a first conductive film 12 made of a polycrystalline silicon film by etching back. By the above steps, FIG.
The state shown in FIG.

[0003] Next, for example, a film thickness of 8
A second interlayer insulating film 9 is formed by depositing a 00 nm silicon oxide film on the entire surface. Subsequently, for example, a silicon nitride film having a thickness of 100 nm is deposited on the entire surface by the CVD method, and the second etching stopper film 14 is formed. Through the above steps, the state shown in FIG. 7B is obtained. Next, the region other than the capacitor formation region is masked with a photoresist and etched to remove the second etching stopper film 14 and the second interlayer insulating film 9. By the above steps, FIG.
The state shown in FIG.

Subsequently, a second conductive film 1 made of, for example, a polycrystalline silicon film having a thickness of 100 nm is formed by CVD.
5 is deposited on the entire surface, and then, for example, SOG (Spin
After applying an OnGlass forming material and baking it, etch back or CMP (Chemical Mechanical Polishing).
g), the capacitor formation region becomes SO
Embed with G16. Through the above steps, the state shown in FIG. Next, after the exposed polycrystalline silicon 15 is removed by etching, the SOG 16 buried in the capacitor formation region is removed. Further, a third conductive film (18) made of, for example, a silicon nitride film (17) having a thickness of, for example, 5 nm and a polycrystalline silicon film having a thickness of, for example, 100 nm is deposited on the entire surface by CVD. Then, pattern the photoresist,
The third conductive film (18) and the silicon nitride film (17) on the bit contact opening region and the peripheral circuit region are removed by etching to form an upper capacitance electrode 18A, a capacitance insulating film 17A, and a lower capacitance electrode 15A. . With the above steps, the state shown in FIG.

Next, for example, by a CVD method,
A fourth interlayer insulating film 19 is formed by depositing a 00 nm silicon oxide film on the entire surface. After that, the bit contact opening region is patterned with the photoresist 20. Through the above steps, the state shown in FIG. Next, after the etching is performed to form the bit contact hole 22, for example, W is buried to form the bit contact plug 23. Then, for example, Al
Alternatively, the bit line 24 is formed by patterning after sputtering Cu over the entire surface. Through the above steps, the state shown in FIG. Thus, a memory cell including one transistor and one capacitor is formed.

[0006]

In a memory cell formed by a conventional manufacturing method, the following problems occur as the capacitance of the capacitor increases and the design size of the memory cell becomes finer. First, in order to increase the capacitance of the capacitor, it is usually necessary to reduce the thickness of the capacitance insulating film or increase the area of the capacitance electrode. Since there is a limit in reducing the thickness of the capacitor insulating film, attention is paid here to increasing the capacitor electrode area. In the case of the conventional example, it is necessary to increase the height of the capacitor electrode in order to increase the capacitance of the capacitor, and accordingly, it is necessary to increase the thickness of the interlayer insulating film. As a result, the aspect ratio of the bit contact hole is increased, and contact failure is likely to occur. Conversely, if the height of the capacitor electrode is reduced in order to reduce the aspect ratio of the bit contact hole, a desired capacitor capacity cannot be obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems of the conventional example, and an object of the present invention is to provide a capacitor in which a lower capacitance electrode and an upper capacitance electrode face each other via a capacitance insulating film. In such a semiconductor device, it is possible to increase the capacitance of the capacitor and reduce the aspect ratio of the bit contact hole.

[0008]

An object of the present invention is to provide a MOS transistor having source / drain regions (5, 6), a lower interlayer insulating film (7, 8) covering the MOS transistor, and An upper interlayer insulating film covering the lower interlayer insulating film; and a columnar conductive film formed by burying a capacity contact hole (11) formed in the lower interlayer insulating film in one of the source / drain regions (6). 1
2) a semiconductor device comprising: a capacitor connected via a capacitance insulating film (17A) and having a lower capacitance electrode (15A) and an upper capacitance electrode (18A) opposed to each other,
The lowermost part of the lower capacitor electrode is formed on the lower interlayer insulating film, and the upper part of the columnar conductive film embedded in the capacitor contact hole is exposed from the upper interlayer insulating film to the lower part.
The columnar conductive film protruding from the lowermost part of the capacitor electrode and filling the capacitor contact hole is the same as the columnar conductive film filling the cell contact hole formed on the other of the source / drain regions. A semiconductor device, wherein the columnar conductive film formed at a height and filling a cell contact hole formed on the other of the source / drain regions is embedded in the upper interlayer insulating film. , Can be solved.

Another object of the present invention is to (1) form a gate electrode on a semiconductor substrate with an element isolation insulating film and a gate insulating film interposed therebetween, and then connect the first diffusion layer connected to a bit line and a capacitor. Forming a second diffusion layer; (2) depositing a first interlayer insulating film, a first etching stopper film, and a second interlayer insulating film over the entire surface; A predetermined region of the interlayer insulating film, the second interlayer insulating film and the first etching stopper film is opened, and a cell contact hole and a capacitor contact hole are formed on the first and second diffusion layers, respectively. Forming; (4) embedding the cell contact hole and the capacitor contact hole with a first conductive film; and (5) depositing a third interlayer insulating film on the entire surface of the first insulating film. Etching stopper film A step of opening a capacitor formation region by etching as a stopper and projecting an upper portion of the first conductive film which has filled the capacitor contact hole from an upper surface of the first etching stopper film; and (6) an entire surface Depositing a second conductive film on the substrate, further filling the capacitor formation region with a filler, removing the exposed second conductive film by etching, and then removing the filler. (7) After depositing an insulating film for forming a capacitive insulating film and a third conductive film over the entire surface, at least opening a bit contact hole forming region of the film to form an upper capacitive electrode and a capacitive insulating film And a step of forming a lower capacitance electrode, and a method for manufacturing a semiconductor device, comprising:

[Operation] In the semiconductor device according to the present invention, the columnar conductive film on the capacitor contact and the columnar conductive film (pad) on the cell contact are formed so as to protrude from the lower interlayer insulating film. Therefore, the aspect ratio of the bit contact hole formed on the pad of the upper interlayer insulating film is reduced. Further, since the lower capacitor electrode is formed so as to surround the columnar conductive film on the capacitor contact,
The capacity of the capacitor can be increased.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. [First Embodiment] FIGS. 1 to 3 are views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Here, the same reference numerals as those used in FIG. 7 or 8 are used for the same or corresponding parts as those in FIG. 7 or FIG.

First, an element isolation insulating film 2 is selectively formed on the surface of a semiconductor substrate 1. Next, after forming the gate electrode 4 with the gate insulating film 3 interposed therebetween, a first diffusion layer 5 connected to the bit line and a second diffusion layer 6 connected to the capacitor are formed. Next, for example, a film thickness of 4
A first interlayer insulating film 7 is formed by depositing a 00 nm silicon oxide film on the entire surface. Further, a first etching stopper film 8 is formed by depositing, for example, a silicon nitride film having a thickness of 100 nm on the entire surface by the CVD method. Further, for example, a film thickness of 600
A second silicon oxide film is deposited on the entire surface to form a second interlayer insulating film 9. Subsequently, predetermined regions of the first interlayer insulating film 7, the first etching stopper film 8 and the second interlayer insulating film 9 are opened by using photolithography to form the cell contact holes 10 and the capacitor contact holes 1 respectively.
Form one. Thereafter, a polycrystalline silicon film having a thickness of, for example, 400 nm is deposited on the entire surface by CVD, and then etched back to form the cell contact hole 10 and the capacity contact hole 11 in the first conductive film made of the polycrystalline silicon film. It is embedded with the film 12. Through the above steps, the state shown in FIG.

Next, for example, a film having a thickness of 8
A third interlayer insulating film 13 is formed by depositing a 00 nm silicon oxide film on the entire surface. Subsequently, for example, a silicon nitride film having a thickness of 100 nm is deposited on the entire surface by the CVD method, and the second etching stopper film 14 is formed. By the above steps, the state shown in FIG. In this figure, the boundary between the second interlayer insulating film 9 and the third interlayer insulating film 13 is indicated by a broken line because they are formed from the same silicon oxide film. Broken lines are omitted in the following figures. Next, by masking a region other than the capacitor formation region with a photoresist and performing anisotropic etching, the second etching stopper film 14, the third interlayer insulating film 13, and the second interlayer insulating film 9 are formed. Remove. Through the above steps,
The state shown in FIG.

Subsequently, a second conductive film 1 made of, for example, a 100 nm-thick polycrystalline silicon film is formed by CVD.
After 5 is deposited on the entire surface, for example, an SOG forming material is applied and baked, and then the capacitor forming region is buried with SOG 16 by performing etch back or CMP.
Through the above steps, the state shown in FIG. Instead of SOG, another material having good embedding property and etching selectivity to polycrystalline silicon and silicon nitride, for example, BPSG (boro-phospho-silicat)
e glass) can be used. Subsequently, after the exposed second conductive film 15 is removed by etching, the SOG 16 buried in the capacitor formation region is removed. Further, by a CVD method, for example, a film thickness of 5 nm
And a third conductive film 18 made of, for example, a 100 nm-thick polycrystalline silicon film are deposited on the entire surface. Next, the cell region is masked with a photoresist, and the third conductive film 18 and the silicon nitride film 17 on the peripheral circuit region are removed by etching. Through the above steps, the state shown in FIG.

Next, for example, a film thickness of 4
A fourth interlayer insulating film 19 is formed by depositing a 00 nm silicon nitride film on the entire surface. Thereafter, the photoresist 20 is patterned to form a fourth interlayer insulating film 19, a third conductive film 18, a silicon nitride film 17, a second conductive film 15, and a second etching stopper film on the bit contact opening region. The upper capacitor electrode 18A, the capacitor insulating film 17A, and the lower capacitor electrode 15A are formed by removing 14 by etching. By the above steps, FIG.
The state shown in FIG. Photoresist 20
Is removed, for example, a silicon nitride film having a thickness of 100 nm is deposited, and anisotropic etching is performed to form a sidewall 21 made of the silicon nitride film. Thereby, a part of the bit contact hole (22) is formed. Through the above steps, the state shown in FIG.

Next, the third interlayer insulating film 13 is etched using the fourth interlayer insulating film 19 and the side walls 21 as an etching mask, and the bit contact holes 22 are formed.
Is completed and, for example, W (tungsten) is buried therein to form a bit contact plug 23. afterwards,
For example, the bit line 24 is formed by sputtering Al or Cu on the entire surface and patterning the same.
Through the above steps, the state shown in FIG. As described above, in the present embodiment, the uppermost portion of the first conductive film 12 formed on the capacitor contact is located at a position higher than the lowermost portion of the lower capacitor electrode 15A. , The capacitance of the capacitor can be increased. Further, since the conductive film on the capacitor contact and the pad (conductive film on the cell contact) are formed so that the upper ends thereof protrude from the upper surface of the first etching stopper film 8, the bit size is smaller than that of the conventional example. The aspect ratio of the contact hole can be reduced.

[Second Embodiment] FIGS. 4 to 6 are views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Here, the same reference numerals as those used in FIGS. 1 to 3 are used for the same portions as those in FIGS. The feature of this embodiment as compared with the first embodiment is that a photoresist is used to bury the capacitor formation region (in the first embodiment, SO
G). Therefore, in the present embodiment, the second etching stopper film 14 used in the first embodiment is not required.
The following description focuses on the differences from the first embodiment. First, the steps up to the state of FIG. 4A are the same as the steps up to the state of FIG. 1A in the first embodiment described above.

Next, for example, a film thickness of 9
A third interlayer insulating film 13 is formed by depositing a 00 nm silicon oxide film on the entire surface. With the above steps, the state shown in FIG. In this figure, the boundary between the second interlayer insulating film 9 and the third interlayer insulating film 13 is indicated by a broken line because they are formed from the same silicon oxide film. Broken lines are omitted in the following figures. Next, the third interlayer insulating film 13 and the second interlayer insulating film 9 are removed by masking a region other than the capacitor forming region with a photoresist and performing anisotropic etching. Through the above steps, the state shown in FIG. Subsequently, a second conductive film 15 made of, for example, a polycrystalline silicon film having a thickness of 100 nm is deposited on the entire surface by CVD, and then the capacitor formation region is buried with a photoresist 25. Through the above steps, the state shown in FIG. As a material for filling the capacitor formation region, another resin material can be used instead of the photoresist.

Subsequently, after the exposed second conductive film 15 is removed by etching, the photoresist 25 buried in the capacitor formation region is removed. further,
By a CVD method, for example, a silicon nitride film 17 having a thickness of 5 nm and a third conductive film 18 made of, for example, a polycrystalline silicon film having a thickness of 100 nm are deposited on the entire surface.
Next, the cell region is masked with a photoresist, and the third conductive film 18 and the silicon nitride film 17 on the peripheral circuit region are removed by etching. Through the above steps, the state shown in FIG. Next, CV
By a method D, for example, a silicon nitride film having a thickness of 400 nm is deposited on the entire surface to form a fourth interlayer insulating film 19. Thereafter, the photoresist 20 is patterned to form the fourth interlayer insulating film 1 on the bit contact opening region.
9, the third conductive film 18, the silicon nitride film 17, and the second conductive film 15 are removed by etching to form an upper capacitance electrode 18A, a capacitance insulating film 17A, and a lower capacitance electrode 15A. By the above steps, FIG.
The state shown in FIG.

Next, for example, a silicon nitride film having a thickness of 100 nm is deposited on the entire surface, and anisotropic etching is performed to form a side wall 21 made of the silicon nitride film. Form. Through the above steps, the state shown in FIG. Next, the third interlayer insulating film 13 is etched by using the fourth interlayer insulating film 19 and the sidewalls 21 as an etching mask to complete the bit contact hole 22 and, for example, bury W (tungsten) therein, and The contact plug 23 is formed. After that, for example, the bit line 24 is formed by patterning after sputtering Al or Cu over the entire surface. Through the above steps, the state shown in FIG. 6B is obtained.

[0021]

As described above in detail, according to the semiconductor device of the present invention, the uppermost portion of the conductive film in which the capacitor contact hole is buried is located at a position higher than the lowermost portion of the lower capacitor electrode. The capacitance of the capacitor can be increased as compared with the conventional example. Further, in the semiconductor device according to the present invention, since the columnar conductive film on the capacitor contact and the columnar conductive film (pad) on the cell contact are formed so as to protrude from the lower interlayer insulating film, the upper interlayer insulating film is formed. The aspect ratio of the bit contact hole formed on the pad can be reduced. Therefore, the connection reliability of the bit contact can be improved.
Alternatively, the thickness of the upper interlayer insulating film can be increased, and the capacitance of the capacitor can be further increased. In addition, a photolithography process for forming a bit contact hole is not particularly required, and the photolithography process for forming an upper capacitor electrode can also be used, so that the process can be simplified.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a part of a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIGS. 2A and 2B are cross-sectional views in the order of steps showing another part of the method for manufacturing a semiconductor device according to the first embodiment of the invention; FIGS.

FIG. 3 is a cross-sectional view in a process order illustrating still another portion of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating a part of a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

5A to 5C are cross-sectional views in the order of steps showing another part of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view in the order of steps showing still another part of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view in the order of steps showing a part of the conventional method for manufacturing a semiconductor device.

FIG. 8 is a cross-sectional view in the order of steps showing another part of the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulation film 3 gate insulation film 4 gate electrode 5 first diffusion layer 6 second diffusion layer 7 first interlayer insulation film 8 first etching stopper film 9 second interlayer insulation film 10 cell Contact hole 11 Capacitive contact hole 12 First conductive film 13 Third interlayer insulating film 14 Second etching stopper film 15 Second conductive film 15A Lower capacitor electrode 16 SOG 17 Silicon nitride film 17A Capacitive insulating film 18 Third Conductive film 18A Upper capacitor electrode 19 Fourth interlayer insulating film 20, 25 Photoresist 21 Side wall 22 Bit contact hole 23 Bit contact plug 24 Bit line

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 27/108 H01L 21/28 301 H01L 21/316 H01L 21/3205 H01L 21/768

Claims (8)

(57) [Claims] A MOS transistor having a source / drain region, a lower interlayer insulating film covering the MOS transistor, an upper interlayer insulating film covering the lower interlayer insulating film, and one of the source / drain regions. A capacitor connected to the lower interlayer insulating film via a columnar conductive film formed by burying a capacitive contact hole formed in the lower interlayer insulating film, wherein the lower capacitive electrode and the upper capacitive electrode face each other via the capacitive insulating film; A semiconductor device, wherein a lowermost portion of the lower capacitor electrode is formed on the lower interlayer insulating film, and an upper portion of the columnar conductive film filling a capacitor contact hole is exposed from the upper interlayer insulating film to form the lower portion.
The columnar conductive film protruding from the lowermost part of the capacitor electrode and filling the capacitor contact hole is the same as the columnar conductive film filling the cell contact hole formed on the other of the source / drain regions. A semiconductor device, wherein the columnar conductive film formed at a height and filling a cell contact hole formed on the other of the source / drain regions is embedded in the upper interlayer insulating film. . 2. The semiconductor device according to claim 1, wherein said lower capacitance electrode is formed so as to surround an upper portion of said columnar conductive film. 3. The lower capacitor electrode is formed so as to surround an upper portion of the columnar conductive film at a central portion, and is formed on an upper interlayer insulating film whose upper surface is above the upper surface of the columnar conductive film at an outer peripheral portion. 2. The semiconductor device according to claim 1, wherein said semiconductor device is formed so as to cover an inner wall surface of said capacitor forming region opening. 4. After forming a gate electrode on a semiconductor substrate with an element isolation insulating film and a gate insulating film interposed therebetween, a first diffusion layer connected to a bit line and a second diffusion layer connected to a capacitor are formed. Forming; (2) depositing a first interlayer insulating film, a first etching stopper film, and a second interlayer insulating film on the entire surface; (3) the first interlayer insulating film; Opening predetermined regions of a second interlayer insulating film and the first etching stopper film to form cell contact holes and capacitor contact holes on the first and second diffusion layers, respectively; 4) a step of embedding the cell contact hole and the capacitor contact hole with a first conductive film; and (5) depositing a third interlayer insulating film over the entire surface, and then using the first etching stopper film as a stopper. To do (C) projecting the upper portion of the first conductive film, in which the capacitor contact region is buried, from the upper surface of the first etching stopper film by opening the capacitor forming region by ching; After depositing a conductive film of, further filling the capacitor forming region with a filler, removing the exposed second conductive film by etching,
And (7) depositing an insulating film for forming a capacitive insulating film and a third conductive film over the entire surface, and then opening at least a bit contact hole forming region of the film. Forming a top capacitance electrode, a capacitance insulating film, and a bottom capacitance electrode by forming holes. 5. In the step (5), a second etching stopper film is deposited following the deposition of the third interlayer insulating film, and the second etching stopper film in the capacitor formation region is also etched. 5. The method for manufacturing a semiconductor device according to claim 4, wherein holes are formed. 6. The method according to claim 5, wherein, in the step (7), a bit contact hole forming region of the second etching stopper film is also opened. 7. In the step (7), after depositing the third conductive film, depositing a fourth interlayer insulating film over the entire surface, and thereafter depositing the fourth interlayer insulating film. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the bit contact hole forming region is opened including the step. 8. After the step (7), an insulating film for forming a sidewall is deposited on the entire surface.
Forming a sidewall forming a part of the wall surface of the bit contact hole by performing etch back; and a conductive film filling the cell contact hole using the fourth interlayer insulating film and the sidewall as an etching mask. Etching the third interlayer insulating film above to open another part of the bit contact hole in the third interlayer insulating film; and forming a bit contact plug filling the bit contact hole. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the following are added.