JP3253856B2 - Diversity receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver. The diversity receiver particularly relates to a clock recovery unit and a configuration of a received electric field strength detection (RSSI). Diversity reception, especially in digital communication, reproduces a synchronization clock for the input signal, processes the data with this clock, and combines the data of each branch in maximum ratio combining, etc. Needed.

Further, since the reproduced clock is output in synchronization with the reproduced data, a clock with no data skipping and little jitter is required even when a delay difference occurs in switching diversity or the like. In mobile communication, a time-division multiplexing method is used, and a clock that is accurately and quickly synchronized with each slot of a burst signal is required. Further, as for the RSSI, it is necessary to obtain a stable and high-accuracy value for the detected value excluding the error of the device, and it is necessary to have a followability in accordance with the changing speed with respect to the fading.

[0003]

2. Description of the Related Art FIGS. 30 and 31 show block diagrams of conventional two types of diversity receivers, and their explanation will be given. However, the same reference numerals are given to the same parts in both figures, and the description in one figure is omitted.

In FIG. 30, reference numeral 300 denotes a quadrant data detecting unit for the first branch detection phase data, and 301 denotes a second quadrant detection phase data.
Quadrant data detector for branch detection phase data, 302
Is a selector, 303 is a clock component extraction unit, 304 is a digital PLL unit, and 305 is a BTR (clock generation circuit)
306 is an RSSI level comparing unit, 307 is a most significant sign bit holding unit, and 308 is a phase shifter.

In such a configuration, the most significant code bit of the detection result of the higher RSSI level of each branch obtained by the RSSI level comparison unit is used as the most significant code bit holding unit 307 using the reproduction clock as a timing clock.
And the retained most significant code bit, ie, RS
The selector 302 selects the quadrant data of each branch detected by the quadrant data detectors 300 and 301 according to the SI level large detection holding result.

The clock component of the selected quadrant data is extracted by a clock component extraction unit 303, and after being stabilized by a digital PLL unit 304, the phase is adjusted by a phase shifter 308 to an appropriate phase, and the clock is reproduced. This reproduced clock is sent to each unit.

In FIG. 31, reference numeral 309 denotes a first branch clock component extraction unit, 310 denotes a second branch clock component extraction unit, and 311 denotes a first branch digital PLL.
, 312 are digital PLL units of the second branch, 313
Is a phaser of the first branch, 314 is a phaser of the second branch, and 315 is a selector.

As can be seen from such a configuration, in the example shown in FIG. 31, a circuit necessary for clock recovery is provided in each branch, and a clock recovered for each branch is detected by RSSI level magnitude detection. According to the result, the reproduced clock of each branch is selected using the selector 315, and the reproduced clock is transmitted to each unit.

[0009]

However, the above-mentioned conventional diversity receiving apparatus has the following problem.

[0010] A plurality of branches have different antennas, respectively, and are installed so that there is no correlation between the antennas. One of the received signals is transmitted by a path from a transmission point or by multipath fading. There is a delay difference in the reception timing in each branch.
Only if it is not possible to perform only the generation of a clock synchronized to either the branch for this, the reproduced data of each branch, when switching or synthetic, missing data depending on the size of the delay difference, further, in the synthesis There is a problem that a malfunction occurs due to combining data having different times.

In the reception field strength detection (RSSI) timing based on the recovered clock, a clock synchronized with only one branch is used for the detection timing of another branch, and the RSSI level is shifted from the symbol point. This leads to the problem that the detection accuracy is remarkably deteriorated.

When transmitting the reproduction clock to the data processing means, the clock synchronized with each branch is switched and transmitted. At this time, due to the delay difference, the amount of change in timing at the time of switching becomes large, and thus jitter occurs in the clock,
There was a problem that data processing malfunctioned.

In the case of the communication based on the time division multiplexing method, the reception timing in each burst slot is independent, and therefore, it is necessary that the internally reproduced clock has a clock synchronized with them. Therefore, in the clock synthesis, there is a problem that the clock timing must be made independent for each slot.

When RSSI is used for clock synthesis,
There was a problem that a correct and stable value could not be obtained due to the RSSI level detection accuracy and variations for each symbol. In the case of the communication by the time division multiplexing method, an error occurs because the detection of the RSSI level is not a pure value of only the burst, but is affected by values of other bursts.
Furthermore, even if the effects of other slots are removed by switching,
There has been a problem that the value immediately after the switching is not stable and a correct value cannot be obtained.

The present invention has been made in view of the above points, and has as its object to provide a diversity receiving apparatus capable of accurately reproducing a reception synchronization clock.

[0016]

FIG. 1 shows the principle of the present invention. The diversity receiving apparatus shown in FIG. 1 includes electric field strength detecting means 5 and 6 for detecting the electric field strength of the received signals of antennas 1 and 2, detecting means 7 and 8 for detecting the received signals,
Data reproducing means 9 and 10 for reproducing data from the detected signal to obtain branch reproduced data, and clock reproducing means 11 and 12 for reproducing a clock from the detected signal to obtain a branch reproduced clock, First to n-th branch means B1 and Bn in which each of the electric field strength detection means 5 and 6, detection means 7 and 8 and data recovery means 9 and 10 are synchronized with a branch recovery clock, and first to n-th branches An electric field strength comparing means 13 for obtaining the magnitude of the electric field strength and difference data indicating the difference by detecting the difference between the electric field strengths obtained by the means B1 and Bn; Clock synthesizing means 14 for synthesizing each of the branch reproduced clocks obtained by the first to n-th branch means B1 and Bn according to the ratio to output a reproduced clock; When the data difference is larger than a predetermined threshold, branch reproduction data having a large electric field strength is selected and output as reproduction data, and when the difference is smaller than a predetermined threshold, each branch reproduction data is synthesized and reproduced data is reproduced. And a data switching / synthesizing means 16 synchronized with the reproduced clock output as the data.

According to such a configuration, regardless of the delay difference between the received signals in each branch, the recovered clock and
It is possible to stably obtain reproduction data synchronized with the reproduction clock.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a radio unit of the diversity receiving apparatus for performing the delay time correction between the diversity receiving branches according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a first internal configuration example of the clock synthesizing unit shown in FIG. FIG. 4 is a block diagram of a second internal configuration example of the clock synthesizing unit shown in FIG. FIG. 5 is a block diagram showing an example of the internal configuration of the count value generation unit shown in FIG. FIG. 6 is a block diagram showing a case where the count value synthesizing unit shown in FIG. 5 is provided with a count value change amount limiting function.

FIG. 7 is a block diagram showing an example of the internal configuration of the ratio setting converter shown in FIG. FIG. 8 is a block diagram of the clock delay difference quantization unit shown in FIG. FIG. 9 is a block diagram showing a third internal configuration example of the clock synthesizing unit 14 shown in FIG. FIG. 10 is a block diagram of an alarm generator added to the clock synthesizer shown in FIG.
FIG. 11 is a block diagram showing a case where an averaging circuit is connected between the RSSI detector and the RSSI level comparator shown in FIG.

FIG. 12 is a block diagram of a first internal configuration example of the averaging circuit shown in FIG. FIG. 13 is a block diagram of a second internal configuration example of the averaging circuit shown in FIG. FIG. 14 is a block diagram showing the configuration of the burst slot corresponding synthesized clock generation unit in the clock synthesis unit shown in FIG.
FIG. 15 is a block diagram of the memory shown in FIG.
FIG. 16 is a block diagram of a third internal configuration example of the averaging circuit shown in FIG. In all of the above drawings, the same parts are denoted by the same reference numerals.

This embodiment is an apparatus for internally correcting a delay time difference between individual branches when a plurality of demodulation circuits input from a plurality of antennas such as diversity reception are provided. A BTR circuit is provided, and the phase difference of the reproduced clock synchronized with the input data is calculated by B
It is quantized by the reference clock used in the TR circuit and used for the operation. Further, the quantized delay difference is represented by RSSI using the electric field reception strength level (RSSI) input to each branch.
Clock timing is generated by synthesizing at a ratio corresponding to the I difference.

Further, in the case where the variation of the RSSI difference changes abruptly so that the jitter becomes less than a certain level in the synthesized clock, the variation of the clock timing is one clock of a predetermined reference clock (high speed) or a predetermined clock. Only the clock equivalent is used as the maximum movement amount, and the RSS is gently
Converge to a ratio according to the I difference. Further, a monitoring function is provided when the delay difference exceeds a half symbol of the received signal, and a function of selecting a branch where the clock synthesis is stopped and the RSSI level becomes large is provided. At the time of burst reception, a memory is provided for each slot to hold a combined clock phase in order to cope with different timings for each burst slot.

This enables normal data demodulation even when a delay difference occurs in each branch. Also, at the RSSI level, an integrating circuit is provided to prevent sudden RSSI level fluctuations due to noise and the like, and a moving average can be obtained by providing an integrating circuit by convolution as an averaging circuit. A circuit for holding the subsequent RSSI level is provided, and a function of giving the value to the averaging circuit at the start of the next burst is provided, so that the average can be continuously obtained for each burst slot.

In FIG. 2, reference numeral 1 denotes a receiving antenna unit of the first branch, 2 denotes a receiving antenna unit of the n-th branch, 3
Is the high-frequency receiving section of the first branch, 4 is the high-frequency receiving section of the n-th branch, 5 is the RSSI detecting section of the first branch, 6 is the RSSI detecting section of the n-th branch, 7 is the detecting section of the first branch, 8 is A detector for the n-th branch, 9 is a data reproducer for the first branch, 10 is a data reproducer for the n-th branch, 1
1 is a clock recovery unit (BTR unit) of the n-th branch, 12
Is a clock recovery unit (BTR unit) of the n-th branch, 13 is an RSSI level comparison unit, 14 is a clock synthesis unit, 15 is a switching synthesis control unit, 16 is a data switching synthesis unit, 1
Reference numeral 7 denotes a data processing unit / TDMA control unit.

That is, there are provided n first to n-th branches indicated by broken-line frames, and the receiving antennas 1 and 2,
The receiving high-frequency units 3 and 4, the RSSI detecting units 5 and 6, the detecting units 7 and 8, the data reproducing units 9 and 10, and the clock reproducing units 11 and 12 are provided. A clock synthesizing unit 14 is provided on the output side of the clock recovery units 11 and 12 of the first to n-th branches.

The received signals received by the receiving antennas 1 and 2 are sent to the RSSI detection units 5 and 6 and the detection units 7 and 8 via the reception high frequency units 3 and 4. RSSI detectors 5, 6
After detecting the received field strength data at
It is sent to the I comparison unit 13. As a result, the magnitude of the received electric field strength in each branch and the difference between them are obtained, and the difference information is used as the clock combining unit 14 and the switching combining control unit 15.
Send to

On the other hand, detectors 7 and 8 detect the received signal,
This is sent to the data reproducing units 9 and 10 as a detection baseband signal. In the data reproducing units 9 and 10, the signals demodulated by the detectors 7 and 8 are determined, and the result of the determination is sent to the data switching unit or the combining unit 16 as reproduced data.

The baseband signals from the detectors 7 and 8 are also sent to clock reproducers 11 and 12, where a clock synchronized with the received signal is reproduced. Inside each branch, a clock recovery unit 11 provided for each branch,
Twelve reproduction clocks are used as data reproduction and RSSI detection timing.

The clock synthesizing unit 14 receives the RSSI difference information between the branches from the RSSI comparing unit 13 and the reproduced clocks of the clock reproducing units 11 and 12. Timing synthesis of both reproduced clocks is performed according to the ratio of whether the clocks are large (for example, 2: 3).

In the data switching unit or synthesizing unit 16, the output data of the clock synthesizing unit 14 is used as the timing of the data switching unit or synthesizing unit 16.
When the difference is larger than a predetermined threshold value, switching is performed so that higher-level reproduced data is selected, and when the difference is larger than a predetermined value, according to the control of the switching / combining control unit 15 that determines whether to switch or combine in accordance with difference information. Is smaller than the threshold value, the two reproduced data are combined, and the data processing and TDMA
It is configured to be output to the control unit 17.

In such a configuration, first, in the plurality of first to n-th branches shown in FIG. 2, a clock synchronized with the reception signal of each branch is reproduced. The clock synthesizing unit 14 to which these reproduced clocks are input is connected to the RSSI detection units 5 and 6 connected to the output side of each branch.
The RSSI level difference data from the I level comparison unit 13 is also input, and the reproduced clock of each branch is synthesized according to the difference data.

In each branch, the signals received by the reception antenna units 1 and 2 are converted into baseband signals by performing necessary processing such as frequency conversion in the reception high frequency units 3 and 4. RSSI detectors 5, 6
And output to the detectors 7 and 8.

The detection signals from the detectors 7 and 8 are input to the data reproducers 9 and 10, where they are synchronized with the reproduced clocks from the clock reproducers 11 and 12 reproduced at the reception timing for each branch. The data is output to the data switching / combining unit 16 as reproduction data. However, these reproduced data have different correlations in the reception characteristics of the receiving antenna units 1 and 2 in each branch, and therefore have different reproduction timings.

In the data switching / synthesizing section 16, the reproduction data is resynchronized with the synthesized clock output from the clock synthesizing section 14, and the reproduction / synthesis of each reproduction data is synthesized or switched in accordance with a control signal from the switching / synthesis control section 15. Is performed and output to the data processing and TDMA control unit 17. The data processing and TDMA control unit 17 also receives the synthesized clock output from the clock synthesis unit 14.

Therefore, the reproduced data synchronized with the synthesized clock from the clock synthesizing unit 14 and the synthesized clock can be stably transmitted to the data processing and TDMA control unit 17 irrespective of the delay difference of the received signal in each branch. Can be
Since the clock timings are aligned, data phase synthesis and maximum ratio synthesis can be performed.

Further, since the RSSI level difference data is used at the time of synthesizing the reproduced clock, the clock of the branch received properly can be used, and the unstable element can be removed.

Next, FIG. 3 shows a first internal configuration example of the clock synthesizing unit 14 shown in FIG. In FIG. 3, reference numeral 18 denotes a high-speed clock generator for quantization;
Is a composite clock counter, and 20 is a count set value load timing generator.

The count set value generated in the synthesized clock generator is sent to the synthesized clock counter 19. The high-speed clock output from the high-speed clock generator for quantization 18 is used as the count clock of the synthesized clock counter 19.

As the count start timing of the composite clock counter 19, a load timing (count start timing) signal output from the count set value load timing generator 20 is used.

Count setting value load timing generator 2
For 0, the clock recovery units 11 and 12 of each branch
The recovered clock output from the controller is input, and a valid branch clock is selected according to the synthesized clock, and the selected clock is generated as a load timing signal. The synthesized clock counter 19 is configured to count up to a set value with a high-speed quantization clock based on the load timing signal and use the counted value as a synthesized clock.

In such a configuration, the counter 19
Is used to detect a delay difference between reproduced clocks in each branch, and generates a composite clock by counting high-speed clocks of the high-speed quantization clock 18. Since the high-speed clock for generating the reproduction clock is equal to the clock for quantizing the delay difference, it is possible to match the detection accuracy of the delay difference with the amount of change in the timing of the synthesized clock.

The count phase and the cycle of the counter 19 are determined by the count set value, and the load timing of the count set value to the counter is determined by the ripple carry of the synthesized clock counter 19 or the clock timing of each branch. The timing of the synthesized clock can be freely changed in units of one clock cycle by reading the count set value and generating the count set value.

Next, FIG. 4 shows a second internal configuration example of the clock synthesizing section 14 shown in FIG. In FIG. 4, reference numeral 21 denotes a clock delay difference quantization unit, 22 denotes a clock edge detection unit, 23 denotes a clock generation counting unit, 24 denotes a ratio setting conversion unit based on the RSSI difference, and 25 denotes a count value generation unit.

The recovered clocks of the clock recovery units 11 and 12 shown in FIG. 2, the high-speed clock output from the high-speed clock generator for quantization 18, and the RSSI level difference output from the RSSI level comparison unit 13 shown in FIG. A clock delay difference quantizer 21 to which data is input, a clock edge detector 22 to which both reproduced clocks and difference data are input, a ratio setting converter 24 to which RSSI level difference data is input, a clock delay Count value generation unit 2 connected to the output side of difference quantization unit 21 and ratio setting conversion unit 24
5, the count value generator 25 and the clock edge detector 2
Clock timing comparison unit 2 connected to the output side
3 is provided.

The clock delay difference quantizing section 21 obtains the magnitude relationship between the levels of the respective reproduction clocks from the difference data, and uses the high-speed clock as a timing to indicate whether the small clock is ahead or behind the large clock. And outputs this as delay difference data.

The clock edge detecting section 22 obtains the magnitude relationship between the levels of the reproduced clocks from the difference data, detects the rising or falling edge of the large clock, and outputs the timing.

The ratio setting conversion unit 24 obtains the ratio of the received signal level from the difference data, for example, the ratio 1/5 of the small level when the larger level is set to 1, and uses this as ratio data to obtain the count value generation unit 25. Output to

The count value generation section 25 multiplies the delay difference data output from the clock delay difference quantization section 21 by 1/5 ratio data and outputs the result to the clock generation count section 23 as a count value. That is, the count value indicates the delay difference ratio of the delay / advance of the small clock with respect to the large clock.

The clock generation counter 23 outputs a synthesized clock by delaying or advancing the timing of the rising or falling edge of the large clock output from the clock edge detector 22 by the time indicated by the count value.

In such a configuration, the clock generation counting section 23 uses the timing from the clock edge detection section 22 as a reference point, counts only the count value indicated by the count value generation section 25 from this point, and detects the clock change. A synthesized clock is generated by advancing or delaying. Therefore, it is possible to generate a synthesized clock according to the ratio based on the RSSI level difference, and it is possible to obtain a highly reliable reproduced clock.

Next, FIG. 5 shows an example of the internal configuration of the count value generator 25 shown in FIG. In FIG. 5, 30 is a ratio-count value converter, 31 is a count set value latch, 32 is a count value comparator, 34
Is an adder / subtractor.

The ratio-count value converter 30 calculates the ratio data output from the ratio setting converter 24 shown in FIG.
The count reference value is output by multiplying by the delay difference data output from the clock delay difference quantization unit 21 shown in FIG.

The count value latch section 31 includes an adder / subtractor 34
Is held, and the held count value is compared with the count value comparing unit 32 and the adder / subtractor 34.
Output to

The count value comparing section 32 finds a difference of ± how much the set count value is apart from the count reference value, and outputs the found ± difference value to the adder / subtractor 34 as control data.

The adder / subtractor 34 adds / subtracts a value internally generated according to the control data to / from the held count value, and adds the resulting count value to the latch unit 31 and the clock generation count shown in FIG. This is output to the unit 23. If the control data indicates that the count reference value is equal to the count value, no addition / subtraction is performed. In other words, if the control data is separated by +10 from the count reference value and the held count value, an operation for eliminating the difference is performed.

By repeating the above feedback loop, the count value output from the adder / subtractor 34 is made equal to the count reference value from the ratio-count value converter 30.

In such a configuration, the count reference value output from the ratio-count value conversion unit 30 and the count value held by the count value latch unit 31 are compared by the count value magnitude comparison unit 32, and the count reference value is compared with the count reference value. Control data on the direction of the operation (addition, subtraction, or stop of the operation) that makes the count value equal is supplied to the adder / subtractor 34.

The adder / subtractor 34 adds / subtracts a fixed or specified value to / from the held count value, that is, the current count set value, based on the control data, and outputs the result as the next count value. Here, in the adder / subtractor 34, when the count reference value and the held count value become equal, the operation in the adder / subtractor 34 is stopped, the held count value is output as it is as the next count value, and the count value latch unit 31
Is held.

As a result, the count value finally becomes the ratio-
The values in the count value converter 30 approach or become equal as a convergence point. Therefore, even when the RSSI level difference data changes abruptly, the change of the output count value of the adder / subtractor 34 becomes gentle and can follow the RSSI level difference.

Next, FIG. 6 is a block diagram showing a case where the count value synthesizing section shown in FIG. 4 is provided with a count value change amount limiting function, which will be described. 6, a newly provided component is a clock movement amount setting table indicated by reference numeral 35. FIG. 6 shows only the components necessary for the description among the components shown in FIG.

When the adder / subtracter 34 adds / subtracts the value corresponding to the control data to / from the held count value, the clock movement amount setting table 35 restricts the magnitude of the value of the addition / subtraction. The clock movement amount setting value for preventing the count value output from the output signal 34 from changing abruptly and causing jitter in the synthesized clock shown in FIG. 4 is registered.

The set value of the amount of clock movement is arbitrarily set, and the set value of the amount of clock movement corresponding to the set value is output from the table 35 to the adder / subtractor 34.

According to such a configuration, the count value can be changed gently, whereby the jitter of the synthesized clock can be suppressed within the frequency of the high-speed quantization clock.

Next, FIG. 7 is a block diagram showing an example of the internal configuration of the ratio setting converter 24 shown in FIG. In FIG. 7, 29 is the RSSI level difference−
A ratio conversion table, 37 is an RSSI level comparing / monitoring unit for the first branch, 38 is an RSSI level comparing / monitoring unit for the nth branch, 39 is an unreceivable RSSI level setting value holding unit, and 40 is a combining ratio masking unit.

RSSI level difference-ratio conversion table 29
Is the ratio of each branch RSSI level (eg, 1: 3)
Is registered, and outputs a ratio value corresponding to the difference data output from the RSSI level comparison unit 13 shown in FIG.

RSSI level comparison / monitoring units 37 and 38
Performs a comparison between the setting value of the unreceivable RSSI level setting value holding unit 39 and the RSSI level output from the RSSI detection units 5 and 6 of each branch shown in FIG. The RSSI level data indicating whether the value is larger or smaller than the value is output to the combining ratio mask unit 40.

The combining ratio masking section 40 outputs the unreceivable RSS
The RSSI level data of the branch below the I level setting value is masked, and the ratio value is corrected so that the clock phase of the branch having the RSSI level below the setting value does not affect the ratio. Is output to the count value generator 25 shown in FIG.

According to such a configuration, when the clock in the unreceivable branch is in an undefined state, the correct clock phase and frequency are not affected by the undefined clock, and the timing error is reduced. The ratio data based on the RSSI level difference for generating a stable clock can be output without generation.

Next, FIG. 8 shows a block diagram of the clock delay difference quantization section 21 shown in FIG. 8, reference numeral 41 denotes a clock rising edge detection unit, 42 denotes a clock falling edge detection unit, and 43 denotes a clock delay difference counting unit.

The clock rising edge detecting section 41
Among the recovered clocks of the first to n-th branches, a rising edge of the recovered clock whose level can be determined from the difference data is detected. The clock rising edge detection unit 42
Detects the rising edge of the reproduced clock of a small level that can be determined from the difference data among the reproduced clocks of the first to n-th branches.

The clock delay difference counting unit 43 determines whether the time between the rising edges output from the detection units 41 and 42 is equal to or higher than the clock used for generating the reproduced clock, Specifically, the counting is performed in accordance with a high-speed clock that is equal to or higher than the frequency of the jitter allowed in the synthesized clock, and the value obtained by this is used as delay difference data as a count value generation unit 2 shown in FIG.
5 is output.

Next, FIG. 9 is a block diagram showing a third internal configuration example of the clock synthesizing unit 14 shown in FIG. 2, and the configuration will be described. In FIG. 9, 29a is a delay difference ratio conversion table, 44 is a clock timing comparison unit, and 45 is a count value setting addition / subtraction unit. The other components are the same as those used in any of FIGS. 2 to 8 described above, and are denoted by the same reference numerals.

The clock delay difference quantization section 21 outputs the delay difference data of each branch recovered clock to the delay difference ratio conversion table 29a. The clock edge detecting section 22 detects an edge of a high-level clock, and outputs the detected edge data to the clock synthesizing counting section 23.

The delay difference ratio conversion table 29a stores the delay difference data output from the clock delay difference
A convergence point, which is a point between each clock edge when synthesizing the large clock and the small clock, according to the difference data output from the RSSI level comparison unit 13 shown in FIG. The convergence point data corresponding to the data and the difference data is output to the count value setting addition / subtraction unit 45.

In the clock movement amount setting table 35, a set value of the clock timing change amount per one cycle is registered, and the set value is added to the count value setting addition / subtraction unit 45.
Output to

The clock timing comparing section 44 adds / subtracts a deviation amount data indicating how much the edge of the synthesized clock output from the clock generation counting section 23 deviates from the convergence point indicated by the convergence point data. This is output to the unit 45.

The count value setting addition / subtraction unit 45 indicates a movement amount for moving the edge of the high-level clock output from the clock edge detection unit 22 to the convergence point from the convergence point data, the set value, and the deviation amount data. The moving amount count value is output to the clock synthesizing counter 23.

The clock synthesizing counter 23 moves the edge of the high-level clock to the convergence point in accordance with the movement count value, and outputs this as a synthesized clock. According to such a configuration, the jitter of the synthesized clock is suppressed,
The duty of the clock can be set to 50%, and a stable synthesized clock can be obtained.

Next, FIG. 10 shows a block diagram of an alarm generating unit added to the clock synthesizing unit 14 shown in FIG. 2, and the configuration will be described. In the alarm generation unit shown in FIG.
47 is a delay difference latch unit, 48 is a clock delay difference comparison unit,
49 is a clock delay difference-set value comparison unit, 51 is a clock selection unit, and 52 is a clock selection unit based on RSSI level. The other components are the same as those used in any of FIGS. 2 to 8 described above, and are denoted by the same reference numerals.

In FIG. 10, each of the branch recovered clocks is input to the clock delay difference quantizer 21, and the obtained delay difference data is output to the delay difference latch 47 and the clock delay difference comparator 48. The delay difference latch unit 47
The delay difference data before the clock is output to the clock delay difference comparison unit 48.

The clock delay difference comparing section 48 outputs a difference between the respective delay difference data. Clock delay difference-set value comparison unit 4
9 indicates that the difference output from the clock delay difference comparing section 48 is
When the difference exceeds the set value, the alarm data is output to the clock selector 51 when the difference exceeds the set value.

The clock selector 51 selects the large-level clock selected by the clock selector 52 when the alarm data is supplied, and outputs the selected clock as a composite clock. When the alarm data is not supplied, the composite clock output from the clock synthesizer 14 is output. Select and output.

According to such a configuration, the clock of the branch performing the most reliable reproduction can be used. Next, FIG. 11 illustrates the RSSI detection unit and the RSI shown in FIG.
A block configuration diagram in the case where an averaging circuit is connected between the SSI level comparison unit and the SSI level comparison unit will be shown and described.

As shown in FIG. 11, averaging circuits 53a and 53b updated by the reproduction clock of each branch are connected between the RSSI detectors 5 and 6 and the RSSI level comparator 13. . Averaging circuits 53a, 53b
The averaging stage number is arbitrarily set according to the average stage number setting value, the averaging corresponding to the arbitrary average stage number is performed for the RSSI level, and the result is output to the RSSI level comparison unit 13.

According to such a configuration, the RSSI level comparison unit 13 performs comparison using the averaged value, thereby absorbing fluctuations and variations due to indefinite factors such as detection accuracy and noise, and providing a stable RSSI level. Can be compared. Here, as the average number of stages, it is necessary to follow an external factor in the fluctuation of the RSSI level.
For example, it must be able to detect fading and the like. By using a value determined by system factors for the average number of stages, a highly accurate RS
SI level data can be obtained.

Next, FIG. 12 shows a block diagram of a first internal configuration example of the averaging circuit 53a or 53b shown in FIG. 12, 54a-54
f is a delay unit, 55a to 55g are coefficient multipliers, 56a to 5
6f is an adder / subtracter, 57 is a divider, and 58 is an average stage number setting holding unit.

The output terminal of the RSSI detector 5 or 6 is connected to the input terminal of the first-stage delay unit 54a and one input terminal of the coefficient multiplier 55a, and the output terminal of the first-stage delay unit 54a is connected to two stages. The output terminal of the second-stage delay unit 54b is connected to one input terminal of the third-stage delay unit 54c and the coefficient multiplier 55c.
Second stage coefficient multiplier 55a and second stage coefficient multiplier 55b
Are connected to both input terminals of the third-stage adder / subtractor 56a, the output terminal of the third-stage delay unit 54c is connected to one input terminal of the fourth-stage delay unit 54d and the coefficient multiplier 55d, and , 3
The output terminal of the coefficient multiplier 55 in the stage and the output terminal of the adder / subtractor 56a are connected to both input terminals of the adder / subtractor 56 in the fourth stage. The connection with the terminal is configured in n stages, and the output terminal of the delay unit
The n-th stage coefficient multiplier 55 is added to the (+1) th stage coefficient multiplier 55.
And the output terminal of the adder / subtractor 56 are connected to both input terminals of the adder / subtractor 56e of the (n + 1) th stage, and the output terminals of the coefficient multiplier 55g and adder / subtractor 56e of the (n + 1) th stage are connected to the adder / subtractor 56f of the (n + 2) th stage. Are connected to both input terminals.

Further, the output terminal of the average stage number setting holding unit 58 is connected to the other input terminals of the coefficient multipliers 55a to 55g.
The output terminal of the adder / subtractor 56f of the (n + 2) th stage and the output terminal of the average stage number setting holding unit 58 are connected to both input terminals of the divider 57, and the output terminal of the divider 57 is connected to the RSSI level comparing unit 13 shown in FIG. Is connected to the input terminal of

That is, the RSSI level output from the RSSI level detector 5 or 6 is input to the delay unit 54a and the coefficient multiplier 55a, and is set in the average stage number set value holding unit 58 in the coefficient multiplier 55a. The average stage number setting value is given, and multiplication is performed.

Further, each of the coefficient multipliers 55b to 55b in the second and subsequent stages
5g, each of the delay units 54a to 54f is provided with a delay corresponding to one cycle of the detection timing of the RSSI level.
SI level data is sequentially provided. These RSSI level data delayed by one cycle are supplied to coefficient multipliers 55b to 55b.
g, the result of the multiplication with one step difference is added / subtracted by each of the adders / subtractors 56a to 56f, and the result of addition / subtraction and the average stage number set value are divided by a divider 57. The division result is output to the RSSI level comparing unit 13 as the RSSI level.

In other words, the delay units 54a to 54f are connected in series to the output of the RSSI level detection unit 5 or 6 to have the average stage number set value, that is, the average stage number minus one, so that the period is equal to the RSSI level detection period. Have a time delay. The outputs of the delay units 54a to 54f are multiplied by a coefficient corresponding to the average number of stages.
5a to 55g are provided.

The RSSI level multiplied by a constant value by the coefficient multipliers 55a to 55g is equal to the coefficient multiplier 55a.
Adders / subtractors 56a to 56f provided at the output terminals of
All the coefficient multipliers 55a
After the outputs of .about.55 g have been added, division is performed by the divider 57 and normalized.

The divisor given to the divider 57 and the multiplier of the coefficient multipliers 55a to 55g are determined so that the value obtained by dividing the sum of the multipliers by the divisor becomes 1. Therefore, the coefficient multiplier 55
These values are determined in consideration of the arithmetic digits of a to 55g and the adders / subtractors 56a to 56f.

Specifically, the divider 57 can be eliminated by using decimal numbers for the coefficient multipliers 55a to 55g and setting the divisor to 1. Alternatively, by giving a margin to the digits of the operation and setting the divisor of the division to a value equivalent to the number of additions, the coefficient multiplier 55
The multipliers of a to 55g are set to 1 and coefficient multipliers 55a to 55g
Can be excluded. Further, according to this configuration, since the RSSI level data is updated one by one, a moving average can be obtained, and highly accurate, continuous averaged data can be obtained.

Next, FIG. 13 shows a block diagram of a second internal configuration example of the averaging circuit 53a or 53b shown in FIG. However, the averaging circuit 53a or 53b shown in FIG. 13 is for averaging the RSSI level “2 n stages”, and the same reference numerals are given to the same components as those used in FIG. In FIG. 13, 59
a to 59j denote subtracters with an output unit 1-bit shift function;
0 is a selector.

That is, the delay terminals 54a to 54i are provided at the output terminals of the RSSI level detectors 5 or 6 of each branch, and the adder / subtractors 59a to 59 having a 1-bit right shift function at the output units.
9j is provided. Each of the first-stage adder / subtractors 59a to 59d
In each of the delay units 54a to 54i, RSSI level data given a delay corresponding to one period of the RSSI detection timing is input, and addition and subtraction are performed.

The result of the first-stage addition / subtraction is further added / subtracted by each of the adder / subtractors 59e to 59j in a plurality of subsequent stages. These adders / subtractors 59a to 59j and delay units 54a to 54
i is connected by the number of stages required for integration. The output result of the first adder / subtracter in each stage is input to the selector 60.
Then, the selector 60 integrates one of the outputs of the respective adders / subtractors according to the value of the average stage number set value holding unit 58 and outputs the result to RS
It is configured to output as SI level.

In other words, the outputs of the RSSI level detectors 5 or 6 are provided with delay units 54a to 54i in series with the number of the maximum average stages minus one, so as to have a delay time equal to the RSSI level detection cycle. . In addition, adders / subtractors 59a to 59d with 1-bit right shift are provided at the outputs of the delay units 54a to 54i so as to sandwich one delay unit.

Two of the adders / subtractors 59e to 59g connected to the adder / subtractors 59a to 59d are paired, and connected to adders / subtractors 59h to 59i in the next stage to output data. The adders / subtractors 59a to 59j add two inputs and, when outputting the result, output the other bits excluding the least significant bit in binary notation, thereby performing a right shift by one bit, equivalently. Divide by two.

In this manner, the adders / subtractors 59a to 59j take the average of each of the two outputs and output the result to the next stage. In this manner, an average of two averages is obtained in the first stage, an average of four is obtained in the second stage, and an average result of 2 n is obtained in the nth stage.

Out of the layers of the adders / subtractors 59a to 59j, the output of each layer is input to the selector 60 one by one. The selector 60 selects and outputs one from the output of each layer according to the value indicated by the average stage number setting value holding unit. The selector 60 directly feeds the RSSR without passing through the delay units 54a to 54i.
By also inputting data from the I-level detection unit 5 or 6, it is possible to perform averaging 2 n times (n is an arbitrary value from 0 to a positive integer) as the average number of times. This can be realized by the device 59 and the selector 60, and the configuration becomes easy.

Next, FIG. 14 is a block diagram showing the configuration of the burst slot corresponding synthesized clock generation unit in the clock synthesis unit shown in FIG. In FIG. 14, reference numeral 61 denotes a clock synthesizing control unit (delay detection or the like);
Denotes a memory, and 63 denotes a burst control signal generator for generating a slot designation signal, a memory read timing signal, and a memory write timing signal.

The count state of the clock generation counter 23 is written or loaded into the memory 62 indicated by the slot designation signal at the timing of the memory write timing signal of the burst control signal generator 63. The clock generation counter 23 reads the written count state from the memory 62 indicated by the slot designation signal at the timing indicated by the memory read timing signal, and loads the signal into the clock generation counter 23. To be configured.

In such a configuration, since each burst signal has a clock at a different frequency and phase for each burst in the time division multiplex communication, synthesized clock information corresponding to each burst is stored in the memory 62. Keep it.

The memory 62 reads the block for the slot of the memory 62 indicated by the slot designation signal at the timing including the phase indicated by the memory write timing signal. When the stored information is to be extracted in the predetermined slot, the information is obtained from the block for the previous slot of the memory 62 indicated by the slot designation signal.
Clock information is supplied to the clock generation counter 23 at the timing indicated by the memory read timing signal.

The clock generation counting section 23 performs clock synthesis using the information as an initial value. It is assumed that the memory read timing signal and the memory write timing signal are externally phase-synchronized. These signals are generated by the burst control signal generation unit 63 using an external reference timing signal, and output to the memory 62 and the clock generation count unit 23. As a result, even in the case of a burst signal that is not continuous, clocks can be synthesized, and a clock corresponding to each slot can be generated.

Next, FIG. 15 shows the memory 6 shown in FIG.
2 is shown in the block diagram of FIG. In FIG. 15, reference numeral 64 denotes a clock holding counter for slot 0, 65 denotes a clock holding counter for slot 1, 6
6 is a clock holding counter for slot m, 67 is a load signal mask for slot 0, 68 is a load signal mask for slot 1, 69 is a load signal mask for slot m, 70 is a decoder, and 71 is a selector. , These elements constitute the memory 62.

That is, the count state (synthesized clock) of the clock generation counter 23 is input to each slot clock phase holding counter 64, 65, 66 as load data. Also, a clock generation counter 2
The quantization high-speed clock synchronized with 3 is input as a counting clock of each of the slot holding counting units 64, 65, and 66. On the other hand, the slot designating signal output from the burst control signal generating section 63 shown in FIG. 14 is decoded by the decoder 70 and becomes a load mask signal, and the load signal masking sections 67, 68, and 6 of predetermined slots are provided.
Enter 9

Further, since signals in slots other than the slot where loading is performed are masked by the load mask signal, when the memory write timing signal is input to the load signal masking sections 67, 68 and 69, the masking is performed. Other signals are output. This signal is input to each slot clock phase holding count unit 64, 65, 66 and used as a load timing signal.

The output signal of the decoder 70 is input to the selector 71 as the output of each slot clock phase holding count unit 64, 65, 66 and a switching control signal. Based on this signal, the outputs of the clock phase holding counters 64, 65, and 66 of the predetermined slot are selected and output.

This output signal is input to the clock generation counter 23. Further, a memory read timing signal is also input as a control signal, and the clock generation count unit 23 loads data by the signal, and the selector 71
The signal output from the selector 71 is held in one of the clock phase holding count units 64, 65, and 66 selected by the clock phase holding count unit 64, 65, or 66. The signal output from the selector 71 is set to the initial count state of the clock generation counter 23 to generate a synthesized clock.

In such a configuration, the count phase of the clock generation counter 23 is passed to each slot clock holding counter 64, 65, 66 as load data. In each slot clock holding count unit 64, 65, 66, the load signal mask unit 67, 68,
Loading is performed for the slot in which the memory write timing signal from 69 has been generated.

The memory write timing signal is input to the load signal mask units 67, 68, and 69, and only the slot indicated by the decoder 70 that has converted the slot designation signal is used.
Clock holding counters 64 and 6 without being masked
5, 66 are output to the designated block corresponding to the slot, and are loaded into the clock holding count unit.

Here, the memory write timing signal is
Neither the phase nor the frequency need be synchronized with other signals, and they can be used at any timing except when the slot designation signal changes.

The slot clock holding counter 64, 65 or 66 indicated by the slot designation signal starts counting in the same phase state as the clock generating counter 23 when the memory write timing signal is generated. After the disappearance of the timing signal, the counter ripple carry is fed back so that the self-running operation is performed until the next timing signal is generated, and the same phase state as that of the clock generation counter 23 is maintained.

In this way, the phase state of each slot is held in the slot holding count units 64, 65, 66. When reading the phase information held by the clock generation counting unit 23, a memory read timing signal is input to the selector 71 via the clock generation counting unit 23.

As a result, the count values of the holding counting sections 64, 65 and 66 of the predetermined slots are selected by the selector 71 and output to the clock generating counting section 23. When a count load signal (for reading) is generated, the clock generation counter 23 takes in the signal output from the selector 71 as a load signal and counts the signal as an initial value.

As a result, the phase becomes the same as that of the counter of the clock holding counting unit selected as the burst slot designation signal. Therefore, by generating the memory read timing signal at the switching point of the burst, data reproduction or the like can be performed using a synthesized clock whose timing is correct from the start point of the slot. The memory read timing signal does not need to be synchronized with the memory write timing signal in phase, timing, and the like, and can be generated at any timing. In this way, a clock synchronizing with a non-continuous received signal can be synthesized, and correct data reproduction can be performed. Further, there is no need to externally manage the phase of the timing signal, so that the configuration can be made easily.

Next, FIG. 16 shows a block diagram of a third example of the internal configuration of the averaging circuit 53a or 53b shown in FIG. In FIG. 16, 72a to 72
d is a selector, 73a to 73d are delay units, and 74 is a memory. Reference numeral 500 denotes an arithmetic unit, which is shown in FIG.
Has the same configuration as the averaging circuit shown in FIG.

Each selector 72a-72d and each delay unit 73
a to 73d are alternately connected in series between the RSSI level detection unit 5 or 6 and the arithmetic unit 500, and the output terminals of the selectors 72a to 72d are connected to the arithmetic unit 500. The other input terminals of the delay units 73a to 73d are configured to receive the synthesized clock described above.

The output data of the memory 74 and the RSSI level slot information read timing signal for controlling the switching are input to the selectors 72a to 72d. The calculation result of the calculation unit 500 is output as an averaged RSSI level and is input to the memory 74 at the same time. Memory 7
In 4, an RSSI level slot information writing timing signal and a slot designation signal are input for holding timing of the averaged RSSI level, and the timing indicated by the RSSI level slot information writing timing signal in the memory 74 corresponding to the designated slot. Is configured to perform writing.

In such a configuration, the memory 74 stores R
This is a block for holding an average value at the end of an SSI-level burst slot. This is the RSSI level detector 5,
6 outputs the integrated value as an averaged RSSI level in the integrating circuit provided in the output unit 6 and simultaneously supplies the RSSI level to the memory 74.

In the memory 74, the average value of the RSSI level before the end of the slot and the switching to another slot is stored by the RSSI level slot end information write timing signal for the block indicated by the slot designation signal.

The stored information is output to selector 72 at the timing indicated by the RSSI level slot start information read designation signal when the stored slot starts next.

When the selector 72 is performing the integration of the RSSI level, the selector 72 detects the RSSI level.
Alternatively, a signal from the delay unit 73 is output to the arithmetic unit 500 or the selectors 72a to 72d and the delay units 73a to 73d.

When the RSSI level slot start information read timing signal is generated, the value of the block indicated by the slot designation signal
3a to 73d to the arithmetic unit 500.

As a result, the information held by all the delay units 73a to 73d becomes equal, so that the average of these values becomes equal, and the continuity is provided to the burst information before a predetermined slot. Can be.

Further, for each of the delay units 73a to 73d,
After giving the average value from the memory 74, the selectors 72a-72
Switch 72d for normal averaging and use the new RS
By adding the SI level, the average of the slot can be used from the beginning. Further, since this configuration is a method of giving the average of a predetermined slot of the previous burst to the delay device, it can be similarly used for various calculation methods, and continuity can be maintained.

Next, with reference to FIG. 17, a description will be given of a radio unit of a diversity receiving apparatus for correcting the delay time between diversity receiving branches according to the second embodiment. In FIG. 17, reference numeral 100 denotes a receiving antenna unit in the first branch, 1
01 is the receiving antenna section in the second branch, 102 is the first antenna
The receiving high-frequency section in the branch, 103 is the receiving high-frequency section in the second branch, 104 is the frequency converting section in the first branch, 105 is the frequency converting section in the second branch, and 106 is the baseband filter in the first branch. , 107 is the second
A baseband filter in the branch; 108, an RSSI detector in the first branch; 109, an RSI in the second branch;
SSI detection unit, 110 is a limiter amplifier in the first branch, 111 is a limiter amplifier in the second branch, 112
Is an A / D converter in the first branch, 113 is an A / D converter in the second branch, 114 is a phase detector in the first branch, 115 is a phase detector in the second branch,
Reference numeral 116 denotes a clock recovery unit in the first branch, and 117 denotes a clock recovery unit in the second branch.

Reference numeral 118 denotes an RSSI level comparison unit, 119 denotes a data phase synthesis control unit, 120 denotes a clock delay difference detection unit, 121 denotes a clock synthesis count setting unit, 122 denotes a quantization high-speed clock, 123 denotes a synthesized clock counter, 124 is a data phase difference detection unit, 125 is a data phase synthesis unit, 126 is a data processing unit, 127 is a forward clock detection unit, 128 is a load timing generation unit, 129 is a reception signal frequency setting unit, and 130 is a frequency conversion oscillator. is there.

This diversity receiving apparatus has two branches as receiving sections, each of which has a separate receiving circuit, and each receiving antenna 100, 10
1 is input to each phase detector 114,
At 115, it is detected and processed as data.

Each of these individual receiving units has a clock recovery unit 116 that follows the signal input to each branch,
117, and reproduces a clock with respect to a signal having an external delay and a delay of an internal circuit (the baseband filters 106 and 107, etc.). The data detected by the receiving circuit is supplied to a data phase synthesizing unit 125 and a data phase difference detecting unit 124.
And performs processing such as maximum ratio combining, and the like.
26.

The RSSI detector 10 of each branch
8 and 109 are converted into twisted digital values by A / D converters 112 and 113,
The data is output to the I-level comparison unit 118, and reception level difference data between branches is obtained. The reception level difference data is used for the maximum ratio synthesis of the reproduced data by the synthesis control unit 119,
Then, the clock is output to the clock synthesizing count setting unit 121 for clock synthesizing.

On the other hand, the clock recovery section 116 of each branch
The clock reproduced at 117 is output to the clock delay difference detection unit 120 for clock synthesis, and delay difference data at each branch is obtained. This data is output to the clock setting count setting unit 121, and a count setting value corresponding to the RSSI level difference is generated. In accordance with the count setting value, a synthesized clock is generated by the synthesized clock counter 123, and is output to the data phase synthesizing unit 125 and the data processing unit 126, and is used as the maximum ratio synthesizing timing and the like.

The initial timing of the count of the synthesized clock counter is advanced by either the synthesized clock or the reproduced clock in each branch, and is selected by the clock detection unit 127. Output to counter 123.

According to such a configuration, since each branch has a clock recovery function and each branch can perform detection, data necessary for synthesizing phase data can be generated. It is possible to generate a clock that can be used to overwrite data, and it is possible to prevent deterioration of received data due to a delay difference between branches as timing when the data phase combining unit 125 performs processing such as maximum ratio combining.

In addition, since the degree of ratio influence on each branch is changed according to the RSSI level, when the reception level decreases and the input signal becomes unstable, the malfunction may be caused by the data of the branch where the combined clock cannot be received. Can be prevented.

By setting the change in the set value given to the synthesized clock counter to be equal to or less than the value allowed for the clock jitter, the instantaneous interruption of the clock due to clock jitter and switching is suppressed, and the loss of reproduced data is prevented. A stable clock can be supplied.

Further, since the clocks reproduced by the independent clock reproducing unit are synthesized and the RSSI level is used for setting the ratio, there is no need to feed back to the receiving unit, and the circuit can be easily formed.

Next, a count value setting type clock synthesizing unit based on a branch having a small transmission path delay of the diversity receiver according to the second embodiment will be described with reference to FIG.

In FIG. 18, reference numeral 131 denotes a clock rise detecting section of the first branch, 132 denotes a clock rising detecting section of the second branch, 133 denotes a counter for detecting a clock delay difference of the first branch, and 134 denotes a clock of the second branch. The delay difference detection counter 135 has a first branch delay difference latch section, 136 has a second branch delay difference latch section, 137 has a delay difference comparison section, and 138 has a delay difference selection section.

139 is an RSSI level difference-ratio conversion logic unit, 140 is an RSSI level subtraction unit (level comparison between branches), 141 is a ratio inversion unit (subtracted from the frequency division ratio), 14
2 is a ratio selector, 143 is a clock rise selector,
144 is a delay difference-ratio ratio multiplication unit, 145 is an addition / subtraction step holding unit, 146 is a BTR reference clock, 147 is a count setting value latch unit, 148 is a count value subtraction unit (comparison), and 149 is a subtraction result most significant bit selection unit. , 150 is a subtraction result absolute value converter, 151 is an addition / subtraction value calculator, 15
2 is a count set value addition / subtraction unit, 153 is a counter load timing generation unit, 154 is a clock generation count unit, and 155 is a clock shaping unit.

The count value setting type clock synthesizing section shown in FIG. 18 inputs the recovered clock in each branch to the clock rising detecting sections 131 and 132, detects the rising timing of the clock by the BTR reference clock, and outputs the timing data. As a load timing signal for the clock delay difference detection counters 133 and 134.

Clock delay difference detecting counters 133, 1
34 is the start timing of the rising timing, and B
It counts using the TR reference clock 146. This count value is latched at the clock rising timing of the other side (delay difference latches 137 and 136), and the latched value is used as the delay difference.

The delay difference is calculated by the delay difference comparing section 137.
The difference is determined from the half period of the symbol period, a branch selection signal having a small delay difference is generated, and is input to the delay difference selection unit 138, the ratio selection unit 142, and the delay difference selection unit 138.
The delay difference selection unit 138 selects one of the data of the delay difference latch units 135 and 136 that has detected the delay difference for each branch, and inputs the data to the delay difference / ratio ratio multiplication unit 144 as delay difference data.

The clock rise selection section selects one of the branch clock rise timing data based on the branch select signal based on the result of the delay difference comparison.
It is input to the counter load timing generator 153.

On the other hand, the RSSI level data detected in each branch is input to the RSSI level subtraction section 140,
The magnitudes of the levels are compared, data of magnitudes and differences are generated, and input to the RSSI level difference-ratio conversion logic unit 139.

RSSI level difference-to-ratio conversion logic section 139
In this example, the data is converted into a plurality of stages from 100% to 0% according to the RSSI level difference to obtain ratio data. Ratio data is RS
In order to ensure the consistency between the SI level magnitude result and the selected branch based on the delay difference comparison, 100
Calculate the value subtracted from%, and select the original value and this result as a ratio selection 1
The data is selected at 42 and is set as branch ratio data equal to the delay difference data and the clock rising data.

The ratio data is input together with the delay difference data to the delay difference-ratio ratio multiplication unit 144 to generate a count value according to the ratio, and to the count value subtraction unit 148. The count value subtraction section 148 compares the count value held in the count setting value latch section 147 with the count value, and compares the large or small data of the comparison result with the most significant bit selection section 149 of the subtraction result.
And the error amount of the comparison result is subtracted from the absolute value conversion unit 1 of the subtraction result.
Enter 50.

The subtraction result absolute value conversion section 150 inputs the value converted into the absolute value to the addition / subtraction section calculation section 151. The addition / subtraction unit calculation unit 151 limits the value indicated by the addition / subtraction step holding unit as an upper limit, generates addition / subtraction data for the count setting value, and supplies the count setting value addition / subtraction unit 152 with the subtraction result most significant bit selection unit 149. Input together with the code data.

The count set value adding / subtracting unit 152 adds and subtracts these values to and from the count set value latch unit 147 and holds the count set value latch unit 147. The held data is performed for each symbol or at an arbitrary time. The data of the count set value latch unit 147 is input to the clock generation count unit 154.

The clock generation counting unit 154 receives the initial count timing from the counter load timing generation unit 153, performs counting while correcting the BTR reference clock 146 with the count set value, and the clock shaping unit 155. Remove the hazard and use it as a synthesized clock.

According to such a configuration, it is possible to use the branch clock with the smaller or larger delay amount of each branch as a reference, and the reference is determined regardless of the RSSI level detection timing. The ratio conversion can be performed regardless of the delay difference detection timing. Further, the jitter speed of the synthesized clock can be changed by changing the addition / subtraction step. Since the output of the clock generation counter is not fed back to the set value, the configuration is simplified.

Next, a count value setting type clock synthesizing unit based on a branch having a high RSSI level of the diversity receiver according to the second embodiment will be described with reference to FIG.

In FIG. 19, 131 is a clock rise detecting section of the first branch, 132 is a clock rising detecting section of the second branch, 139 is an RSSI level difference-to-ratio conversion logic section, and 140 is an RSSI level subtraction section (between branches). 145 is an addition / subtraction step holding unit, 146 is a BTR reference clock, 147 is a count set value latch unit, 148 is a count value subtraction unit, 149 is the most significant bit selection unit of the subtraction result, and 150 is a subtraction result absolute value conversion unit , 151 is an addition / subtraction value calculation unit, 152 is a count set value addition / subtraction unit, 153 is a counter load timing generation unit, 154 is a clock generation count unit, 155 is a clock shaping unit, 156 is an RSSI level high side branch selection unit, and 157 is RSSI level low side branch selector, 15
8 is a clock delay difference detection counter, 159 is a delay difference latch unit, and 160 is a delay difference-ratio ratio multiplication unit.

The count value setting type clock synthesizing section shown in FIG. 19 inputs the reproduced clock in each branch to the clock rising detecting sections 131 and 132, detects the rising timing of the clock with the BTR reference clock, and outputs the timing data. To the RSSI level high branch side selection unit 156 and the RSSI level low branch side selection unit 157.

The RSSI level data detected in each branch is input to the RSSI level subtraction unit 140,
The magnitudes of the levels are compared to generate data of magnitude and difference, and the RSSI level difference-to-ratio conversion logic unit 139 and R
The signal is input to the SSI level high branch side selection unit 156 and the RSSI level low branch side selection unit 157.

RSSI level high branch side selector 156
Then, the rising timing of the branch having the higher level is selected based on the result of the RSSI level operation, and is input to the clock delay difference detection counter 158 and the counter load timing generator 153. Further, the RSSI level low branch side selector 157 selects the rising timing of the higher level branch based on the RSSI level operation result, and inputs it to the delay difference latch 159.

The clock delay difference detection counter 158 counts using the BTR reference clock 146 with the rising timing as a start point. This count value is latched at the clock rising timing by the delay difference latch 159, and this value is used as delay difference data.

The RSSI level difference-ratio conversion logic unit 1
In step 39, the data is converted into a plurality of stages from 100% to 0% in accordance with the RSSI level difference to obtain ratio data. The ratio data, together with the delay difference data, is input to the delay difference-ratio ratio multiplication unit 160 to generate a count value according to the ratio, and input to the count value subtraction unit 148 to generate a synthesized clock as shown in FIG. You.

According to such a configuration, either a high-level branch or a low-level branch can be used as a reference by using a large or small signal of the RSSI level. Part of the difference detection circuit and the ratio conversion circuit can be reduced, and simplification can be achieved.

Next, a convergence phase value comparison type (feedback comparison) clock synthesizing unit based on a branch having a high RSSI level in the diversity receiver according to the second embodiment will be described with reference to FIG.

In FIG. 20, reference numeral 131 denotes a clock rising detector of the first branch, 132 denotes a clock rising detector of the second branch, and 139 denotes an RSSI level difference.
A ratio conversion logic unit, 140 is an RSSI level subtraction unit (level comparison between branches), 145 is an addition / subtraction step holding unit,
146 is a BTR reference clock generation unit, 155 is a clock shaping unit, 156 is an RSSI level high side branch selection unit,
157 is an RSSI level low side branch selection unit, 158 is a clock delay difference detection counter, 159 is a delay difference latch unit, 160 is a delay difference-ratio ratio multiplication unit, 161 is a count value (phase) comparison unit, 162 is an addition / subtraction value Calculator, 163
Is a clock generation counter, 164 is a counter load timing generator, 165 is a phase data generator, 166
Is a convergence phase generation count unit.

The convergence phase value comparison type (feedback comparison) clock synthesizing section shown in FIG.
32, and the rising timing of the clock is set to BT
Detected by the R reference clock and the timing data
The signal is input to the SSI level high branch side selection unit 156 and the RSSI level low branch side selection unit 157.

The RSSI level data detected in each branch is input to the RSSI level subtraction section 140,
The magnitudes of the levels are compared to generate data of magnitude and difference, and the RSSI level difference-to-ratio conversion logic unit 139 and R
The signal is input to the SSI level high branch side selection unit 156 and the RSSI level low branch side selection unit 157.

RSSI level high branch side selector 156
Then, the rising timing of the branch having the higher level is selected based on the result of the RSSI level operation, and is input to the clock delay difference detection counter 158 and the counter load timing generator 153. The RSSI level low branch side selector 157 selects the rising timing of the higher level branch based on the RSSI level operation result, and inputs it to the delay difference latch 159.

The clock delay difference detection counter 158 counts using the BTR reference clock 146 with the rising timing as a starting point. The count value is latched by the delay difference latch unit 159 at the clock rising timing, and this value is delayed. Assume difference data. In the RSSI level difference-ratio conversion logic unit 139, the RSSI
The data is converted into a plurality of stages from 100% to 0% according to the I level difference to obtain ratio data.

The ratio data is input to the delay difference-ratio ratio multiplying section 160 together with the delay difference data to generate a count value according to the ratio, input to the convergence phase generation counting section 166, and output the convergence timing signal (phase). Is generated. The convergent phase signal is input to the count value (phase) comparing section 161.

The phase comparing section 161 compares the clock phase value generated by the phase data generating section 165 with the converged phase based on the count value output from the clock generating count section 163, and compares the converged phase with the synthesized clock. Phase advance /
The direction of the delay and the amount of the difference are detected, and an addition / subtraction value calculation unit 162 is detected.
Enter

The addition / subtraction value calculation section 162 generates a load value with the value indicated in the addition / subtraction step holding section 145 as an upper limit, and uses it as correction data when updating the data of the clock generation counting section. Counter load timing generator 1
Reference numeral 64 generates a load timing signal at a point of a specific count value of the clock generation counter 163, and updates the counter. The phase data generator 165 converts the count value into a form that can be compared in phase and sends it out. The clock generation unit 155 rewrites the bits required for the count value with the BTR reference clock and outputs the bits as a composite clock.
According to this embodiment, the point of the ratio based on the RSSI level is given to the subsequent simplified digital PLL as a convergent phase, and the convergent phase can be gradually changed to the convergent phase at a designated step, and a lack of clock or the like can be achieved. A sudden change can be prevented. Further, the convergence phase generator and the clock generation digital PLL are independent, and the convergence phase can be easily controlled.

Next, with reference to FIG. 21, a description will be given of the clock shift amount setting section in the convergence phase value comparison type clock synthesizing section shown in FIG. 20 of the diversity receiver according to the second embodiment.

In FIG. 21, 131 is a clock rise detecting section of the first branch, 132 is a clock rising detecting section of the second branch, and 139 is an RSSI level difference.
Ratio conversion logic unit, 140 is an RSSI level subtraction unit (level comparison between branches), 146 is a BTR reference clock,
55 is a clock shaping unit.

156 is an RSSI level high side branch selector, 157 is an RSSI level low side branch selector, and 15
8 is a clock delay difference detection counter, 159 is a delay difference latch unit, 160 is a delay difference-ratio ratio multiplication unit, 161 is a count value (phase) comparison unit, 164 is a counter load timing generation unit, and 165 is a phase data generation unit , 166 is a convergence phase generation count unit, 167 is a load data generation unit (+, 0,-), 168 is a reference clock frequency divider, a selection unit,
Reference numeral 169 denotes an enable signal generation unit, and 170 denotes a clock generation count unit.

The clock shift amount setting unit shown in FIG. 21 generates the convergent phase as described with reference to FIG. 20, and inputs the convergent phase from the convergent phase generation count unit 166 to the count value (phase) comparing unit 161.

The count value (phase) comparing section 161 compares the convergent phase point with the synthesized clock phase, determines whether the phase is equal or advanced or delayed, and inputs the comparison result to the load data generating section. The load data generation unit 167 inputs any one of “0”, “constant value of +”, and “constant value of −” to the clock generation counting unit 170 as load data according to the comparison result.

The count value of the clock generation counter 170 generates counter load timing and phase data as shown in FIG. The clock generation counter 170 has an enable input and counts according to the state of the enable signal.

The enable signal is divided by the reference clock frequency divider / selector 168 to divide the clock of the BTR reference clock 146, the result is selected by the maximum clock displacement setting data, and the result is input to the enable signal generator 169. The enable signal generator 169 performs a logical sum with the external compulsory control and performs count control as an enable signal.

According to such a configuration, the maximum shift amount of the clock can be set, and since the speed of the reference clock does not change in the clock generation counter, the clock can be generated by the synchronous circuit.

Furthermore, by using an enable signal obtained by arbitrarily dividing the reference clock, the configuration is simplified, the control can be performed by the synchronization signal, and the configuration of the load data generation unit can be simplified.

Next, with reference to FIG. 22, a description will be given of the alarm stop control unit of the first example in the convergence phase value comparison type clock synthesizing unit shown in FIG. 20 of the diversity receiving apparatus of the second embodiment.

In FIG. 22, 131 is a clock rise detecting section of the first branch, 132 is a clock rising detecting section of the second branch, and 139 is the RSSI level difference.
Ratio conversion logic unit, 140 is an RSSI level subtraction unit (level comparison between branches), 146 is a BTR reference clock,
55 is a clock shaping unit.

Reference numeral 156 denotes an RSSI level high side branch selector, 157 denotes an RSSI level low side branch selector, and 15
8 is a clock delay difference detection counter, 159 is a delay difference latch unit, 160 is a delay difference-ratio ratio multiplication unit, 161 is a count value (phase) comparison unit, 164 is a counter load timing generation unit, and 165 is a phase data generation unit , 166 is a convergence phase generation count unit, 167 is a load data generation unit (+, 0,-), 168 is a reference clock frequency divider, a selection unit,
Is an enable signal generator, 170 is a clock generation counter, 171 is a synthesis inhibition delay difference detector, and 172 is an RS
An SI level sensitivity point or less detection unit, 173 is an RSSI level sensitivity point or less detection unit, 174 is a clock synthesis alarm generation unit, and 175 is a convergence phase selection unit.

The alarm stop control unit shown in FIG.
As shown in FIG. 20, a convergence phase is generated from a clock delay difference between branches. Here, it is input from the delay difference latch unit 159 to the synthesis inhibition delay difference detection unit 171. The combining prohibition delay difference detecting section 171 inputs a detection signal to the clock combining alarm 174 when the combining prohibition delay difference setting data has a delay difference equal to or greater than this delay difference.

In the case where the RSSI level is lower than the sensitivity point, the RSSI level data is input to the RSSI level sensitivity point lower detection units 172 and 173 in each branch and compared with the sensitivity point RSSI level setting data. , The detected data to the clock synthesis alarm generator 1
Enter 74.

The clock synthesizing alarm generating section 174 takes the logical sum of the synthesizing prohibition detection signal due to the delay difference and the detection signal below the sensitivity point, and when any of them is generated, inputs it to the convergence phase selecting section 175 as the synthesizing prohibition alarm. The convergence phase selection unit 175 receives the convergence phase based on the RSSI level and the clock rise detection timing of each branch. If an alarm occurs, the clock rise detection timing of one of the branches with the higher RSSI level is selected, and the digital PLL is selected. And a clock is generated as shown in FIG.

According to such a configuration, when the delay difference between branches increases and relatively exceeds half a cycle, the synthesized clock is prevented from being synthesized at the wrong convergence point, and either of the RSSI levels is prevented. To the branch clock on the higher side.

If the receiving sensitivity is reduced in any branch and falls below the sensitivity point and the recovered clock in that branch becomes an erroneous clock, the sensitivity level is monitored to stop synthesizing the clock, and any one of the RSSI levels is monitored. It is possible to follow a high branch clock, eliminate the influence of a branch clock having a sensitivity level or less, and obtain a stable clock.

Further, since the selecting section is provided for the convergence phase, the clock phase does not become discontinuous due to an instantaneous variation, and the jitter of the synthesized clock after switching is suppressed and stable. Clock is available, RS
It is excellent in compatibility with a diversity system that combines received data at the SI level.

Next, with reference to FIG. 23, a description will be given of a second example of the alarm stop control unit in the convergence phase value comparison type clock synthesizing unit shown in FIG. 20 of the diversity receiving apparatus according to the second embodiment.

In FIG. 23, 131 is a clock rise detecting section of the first branch, 132 is a clock rising detecting section of the second branch, and 139 is the RSSI level difference.
Ratio conversion logic unit, 140 is an RSSI level subtraction unit (level comparison between branches), 146 is a BTR reference clock,
55 is a clock shaping unit.

Reference numeral 156 denotes an RSSI level high side branch selector, 157 denotes an RSSI level low side branch selector,
8 is a clock delay difference detection counter, 159 is a delay difference latch unit, 160 is a delay difference-ratio ratio multiplication unit, 161 is a count value (phase) comparison unit, 164 is a counter load timing generation unit, and 165 is a phase data generation unit , 166 is a convergent phase generation count section, 167 is a load data generation section (+, 0,-), 168 is a reference clock frequency division / selection section,
169 is an enable signal generation unit, 170 is a clock generation count unit, 171 is a synthesis inhibition delay difference detection unit, 172
Is a detection unit below the RSSI level sensitivity point, and 173 is the RSSI level
A level sensitivity point or lower detection unit 174 is a clock synthesis alarm generation unit, and 176 is a reproduced clock selection unit.

The alarm stop control unit shown in FIG.
As shown in FIG. 22, a synthesis prohibition alarm is generated from the clock delay difference between branches and the RSSI level of each branch. This synthesis prohibition alarm is input to the recovered clock selection unit 176 to which the synthesized clock based on the convergence phase based on the RSSI level and the respective branch clocks are input, and a branch clock having a higher RSSI level is selected in the alarm state, and the synthesized clock is output. Output instead.

According to such a configuration, when the delay difference between the branches increases and exceeds a half cycle relatively, even if the synthesized clock is synthesized at the wrong convergence point, either of the RSSI levels is The higher branch clock can be selected and output.

Further, since the clock is switched, the phase is quickly switched by an alarm, and is excellent in compatibility with the diversity scheme for switching received data according to the RSSI level.

Next, with reference to FIG. 24, a description will be given of a burst reception-compatible clock synthesizing unit in the convergence phase value comparison type clock synthesizing unit shown in FIG. 20 of the diversity receiver according to the second embodiment.

In FIG. 24, reference numeral 131 denotes a clock rise detection unit of the first branch, 132 denotes a clock rise detection unit of the second branch, and 139 denotes an RSSI level difference.
Ratio conversion logic unit, 140 is an RSSI level subtraction unit (level comparison between branches), 146 is a BTR reference clock,
55 is a clock shaping section, 156 is an RSSI level high side branch selecting section, 157 is an RSSI level low side branch selecting section, and 158 is a clock delay difference detection counter.

159 is a delay difference latch section, 160 is a delay difference-ratio ratio multiplication section, 161 is a count value (phase) comparison section, 164 is a counter load timing generation section, 165
Is a phase data generation unit, 166 is a convergent phase generation count unit, 167 is a load data generation unit (+, 0,-), 16
8 is a reference clock divider / selector, 169 is an enable signal generator, 170 is a clock generator counter, 178
Denotes a count value (phase) holding memory, and 179 denotes a load data selection unit.

The burst reception compatible clock synthesizing section shown in FIG. 24 generates a synthesized clock from the clock delay difference between branches as shown in FIG. Here, the synthetic clock phase is determined by the write timing of the count value memory when the reception is performed in a burst manner. The write timing of the count value memory stored in the count value (phase) holding memory is the same as that of the current burst until the next burst in the burst reception. Most are generated at the end of a burst to preserve phase. This held count value is input to the load data selection unit 179.

The load data selection unit 179 is also supplied with the initial phase data of the synthesized clock, and receives a digital signal based on the selection signal from the data selection signal generation unit 177.
One of the LL data, the held count value, and the initial phase data of the synthesized clock is selected and input to the clock synthesizing counter 170.

The data selection signal generator 177 generates a load timing signal for the counter from the count value memory read timing signal in order to load the held data at the start of the burst reception. Further, at the initial time, a counter load signal is generated at the initial phase compulsory setting timing to load the initial phase.

At the time of these loads, the PLL loop is cut and forcibly loaded. After the phase has changed, the feedback loop is restored, and the phase is converged to the convergent phase more slowly than the load phase.

According to such a configuration, even when the received data used for generating the clock is received in a burst manner and the clock is disturbed during the time when there is no signal, the original phase is retained and read out quickly by retaining the original phase. A synthesized clock can be obtained.

When the synthesized clock is free running in the initial state, the convergence speed in the initial state can be improved by forcibly reading the initial phase for the convergence for each branch clock.

Next, with reference to FIG. 25, a description will be given of a burst receiving multi-slot compatible clock combining unit in the convergent phase value comparison type clock combining unit shown in FIG. 20 of the diversity receiver according to the second embodiment.

In FIG. 25, 146 is a BTR reference clock, 155 is a clock shaping section, 161 is a count value (phase) comparing section, 165 is a phase data generating section, 167 is a load data generating section (+, 0,-), Reference numeral 180 denotes a combined clock convergence phase generation unit (counting unit or the like), 181 denotes a slot 0 timing mask unit, 182 denotes a slot 0 timing mask unit, and 183 denotes a slot n timing mask unit (n is the number of slots).

184 is a count value (phase) for slot 0
The holding register, 185 is a slot 0 count value (phase) holding register, 186 is a slot n count value (phase) holding register, 187 is a slot 0 load data mask section, 188 is a slot 1 load data mask section, 189 Is the load data mask section for slot n, 1
90 is a data OR unit, 191 is a decoder, 192 is a data selection signal generation unit, 193 is a load data selection unit, 1
Reference numeral 94 denotes a clock generation counter, and 195 denotes a counter load timing generator.

The clock synthesizing unit corresponding to burst reception in the convergent phase value comparison type clock synthesizing unit generates a synthesized clock from the clock delay difference between branches as shown in FIG.
Here, the synthesized clock phase is selected by a signal obtained by converting the slot designation signal by the decoder 191 in the burst reception by a plurality of slots, and the timing mask unit 1
The data is written to the count value holding register for the slot designated by any one of 81 to 183 at the count value memory write timing. Unspecified counter value holding registers are not updated.

The value of the counter value holding register is masked by the decoder output generated from the slot designation signal using the load data masking units 187 to 189, and the result is added by the data OR unit 190 and loaded as load data. The data is input to the data selection unit 193.

That is, the value of the register other than the register designated by the slot designation signal is "0", and the load data of the addition result is the load data only in the designated slot.
Here, the data generation signal generation unit 192 generates a read timing based on the count value memory read timing signal and the counter load timing signal, and inputs the value of the holding register to the clock generation count unit when the count value memory read timing signal is generated. Let P
Disconnect LL loop and force load. Further, after the phase is changed, the feedback loop is restored, and the convergence phase is converged more slowly than the load phase.

According to such a configuration, when a plurality of bursts of received data used for clock generation are received and a clock is reproduced at a specific phase for each burst,
By holding and reading the phase of each slot, a synthesized clock can be obtained quickly.

Next, with reference to FIG. 26, the RSSI level “n-th power of 2” of the diversity receiver according to the second embodiment will be described.
The average part will be described. In FIG. 26, 146 is a reproduced symbol clock generator, 196 is an RSSI detector,
197 to 203 are delay FFs (flip-flops), 2
Numerals 04 to 210 denote an adder 211, a phase shifter, 212 an average stage number set value holding unit, and 213 a selector.

The RSSI level averaging section shown in FIG. 26 detects the reception level by RSSI detection section 196,
The value converted into a digital signal is input to the delay FF 197. The delay FF 197 is a reproduction symbol clock generator 1
46 is adjusted in phase by the phase shifter 211, delayed by one symbol, and input to the delay FF of the next stage.

Each delay FF is updated for each symbol and transmitted to the next stage.
The signal is delayed by seven symbols with respect to the detector 196. The outputs of these delay units are operated by an adder, and the adder 204 calculates the addition result of the 0 symbol delay and the 1 symbol delay,
The adder 205 is a 2-symbol delay and a 3-symbol delay, the adder 206 is a 4-symbol delay and a 5-symbol delay,
07 gives an addition result of 6 symbol delay and 7 symbol delay.

The output of each adder discards the lower one bit and shifts to the right to divide by two. As a result, the average value of two symbols is obtained in each adder.
Of these average results, only the result of the adder 204 is input to the selector 213 as a 2-symbol average. Further, another adder 208 is provided at the output units of the adders 204 and 205, the results are added, and a bit shift is performed at the output, so that an average of four symbols can be obtained.

Similarly, by adding an adder 209 to the outputs of the adders 206 and 207 and performing an arithmetic operation, an average of four symbols is obtained. Only the output of the adder 208 is selected by the selector 213.
To enter. Further, an adder 210 is provided at the outputs of the adders 208 and 209, and an arithmetic operation is performed to obtain an average of eight symbols. The result is input to the selector 213. Selector 21
In the case of 3, one of 1, 2, 4, and 8 symbol averages is selected according to the value indicated in the average stage number setting value holding unit 212,
Output as RSSI level.

According to such a configuration, a moving average at the RSSI level can be obtained, and the number of averaging stages can be set externally. As a result, the RSSI level can be used for the synthesis, the variation (error) of the RSSI level can be suppressed, and the delay time associated with the integration can be reduced and the adjustment can be easily performed when appropriate integration is required. In addition, because of the moving average, it is possible to obtain a correct value without being affected by past fluctuations.

Next, with reference to FIG. 27, the RSSI level shown in FIG. 26 of the diversity receiver according to the second embodiment will be described.
A description will be given of the first example of the RSSI detecting unit for burst reception in the “average unit of 2 n steps”.

In FIG. 27, reference numeral 146 denotes a reproduced symbol clock generator, 196 denotes an RSSI detector, and 197 to 197.
9 is a delay FF, 204, 206 and 208 are adders, 2
14 to 217 are register / detection section input selection sections, 218 is a decoder slot corresponding section, 219 is a timing mask section, 220 is an RSSI level holding register, 221 is a held data mask section, and 222 is a selector.

The RSSI level averaging section shown in FIG. 27 detects the reception level by RSSI detection section 196,
The value converted into the digital signal is input to the delay FF 197, and the averaging operation is performed as shown in FIG.

In FIG. 27, the average number of stages is 1, 2, or 4. In this circuit, the average RSSI level is written into the RSSI holding register 220 at the holding data write timing by masking data other than predetermined data by the timing mask unit 219 using a signal obtained by twisting the slot designation signal into the decoder 218. .

In the written RSSI level data, only the value of a predetermined register is selected by the held data masking unit 221 by the slot designation signal, and the values of the other registers are masked. This data is supplied to the register / detection unit input selection unit 214 by the held data read timing signal.
To 217, and are simultaneously written to the delay FFs 198 to 199. In addition, the normal register / detection unit input selection units 214 to 217 transmit the value of the preceding delay FF to the subsequent stage when the held data read timing signal is not generated,
Take the usual average.

According to such a configuration, when a signal such as a burst signal whose signal level is discontinuous and which does not need to be detected on the time axis is input, or the level is changed between required times, When there is no previous burst, the final average value of the previous burst is obtained as it is by holding the RSSI level value at the end of the previous burst in advance and giving it to all the delay units at the same time in the next burst. The average of the RSSI levels inputted next can be sequentially determined, so that the average value can be continuously obtained even for a temporally discontinuous signal.

Next, referring to FIG. 28, the RSSI level shown in FIG. 26 of the diversity receiver according to the second embodiment will be described.
A description will be given of a second example of the RSSI detecting unit for burst reception in the “average unit of 2 n steps”.

In FIG. 28, 196 is an RSSI detector, 219 is a timing mask unit, 220 is an RSSI level holding register, 221 is a held data mask unit,
23 is a serial-parallel converter (bit), 224 is a shift register, 225 to 228 are mask circuits, 229
Is a decoder (for setting the average number of stages), 230 is an adder, 23
1 is a decoder (corresponding to a slot), and 232 is a bit shift selector.

The RSSI level averaging section shown in FIG. 28 detects the reception level by RSSI detection section 196,
The value converted into a digital signal is converted into a parallel signal for each bit by a serial-parallel converter 223 and input to the shift register 224.

The shift register is prepared in a quantity corresponding to the number of data bits, and the number of shifts is the maximum value of the average number of stages minus one.
And The data is delayed for each symbol by the shift register, and the delayed data is applied to mask circuits 225 to 22.
Enter 6

In the mask circuit, a quantity mask corresponding to the average number of stages is performed by a signal decoded by the decoder 229 based on the average stage number setting signal. That is, when the average stage number is 1, the mask is masked from 226 to 228, when the average stage number is 2, 227 and 228 are masked, and when the average stage number is 4, the mask is not performed. These outputs are input to an adder 230, and the result of the addition is directly shifted by one bit or two bits, and a signal corresponding to the average number of stages is selected by a bit shift selector 232. In this configuration, data is held and read as shown in FIG.

According to such a configuration, the circuit configuration of the adder and the like can be simplified, and the reading of data at the time of burst can be easily performed without the need for switching or the like. Next, FIG.
With reference to FIG. 9, a description will be given of an alarm generation unit for stopping clock synthesis due to an excessive phase difference in the diversity receiver according to the second embodiment.

In FIG. 29, 233 is a clock synthesizing unit, 234 is a clock delay difference detecting unit, 235 is a delay difference latching unit, 236 is a delay difference latching unit, 237 is a delay difference sign comparing unit, and 238 is a delay difference displacement amount detecting unit. 239, a shift amount adder, 240, a clock-synthesizable delay difference setting unit, 24
1 is a clock delay difference-set value comparison unit, 242 is a frequency deviation detection unit, and 243 is an alarm logic adder.

The clock synthesizing stop alarm generator shown in FIG. 29 inputs the delay difference data detected by the delay difference detector 234 to the delay difference latch 235 and further to the delay difference latch 235.

These latch units are updated for each symbol by the synthesized clock. The direction and magnitude of the change of the latched output are determined by the delay difference sign comparison unit 237 and the delay difference displacement amount detection unit 238.

These data are added by the shift amount adder 239, and the values are stacked in the case of a fixed direction, and are canceled out in the case of a different direction, and are input to the frequency shift detecting unit 242. In addition, the clock delay difference-set value comparison unit 241 compares the value indicated by the clock synthesis impossible delay difference setting unit 240 with the delay difference data, and generates an alarm if the difference is outside the set value range.

Also, in the frequency shift detecting section 242, if the delay difference changes in the same direction and the amount exceeds a certain amount, an alarm is generated, and these results are output to the alarm logical adder 2.
At 43, the data is sent to the synthesized clock generation unit 233.

According to such a configuration, when the delay difference between branches increases and relatively exceeds half a cycle, an alarm is generated so that the synthesized clock is not synthesized at an incorrect convergence point.

Further, when the direction of the delay difference is within a certain range, it is considered that a frequency or phase difference exceeding the tracking performance in the synthesized clock circuit has occurred, an alarm is generated, and the clock synthesis is stopped. Malfunctions can be prevented and adverse effects on the system can be eliminated.

[0237]

As described above, according to the diversity receiving apparatus of the present invention, the clock timing can be made uniform, so that there is an effect that data phase combining and maximum ratio combining become possible.

Further, since the RSSI level information is used at the time of combining, the clock timing of the branch received correctly can be used, and there is an effect that the unstable element can be removed.

The timing of the synthesized clock can be freely changed in units of one clock cycle, and the synthesized clock can be generated in accordance with the ratio based on the RSSI difference.
There is an effect that the degree of influence can be increased for a branch having a higher SSI level and higher certainty.

Even when the RSSI level difference data changes abruptly, there is an effect that the clock change becomes gentle and the RSSI level difference can be followed.

The jitter of the synthesized clock can also be suppressed within the frequency of the high-speed clock for quantization, and when the clock is in an indeterminate state, the correct clock phase and frequency are not affected by the indeterminate clock. It is possible to output the ratio data based on the RSSI level difference for generating a stable clock without generating a timing error, to maintain the clock duty at 50%, and to obtain a stable combined clock. .

In the RSSI level comparison unit, the comparison is performed using the averaged value, so that fluctuations due to indefinite elements such as detection accuracy and noise and variations can be absorbed, and the RSSI level comparison can be stably performed.

The averaging circuit can take a moving average,
Highly accurate, continuous averaged data is obtained. 2 n
The configuration is facilitated by performing the averaging circuit for the power (n is an arbitrary value from 0 to a positive integer) times. An initial value of clock synthesis is given from the outside, and there is an effect that the rising speed can be increased.

[0244] Even in the case of a burst signal that is not continuous, it is possible to synthesize clocks, generate a clock corresponding to each slot, and have an effect that correct data reproduction can be performed. In the burst reception, it is not necessary to externally manage the phase of the counter load signal, and the configuration can be easily performed. In the burst reception, the average value of the RSSI level before the end of the slot and switching to another slot is stored and read. This has the effect of providing continuity to the burst information.

Even when the delay difference between the branches increases and relatively exceeds half a cycle, or when the frequency or the phase difference exceeds the tracking performance in the synthesized clock circuit, a malfunction due to clock synthesis occurs. There is an effect that can be prevented.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a radio unit of the diversity receiving apparatus for performing the delay time correction between diversity receiving branches according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a first internal configuration example of a clock synthesizing unit shown in FIG. 2;

FIG. 4 is a block diagram of a second internal configuration example of the clock synthesizing unit shown in FIG. 2;

FIG. 5 is a block diagram illustrating an example of an internal configuration of a count value generation unit illustrated in FIG. 4;

6 is a block diagram showing a case where the count value synthesizing section shown in FIG. 4 is provided with a count value change amount limiting function.

FIG. 7 is a block diagram illustrating an example of an internal configuration of a ratio setting conversion unit illustrated in FIG. 4;

FIG. 8 is a block diagram of a clock delay difference quantization unit shown in FIG. 4;

9 is a block diagram of a third internal configuration example of the clock synthesizing unit 14 shown in FIG. 2;

FIG. 10 is a block diagram of an alarm generating unit added to the clock synthesizing unit shown in FIG. 2;

11 is a block diagram showing a case where an averaging circuit is connected between the RSSI detector and the RSSI level comparator shown in FIG. 2;

12 is a block diagram of a first internal configuration example of the averaging circuit shown in FIG.

13 is a block diagram of a second internal configuration example of the averaging circuit shown in FIG.

14 is a block diagram of a burst slot corresponding synthesized clock generation unit in the clock synthesis unit shown in FIG. 2;

FIG. 15 is a block diagram of the memory shown in FIG. 14;

16 is a block diagram of a third internal configuration example of the averaging circuit shown in FIG.

FIG. 17 is a block diagram illustrating a radio unit of a diversity receiving apparatus that performs delay time correction between diversity receiving branches according to a second embodiment of the present invention.

FIG. 18 is a block diagram of a count value setting type clock synthesizing unit of the first example of the diversity receiver according to the second embodiment of the present invention.

FIG. 19 is a block diagram illustrating a count value setting type clock synthesizing unit according to a second example;

FIG. 20 is a block diagram illustrating a converged phase comparison type clock synthesizing unit of the diversity receiver according to the second embodiment of the present invention.

21 is a block diagram of a clock shift amount setting unit of the convergence phase comparison type clock synthesizing unit shown in FIG. 20;

FIG. 22 is a block diagram of an alarm stop control unit of the first example of the convergent phase comparison type clock synthesizing unit shown in FIG. 20;

FIG. 23 is a block diagram of a second example of the alarm stop control unit.

24 is a block diagram of a clock synthesizing unit corresponding to burst reception in the convergence phase comparison type clock synthesizing unit shown in FIG. 20;

25 is a block diagram of a clock combining phase holding unit corresponding to a plurality of slots for burst reception in the convergence phase comparison type clock combining unit shown in FIG. 20;

FIG. 26 is a block diagram illustrating an RSSI level “n-th power of 2” average section of the diversity receiver according to the second embodiment of the present invention.

27 is a diagram illustrating an RSSI corresponding to burst reception in the first example in the average section of the RSSI level “2 n stages” shown in FIG. 26;
FIG. 4 is a block diagram of a detection unit.

FIG. 28 is a block diagram of a second example of an RSSI detection unit for burst reception.

FIG. 29 is a block diagram of a clock synthesis stop alarm generator of the diversity receiver according to the second embodiment of the present invention.

FIG. 30 is a block diagram of a conventional diversity receiving apparatus.

FIG. 31 is a block diagram of a diversity receiver according to another conventional example.

[Explanation of symbols]

 1, 2 antenna 5, 6 electric field strength detecting means 7, 8 detecting means 9, 10 data reproducing means 11, 12 clock reproducing means 13 electric field strength comparing means 14 clock synthesizing means 16 data switching / synthesizing means B1 first branch B2 second branch

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-288735 (JP, A) JP-A-5-30084 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 7/02-7/12 H04L 1/02-1/06

Claims (16)

(57) [Claims] 1. A diversity receiving apparatus for receiving radio waves with a plurality of antennas, comprising: an electric field intensity detecting means for detecting an electric field intensity of a signal received by an antenna; a detecting means for detecting the received signal; Data reproducing means for reproducing data from the detected signal to obtain branch reproduced data; and clock reproducing means for reproducing a clock from the detected signal to obtain a branch reproduced clock. The electric field intensity detecting means, the detecting means, and the data The first to n-th branch means each of which is synchronized with the branch reproduction clock, and the magnitude of the electric field strength is detected by detecting a difference between the respective electric field strengths obtained by the first to n-th branch means. And an electric field strength comparing means for obtaining difference data indicating the difference, and the first to n-th blocks according to the ratio of the magnitude of each electric field strength found from the difference data. A clock synthesizing unit that outputs a reproduced clock by synthesizing each branch reproduced clock obtained by the launching unit; and selecting the branch reproduced data having a large electric field strength when the difference between the difference data is larger than a predetermined threshold. Data switching / synthesizing means for synchronizing with the reproduction clock for outputting as reproduction data, synthesizing each branch reproduction data when the difference is smaller than a predetermined threshold, and outputting as the reproduction data. Diversity receiver. 2. The clock synthesizing means includes: timing generation means for selecting a branch reproduction clock output from the first to n-th branches in accordance with the timing of the reproduction clock; High-speed clock generating means for generating a clock; performing a count operation with the high-speed clock from a clock supply point selected by the timing generating means to a count set value arbitrarily set; and outputting the count value as the reproduction clock. 2. The diversity receiving apparatus according to claim 1, further comprising: a synthesized clock counter means. 3. The clock synthesizing unit according to claim 1, wherein said clock synthesizing unit is configured to:
Clock delay difference quantizing means for determining the magnitude relationship between the branch recovered clocks of the n-th branch and detecting the delay difference including the delay / progression of the small clock with respect to the determined large clock, and the rise or fall of the large clock A clock edge detecting means for detecting and outputting an edge timing, a ratio setting converting means for obtaining a ratio of a smaller electric field strength to a larger electric field strength determined from the difference data, and multiplying the delay difference by the ratio. A count value generating means for obtaining a count value, and a clock generating count means for obtaining the reproduced clock by delaying / advancing the edge timing of the large clock by the count value. The diversity receiver according to claim 1. 4. The count value generation means outputs a count reference value by multiplying the ratio data output from the ratio setting conversion means with the delay difference data output from the clock delay difference quantization means. Ratio-count value converting means, and holding the count value,
Count latch means for outputting the held count value;
A count value comparing means for obtaining a difference value of the held count set value with respect to the count reference value and outputting the ± difference value as control data, and adding a value corresponding to the control data to the held count value; 4. The diversity receiving apparatus according to claim 3, further comprising an adding / subtracting means for subtracting and outputting the count value. 5. The diversity according to claim 4, wherein said addition / subtraction means does not perform addition / subtraction when said control data indicates that said count reference value is equal to said held count value. Receiver. 6. A clock movement amount setting table in which a clock movement amount setting value for limiting a size of an addition / subtraction value corresponding to the control data when the addition / subtraction means performs the addition / subtraction is provided. 6. The clock movement amount setting value according to the clock movement amount setting value arbitrarily set is output from the clock movement amount setting table to the adding / subtracting means. Diversity receiver. 7. An RSSI level difference-to-ratio conversion table for registering a ratio of electric field intensities of the first to n-th branches and outputting a ratio value according to the difference data, the ratio setting conversion means comprising: RSSI level comparing / monitoring means for outputting field strength data indicating whether the electric field strength of the first to n-th branches is larger or smaller than the unreceivable RSSI level setting value, The intensity data is masked, and the ratio data is obtained by correcting the ratio value so that the clock phase of the branch having the electric field intensity level equal to or less than the unreceivable RSSI level setting value does not affect the ratio. 4. The diversity receiving apparatus according to claim 3, further comprising: combining ratio masking means for outputting to said count value generating means. 8. A first clock rising edge detection unit for detecting a rising edge of a clock having a large level that can be determined from the difference data among the branch recovered clocks of the first to n-th branches. Means, second clock rising edge detecting means for detecting a rising edge of a reproduction clock having a small level which can be determined from the difference data, among the first to n-th branch reproduction clocks, and the first and second clocks. Clock delay difference counting means for counting the time between rising edges output from the rising edge detection means and outputting a value obtained by the counting to the count value generation means as the delay difference data. The diversity receiver according to claim 3, wherein: 9. The clock synthesizing means, the clock delay difference quantizing means, the clock edge detecting means,
The convergence point between each clock edge when synthesizing the large clock and the small clock according to the delay difference data output from the clock delay difference quantization means and the difference data is registered, and the delay difference A delay difference ratio conversion table for outputting convergence point data according to the data and the difference data, a clock movement amount setting table for registering a clock timing change amount set value per cycle, and outputting the clock timing change amount set value; A clock timing comparing means for outputting deviation data between the edge of the reproduction clock and the convergence point, and moving the edge of the large clock from the set value of the clock timing change amount or the deviation amount data to the convergence point data. A movement amount is obtained, and a count value setting for outputting the movement amount as the count value to the clock generation counting means. Diversity receiver according to claim 1, characterized by being configured to and a use subtraction means. 10. The clock delay difference quantization means, delay difference latch means for holding delay difference data output from the clock delay difference quantization means, holding delay difference data of the delay difference latch means, A clock delay difference comparing means for detecting a difference from the output delay difference data of the clock delay difference quantizing means, and a clock delay difference for generating alarm data when a detection difference of the clock delay difference comparing means exceeds a half clock cycle. Setting value comparing means, and RSSI level clock selecting means for selecting a large clock having a large level of the first to n-th branch recovered clocks according to the difference data;
A clock output means for selecting the clock output from the RSSI level clock selection means when the alarm data is generated; and a clock selection means for selecting and outputting the recovered clock when no alarm data is generated. The diversity receiver according to claim 1, wherein: 11. An average number of stages is arbitrarily set between the electric field intensity detecting means of the first to n-th branches and the electric field intensity comparing means, and the electric field intensity detected by the electric field intensity detecting means is set. 2. The diversity receiving apparatus according to claim 1, wherein averaging means for averaging by the number of averaging stages and outputting the averaging result to said electric field strength comparing means is connected. 12. An averaging unit comprising: an average stage number setting holding unit that holds the set average stage number; and an output terminal of the electric field intensity detecting units of the first to n-th branches.
One number is connected in series and has a delay time having a time equal to the detection period of the electric field strength, and a coefficient is connected to an output terminal of each of the delay devices and a coefficient corresponding to the set average number of stages is provided. A plurality of coefficient multipliers for multiplying the output value of the delay unit,
A plurality of adder / subtracters for adding / subtracting the electric field strength obtained as a result of the multiplication by each coefficient multiplier for each of two electric field strengths having a one-time delay relationship, the result of the last-stage adder / subtractor, and the set average number of stages are divided. 12. The diversity receiver according to claim 11, further comprising a divider for outputting the obtained electric field strength to said electric field strength comparing means. 13. An averaging unit comprising: an average stage number setting holding unit that holds the set average stage number; and an output terminal of the first to n-th branch electric field intensity detecting units, wherein the set average stage number—
One delay unit is connected in series and has a delay time equal to the detection period of the electric field intensity, and a plurality of first stage units connected to delay unit output terminals before and after each delay unit. An adder / subtractor, a plurality of second stage adder / subtractors connected to the output terminals of the delay units before and after the first stage adder / subtracter,
The adder / subtractor connected from the third stage to the n-th stage in the same manner as the connection relationship between the stage and the second stage, output electric field intensity data of the electric field intensity detection means and one for each stage. of the output field strength data of the adder-subtractor, comprising a selector for selecting the field strength data corresponding to the set average number 2 ^n, the average of 2 ¹ of the field strength data at each subtractor is 1 stage 2 the average of 2 ² in stage, the diversity receiving apparatus of claim 11, wherein a is adapted to output the average electric field strength results in 2 ⁿ at the n-th stage. 14. A burst control signal generating means for generating one of a slot designation signal, a memory read timing signal and a memory write timing signal in accordance with an external timing signal, and a reproduction clock output from the clock generation counting means. Storage means for storing the read clock in the storage area of the storage means indicated by the slot designation signal at a timing according to the memory write timing signal, and the clock generation counting means outputs the memory read timing signal The read clock read from the storage area of the storage means indicated by the slot designation signal is read at the timing shown by the following, and the read reproduction clock is loaded into the clock generation count means. 3. The diversity receiver according to 3. 15. A plurality of masking means for masking the memory write timing signal in accordance with a masking signal in the storage means, and a mask signal inputted to the plurality of masking means by decoding the slot designation signal. Decoder means, a plurality of clock holding count sections for holding the reproduced clock when a memory write timing signal other than the masked by the plurality of mask means is supplied, and the plurality of clock holding count sections 15. The diversity receiving apparatus according to claim 14, further comprising: selecting means for selecting a reproduced clock according to the mask signal and loading the selected clock into the clock generating counting means. 16. A plurality of selectors and delay units are alternately connected between the electric field intensity detecting means of the first to n-th branches and the averaging means, and a second one designated by a slot designation signal.
In the slot of the storage means, the electric field intensity output from the averaging means before completion of the slot processing in response to the write timing signal and before switching to another slot is stored. Selecting the output electric field strength of the detecting means and each delay device and outputting the selected electric field strength to the averaging means
11. The storage device according to claim 11, wherein each selector selects a storage electric field strength when a read timing signal is input to said second storage means, and outputs it to each delay device and said averaging means.
14. The diversity receiver according to any one of the thirteenth aspects.