JP3251748B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using a scan design method, which is one of techniques for facilitating a test.

[0002]

2. Description of the Related Art Conventionally, a scan design method has been known as one of methods for facilitating a test of a semiconductor integrated circuit. According to this scan design method, by configuring a scan pass (scan pass) with each flip-flop in a sequential circuit formed by a semiconductor integrated circuit,
It is possible to input an arbitrary value to a circuit of another part (constituting a combinational circuit) or directly observe an output value of the combinational circuit.

FIG. 2 is a block diagram for explaining the concept of a conventional scan design method. In the figure, scan flip-flops 201 and 201 in a semiconductor integrated circuit are shown.
02, 203, and 204 input signals from either the input D or the input SI based on the control signal CTRL.
The output Q and the output SO output the value stored in the scan flip-flop. Then, each scan flip-flop 201, 202, 203, 20
4 are connected to the signal lines S ₁ , S ₂ , S ₃
To form a scan path.

In such a semiconductor integrated circuit, when it is desired to input a desired signal to the combinational circuit 205, for example, the control signal CTRL is set to a scan path mode. Next, by inputting a clock signal CLK, a desired signal input from S _{IN is} input to the scan flip-flop 201.
Set to. At this time, the set value is output to Q, and this signal is input to combinational circuit 205. When it is desired to directly observe the output value of the combinational circuit 205, first, the output value of the combinational circuit 205 is fetched from the input D in the normal mode, and then the control signal is switched to the scan path mode and this output signal is output. it is sufficient to output as the signal S _OUT through the scan flip-flops 203 and 204.

FIG. 2 shows a case where all the scan flip-flops 201, 202, 203, and 204 operate with the same clock signal CLK.
Some semiconductor integrated circuits use a plurality of types of clock signals.

As a circuit that constitutes a scan path in a semiconductor integrated circuit that uses a plurality of types of clock signals, for example, there is a circuit as shown in FIG. FIG.
In FIG. 2, components denoted by the same reference numerals as those in FIG. 2 indicate the same components as those in FIG. 3, in the normal operation, the scan flip-flops 201 and 203 is operated by a clock signal CLK _1, scan flip-flops 202 and 204 shows the case of operating by the clock signal CLK _2. Therefore, multiplexers 301 and 302 are newly provided, and
The scan flip-flops 202, 302 are controlled during normal operation by controlling the test flip-flops 1, 302 with the test mode signal M.
The clock signal CLK ₂ to the clock input terminal 204 is input, it is configured so that the clock signal CLK ₁ is inputted at the time of test operation. Thus, the test can be performed in the same procedure as the circuit shown in FIG.

FIG. 4 shows another example in which a scan path is formed in a semiconductor integrated circuit using a plurality of types of clock signals. In this example, an input terminal of a clock signal SCLK for performing shift transfer in a scan path is provided independently to each of the scan flip-flops 201, 202, 203, and 204. In a circuit having such a configuration, a test is performed in the following procedure.

First, by sequentially inputting the input signal S _IN in response to the clock signal SCLK, each of the scan flip-flops 201 and 20 is scanned using a scan path.
Initial values of 2, 203 and 204 are set.

Then, by inputting the clock signal CLK ₁ , the output signal of the combinational circuit 206 is taken into the scan flip-flop 203.

[0010] Then, by inputting again the clock signal SCLK, the captured from the combinational circuit 206 to the scan flip-flop 203 signals, is output from the output S _OUT through the scan flip-flops 203 and 204. Thus, the output signal of the combination circuit 206 can be observed.

Next, each scan flip-flop 201, 202, 203, 204
Then, the same initial value as above is set again.

Then, by inputting the clock signal CLK ₂ , the output signals of the combinational circuits 205 and 207 are taken into the scan flip-flops 202 and 204.

[0013] Then, by inputting again the clock signal SCLK, the signal taken to the scan flip-flops 202, 204 from the combinational circuit 205, 207, and sequentially outputted as an output S _{OU T.} Thus, the output signals of the combination circuits 205 and 207 can be observed.

[0014]

[SUMMARY OF THE INVENTION However, in the semiconductor integrated circuit shown in FIG. 3, during the test operation, the clock signal CLK ₁ is inputted to the skew (i.e. scan flip-flops 201 and 203 to the clock signal CLK ₁ Timing and scan flip-flop 202
Circuit deviation) is caused between the timing of the clock signal CLK ₁ is inputted has a drawback that when there is a malfunction in. This skew is caused by the delay time for the clock signal CLK ₁ is passed through multiplexer 301 and 302. When designing a semiconductor integrated circuit, the effects of skew in normal operation are carefully examined to prevent malfunction.However, when a test operation is performed between scan flip-flops that originally operate with different clock signals, It was virtually impossible to design considering the effect of skew.

On the other hand, in the semiconductor integrated circuit as shown in FIG. 4, the skew problem as in the circuit shown in FIG. 3 arises because the scan flip-flops having different clocks do not operate simultaneously. Absent. But,
The circuit of FIG. 4 has a drawback that the procedure of the test operation is very complicated and the test time becomes long. FIG The circuit 4, perform the operation test of the combination circuit in the preceding stage of the scan flip-flop that operates in an operation test and a clock signal CLK ₂ of the combination circuit in the preceding stage of the scan flip-flop which operates by the clock signal CLK ₁ separately The test time must be extended by that much time. That is, in the method described with reference to FIG. 4, the test must be repeated n times in a circuit using n types of clock signals.

Here, in the circuit using the method described with reference to FIG.
Assuming that the number of scan flip-flops operated by the clock signal a is b, the number of scan flip-flops operated by the second clock signal is b, and the test cycle is T, the time required for the first input data transfer is T (a +
b). Subsequently, since one system clock is input, a time for this is required by T, and finally, a time required for transfer of the output data is T (a + b). Therefore, the time required for the first test is T (a + b) + T + T (a + b) = 2T (a + b) + T. Since the same test needs to be repeated one more time because n = 2, the total time required for the test is {2T (a + b) + T} × 2 = 4T (a + b) + 2T (1) Becomes

The present invention has been made in view of the above-mentioned drawbacks of the prior art. Even when a plurality of clock signals are used, no malfunction occurs during the test and the test is performed in a short time. It is an object of the present invention to provide a semiconductor integrated circuit capable of performing the above.

[0018]

According to the present invention, there is provided a semiconductor integrated circuit comprising a plurality of clock signal lines for transmitting mutually different clock signals, and a plurality of clock signal lines for transmitting clock signals different from each other. A scan flip-flop connected to each of the signal lines by one or more, and a scan path signal line connecting the scan flip-flops connected to the same clock signal line in series. Features.

[0019]

According to the semiconductor integrated circuit of the present invention, the scan flip-flops to which the same clock signal line is connected are connected by the scan path signal line, that is, for each scan flip-flop operated by the same clock signal. By configuring the scan path, even when a plurality of clock signals are used, no malfunction occurs during the test, and the test can be performed in a short time.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to one embodiment of the present invention will be described below.

FIG. 1 is an electric circuit diagram schematically showing the configuration of a semiconductor integrated circuit according to this embodiment.

In the figure, scan flip-flops 111, 112, ... and scan flip-flops 121, 122, ... in the semiconductor integrated circuit receive input D or input D based on a control signal (not shown). A signal is input from one of the SIs. In addition, the scan flip-flops 111 and 112, it is in ... the clock signal CLK ₁
Are scan flip-flops 121, 122,.
The clock signal CLK _2, are input to. Then, the scan flip-flops 111, 112,.
· Input SI and output SO a signal line S _11, S _12, ··
Are connected to each other to form a first scan path. Similarly, scan flip-flops 121 and 12
Are connected to the signal lines S ₂₁ and S ₂₁ .
_22, are connected to each other by ... constitute a second scan path. As described above, the circuit of this embodiment has two scan paths. Scan flip-flop 1
, And the output Q of the scan flip-flops 121, 122,... Are input to the combination circuits 131, 132, 133,. The input D of these scan flip-flops
Are combined circuits 131, 132, 133,
Are input.

Next, the operation of the circuit shown in FIG. 1 will be described.

First, a predetermined value is sequentially input to the SI input of the scan flip-flop 111 by using the clock signal CLK ₁ to shift within the first scan path, thereby forming each of the first scan paths. An arbitrary initial value is set to the scan flip-flops 111, 112,... Subsequently, using the clock signals CLK _2, by shifting the second scan campus by sequentially inputting predetermined values to SI input of the scan flip-flop 121, the scan flip constituting the second scan path Are set to the initial values. Thereby, each combinational circuit 131, 1
32, 133,... Receive the output Q of the preceding scan flip-flop and output a signal corresponding to the input value.

Next, each of the scan flip-flops 111 and 112 constituting the first scan path by using the clock signal CLK _1, and allowed to ingest the output value of the preceding combinational circuit to ..., followed by each of these The value is sequentially shifted on the first _{scan path} and output as an output signal S _OUT1 . At this time, no clock signal is input to each of the scan flip-flops 121, 122,... Constituting the second scan path, so that a malfunction due to skew does not occur.

[0026] Then, the first scan path only activates, the clock signal CLK ₁ the scan flip-flops 111 constituting the first scan path using again,
.. Are set to the initial values. Thus, each of the combinational circuits 131, 132, 133,... Again receives the output Q of the preceding scan flip-flop and outputs a signal corresponding to the input value.

[0027] Then, only the second scan path is activated, the scan flip-flops constituting the second scan path with a clock signal CLK ₂ 121,12
2, ... take in the output value of the preceding combinational circuit,
Thereafter, these values are sequentially shifted on the second _{scan path} and output as the output signal S _OUT2 , thus ending the test. At this time, no clock signal is input to each of the scan flip-flops 111, 112,... Constituting the first scan path, so that a malfunction due to skew does not occur.

In the circuit of this embodiment, the number of scan flip-flops operated by the first clock signal is a
Assuming that the number of scan flip-flops operated by the clock signal b is b and the test cycle is T, the time required to transfer the input data in the first test (test using the first scan path) is T (a + b) ). Subsequently, since one system clock is input, the time for this is T
And finally, the time required to transfer the output data is Ta. Therefore, the time required for the first test is T (a + b) + T + Ta = 2Ta + Tb + T. Next, the time required to transfer the input data in the second test (test using the second scan path) is Ta. Thereafter, since one system clock is input, the time required for this is required by T, and The time required to transfer the output data is Tb. Therefore, the time required for the second test is Ta + Tb + T. Therefore, the total time required for the test is (2Ta + Tb + T) + (Ta + Tb + T) = 3Ta + 2Tb + T (2) Here, when the equation (2) is compared with the above equation (1), the following equation is obtained: (1) − (2) = {4T (a + b) + 2T} − {3Ta + 2Tb + T} = Ta + 2Tb + T That is, according to the circuit of the present embodiment, the total time required for the test is Ta compared to the conventional circuit shown in FIG.
It can be shortened by + 2Tb + T.

As described above, according to the present embodiment, it is possible to reduce the test time when a plurality of clock signals are used.

Further, since each scan path is not operated at the same time, it is possible to eliminate the occurrence of malfunction due to skew.

Further, according to the present embodiment, the number of input data used for the test can be reduced, and the test time can be shortened in this respect as well.

In this embodiment, the case of using a circuit using two types of clock signals has been described as an example.
K ₁ , CLK ₂ ) Needless to say, the present invention can be applied to a case where three or more types of clock signals are used. In the present invention, as the number of types of clock signals increases, the time that can be shortened also increases, and a greater effect can be obtained.

[0033]

As described above in detail, according to the present invention, even when a plurality of clock signals are used, no malfunction occurs during the test and the semiconductor can be tested in a short time. An integrated circuit can be provided.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram schematically showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram for explaining the concept of a conventional scan design method.

FIG. 3 is an electric circuit diagram schematically showing a configuration example of a conventional semiconductor integrated circuit.

FIG. 4 is an electric circuit diagram schematically showing another configuration example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

Reference Signs List 100 semiconductor integrated circuit 111, 112, 121, 122 scan flip-flop 131, 132, 133 combination circuit

────────────────────────────────────────────────── (5) References JP-A-63-205580 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (1)

(57) [Claims] In a semiconductor integrated circuit formed by using a scan design method, a plurality of clock signal lines for transmitting different clock signals and one or more clock signal lines are connected to each clock signal line. A semiconductor integrated circuit comprising: a scan flip-flop; and a scan path signal line that connects the scan flip-flops connected to the same clock signal line in series.