JP3243286B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a device having a MOS transistor.

[0002]

2. Description of the Related Art In manufacturing a CMOS device, in order to adjust a work function of a material constituting a gate electrode, generally, an n ⁺ -type polycrystalline silicon is used for a gate electrode of an NMOS transistor, and a gate of a PMOS transistor is used. P ⁺ -type polycrystalline silicon is used for the electrodes. Here, in order to ensure controllability so that a desired concentration can be obtained when introducing impurities into the polycrystalline silicon of the gate electrode constituent material, before forming the gate electrode, the impurities are implanted by a process such as ion implantation in advance. Must be introduced into polycrystalline silicon. This is because if the introduction of impurities into the polycrystalline silicon as the gate electrode constituent material is performed simultaneously in the ion implantation step for forming the source and drain regions, it is necessary to form the source and drain regions shallowly. This is because the voltage is restricted. In addition, since it is necessary to change impurities to be introduced between the gate electrode of the NMOS transistor and the gate electrode of the PMOS transistor, a resist film is usually formed by using a photo-etching method, and ion implantation is performed using the resist film as a mask. .

Here, after implanting impurity ions,
In order to remove the resist film, an oxygen (O ₂ ) -plasma-asher treatment and a cleaning treatment using a mixed solution of hydrogen peroxide solution (H ₂ O ₂ ) and sulfuric acid (H ₂ SO ₄ ) are performed.

However, a silicon oxide film having a thickness of 20 to 50 angstroms is formed on the polycrystalline silicon film by the process of stripping the resist film. In particular, since it is necessary to implant different impurity ions on the NMOS transistor side and the PMOS transistor side as described above, n
^It is necessary to separate the resist film for implanting ⁺ type ions and the resist film for implanting p ⁺ type ions. Therefore, the oxygen-plasma-asher treatment and the cleaning treatment using a mixed solution of hydrogen peroxide and sulfuric acid are performed twice. Through these steps, n
^{On the +} type polycrystalline silicon film and on the p ⁺ type polycrystalline silicon film, silicon oxide films having different thicknesses depending on the degree of exposure to oxygen are formed. And such a phenomenon occurs not only when impurity ions of different conductivity types are implanted,
This also occurs when a polycrystalline silicon film into which impurity ions of one conductivity type are previously formed is uniformly formed, and then impurity ions of the opposite conductivity type are implanted into only one region.

The silicon oxide films having different thicknesses are formed by NMO.
The following problems have been caused by being formed on the polycrystalline silicon film on the S side and the PMOS side. In order to cope with the thinning of the gate oxide film with the miniaturization of elements,
The anisotropic etching performed when forming the gate electrode is performed such that a high selectivity can be obtained between the polycrystalline silicon film and the silicon oxide film. For this reason, the difference in the thickness of the silicon oxide film formed on the polycrystalline silicon film causes a large shift in the timing at which the etching of the polycrystalline silicon is started after the etching of the silicon oxide film is completed. The time was also causing a big shift.

The polysilicon film on the NMOS side and the PMOS
Etching with the polycrystalline silicon film on the side does not start at the same time, and when the silicon oxide film on the surface starts thinner and finishes sooner, the device that monitors the emission intensity during etching is It is determined that the etching is completed. Then, it is not possible to judge the completion point of the etching for the slower etching, and it becomes impossible to obtain the desired shape of the gate electrode by performing the etching without excess or deficiency.

Heretofore, in general, the difference in the etching completion time between a polycrystalline silicon film into which n ⁺ -type impurity ions are implanted and a polycrystalline silicon film into which p ⁺ -type impurity ions are implanted is due to the difference in impurity of different conductivity type. It was thought that the difference in the material caused by the introduction of was introduced. The fact that silicon oxide films having different thicknesses are formed on the n ⁺ -type polycrystalline silicon film and the p ⁺ -type polycrystalline silicon film has been overlooked.

FIG. 6 shows the results of a comparison between the etching time of the n ⁺ -type polycrystalline silicon film and the etching time of the p ⁺ -type polycrystalline silicon film. A polycrystalline silicon film having a thickness of 2000 angstroms was formed, and different impurity ions were introduced into the two regions to form an n ⁺ -type polycrystalline silicon film and a p ⁺ -type polycrystalline silicon film. And
The same anisotropic etching was performed, and the etching time was measured. The amount of etching with respect to the etching time of the n ⁺ -type polycrystalline silicon film is shown by line L1, and the amount of etching with respect to the etching time of the p ⁺ -type polycrystalline silicon film is shown by line L2. As is apparent from this figure, the etching start times of the n ⁺ -type polycrystalline silicon film and the p ⁺ -type polycrystalline silicon film are different from T1 and T2. The etching rates are not so different between the two, and the start times T1, T
The difference between the two results in a difference between the etching completion times Tn and Tp.

Thus, the n ⁺ type polycrystalline silicon film and the p ^{+
Since the} thickness of the silicon oxide film formed on the surface differs between the ⁺ type polycrystalline silicon film and the silicon oxide film, the etching completion time differs, which causes a problem that a gate electrode cannot be formed in a desired shape.

FIG. 7 shows a cross section of an element in the case where a gate electrode is formed by using a conventional manufacturing method. FIG.
As shown in (a), after a p-well 702a and an n-well 702b are formed on the surface of a p-type semiconductor substrate, the field oxide film 70 is formed in the element isolation region by LOCOS.
Form 3 Impurity ions necessary for achieving a desired element operation are implanted into each channel region, and the threshold voltages Vtn and Vtp are adjusted. Thereafter, gate oxide films 704a and 704b having a desired thickness are formed on the respective element regions. A polycrystalline silicon film 705 is formed to a thickness of 2000 angstroms by using the LPCVD method.
Then, the polycrystalline silicon film 705 on the p well 702a
, And a p-type impurity ion is selectively implanted into the polycrystalline silicon film 705 on the n-well 702b by forming a resist film. Here, the resist film is peeled off by an oxygen-plasma-asher treatment or a treatment using a mixed solution of a hydrogen peroxide solution and sulfuric acid. As a result, as shown in FIG. 7A, a thin silicon oxide film 706a is formed on n ⁺ type polycrystalline silicon film 705a, and a thick silicon oxide film 706b is formed on p ⁺ type polycrystalline silicon film 705b. Is formed.

As shown in FIG. 7B, resist films 707a and 707b for forming gate electrodes are formed, and an n ⁺ -type polysilicon film 705a and a p ⁺ -type polysilicon film 705 are formed.
b) is subjected to anisotropic etching. After the time T1 in FIG. 6 has elapsed after the start of the etching, the n ⁺ -type polycrystalline silicon film 706a starts to be etched, and after the time T2 has elapsed, the p ⁺ -type polycrystalline silicon film 706b starts to be etched. After the time Tn, the etching of the n ⁺ -type polycrystalline silicon film 706a is completed, and the etching monitor makes a Just determination. After this, Just + 10%
N-well 702b
The upper p ⁺ -type polycrystalline silicon film 705a remains without being etched.

If etching is further performed to avoid the remaining of the p ⁺ polycrystalline silicon film 705b, there is a problem that the surface of the semiconductor substrate 701 of the p well 702a is etched as shown in FIG. 7C.

Accordingly, an object of the present invention is to provide a manufacturing method capable of processing gate electrodes of different conductivity types into a desired shape even when they are formed by anisotropic etching.

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

As described above, in the conventional manufacturing method, when manufacturing a CMOS device, an n ⁺ -type polysilicon film and a p ⁺ -type polysilicon film are formed on the surface. Since the thickness of the silicon oxide film is different, the etching completion time is different, and there is a problem that the gate electrode cannot be formed in a desired shape. Therefore, an object of the present invention is to provide a manufacturing method capable of processing gate electrodes of different conductivity types into a desired shape when forming the gate electrodes by anisotropic etching.

[0021]

[0022]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of: depositing a gate electrode component on a surface of a semiconductor substrate to form a gate electrode component film; Forming a resist film on the film, and selectively implanting impurity ions into the gate electrode component material film using the resist film as a mask, thereby providing a plurality of regions having mutually different conductivity types; and Removing the insulating film present on the gate electrode component material film, and etching the gate electrode component material film to form a gate electrode. .

[0023]

[0024]

When impurity ions are implanted into a gate electrode constituent material film using a resist film as a mask and the resist film is removed, insulating films having different thicknesses are formed in a plurality of regions having different conductivity types. By removing this insulating film before performing etching on the gate electrode constituent material film, etching of regions having different conductivity types can be completed almost at the same time, and a gate electrode can be formed in a desired shape. .

[0025]

[0026]

An embodiment of the present invention will be described below with reference to the drawings.

Each of the first to fourth embodiments of the present invention relates to a method of forming gate electrodes of mutually different conductivity types by anisotropic etching. Embodiments of the present invention relate to a method for forming a salicide structure.

First, a manufacturing method according to the first embodiment of the present invention is shown in FIG. As shown in FIG. 1A, a p-well 10 is formed on the surface of a p-type semiconductor substrate 101.
2a and n-well 102b are formed, and L
The field oxide film 103 is formed by using the OCOS method or the like. Adjust the impurity concentration of the channel region by performing ion implantation necessary to achieve the desired transistor operation,
The threshold voltages Vtn and Vtp are obtained.

Next, gate oxide films 104a and 104b are formed to a thickness of about 70 angstroms. Polycrystalline silicon 105 serving as a gate electrode material is deposited by LPCVD to a thickness of about 2000 Å. As the n-type impurity, for example, arsenic (As) is implanted into the polycrystalline silicon film 105 on the p well 102a. This injection
As shown in FIG. 1A, a resist film 106 covering a region other than the p-well 102a is formed. The acceleration voltage is set to, for example, 40 keV, and the dose is set to 3 × 10 ¹⁵ cm ⁻² . Thereafter, the resist film 106 is peeled off by an oxygen-plasma-asher treatment or a cleaning treatment with a mixed solution of a hydrogen peroxide solution and sulfuric acid.

As shown in FIG. 1B, a region other than the n-well 102b is covered with a resist film 120, and boron fluoride (B
F ₂ ) or the like is implanted into the polycrystalline silicon film 105 on the n-well 102b at, for example, a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 35 keV. After that, the resist film 120 is peeled off by a similar process.

At this stage, as shown in FIG. 1C, the surface of the n-type polycrystalline silicon film 105a and the p-type polycrystalline silicon film 105b have a difference in the degree of exposure to oxygen. Silicon oxide films 107 and 108 having different thicknesses
Are respectively formed. This silicon oxide film 107, 1
08 is removed, for example, by treatment with hydrofluoric acid diluted with water at a ratio of 100: 3 for about 1 minute, or by treatment in an ammonium fluoride solution for about 20 seconds.

As shown in FIG. 1D, a resist film 109 is formed on a region where a gate electrode is to be formed. Using this resist film 109, the polycrystalline silicon films 105a and 105a
Anisotropic etching is performed on 5b to form gate electrodes 110a and 110b as shown in FIG. Here, the silicon oxide films 107 and 108 may be removed after the resist film 109 for forming the gate electrode is formed and before the anisotropic etching is performed. If the silicon oxide films 107 and 108 are removed at this stage, the natural oxide film formed during the formation of the resist film 109 is also removed at the same time.

After the gate electrodes 110a and 110b are formed, a source / drain region 112a is formed on the surface of each p-well 102a by performing an impurity ion implantation step and a thermal diffusion step necessary for activating the impurities. And source / drain regions 112b are formed on the surface of the n-well 102b. Here, side walls 111 are formed on side surfaces of the gate electrodes 110a and 110b, and lightly doped drains (LDs) are formed.
D) Although the structure is adopted, it is not always necessary to adopt such a structure.

Further, an interlayer insulating film 113 is formed on the entire surface, and contact holes are formed on the source / drain regions 112a and 112b.
4 to complete the CMOS device.

As described above, in this embodiment, after the polycrystalline silicon film for forming the gate electrode is uniformly formed, impurities having different conductivity types are implanted to form the n-type polycrystalline silicon film and the p-type polysilicon film.
When forming the mold polycrystalline silicon film, the silicon oxide films having different thicknesses formed in the step of removing the used resist film are removed using a diluted hydrofluoric acid solution or an ammonium fluoride solution. As a result, when performing anisotropic etching on the n-type polycrystalline silicon film and the p-type polycrystalline silicon film, the silicon oxide films having different thicknesses which have conventionally affected the etching time are removed. For this reason, in order to cope with the thinning of the gate oxide film which progresses along with the miniaturization of the element, the silicon oxide film has been generated by obtaining a high selectivity required for the anisotropic etching performed when forming the gate electrode. A shift in etching time of the polycrystalline silicon film due to a difference in film thickness can be prevented.

Further, heat treatment for activating the impurities As and BF ₂ introduced into the polycrystalline silicon film is not performed. Therefore, there is no Mott carburetor-type electrical effect that appears when the impurities are activated. Therefore, there is no difference in etching rate due to a difference in material between the n-type polycrystalline silicon film and the p-type polycrystalline silicon film.

As described above, in this embodiment, anisotropic etching can be completed in the n-type polycrystalline silicon film and the p-type polycrystalline silicon film almost simultaneously. Therefore, it is easy to determine when to end the etching, and by performing the etching without excess or deficiency, it is possible to form the n-type polycrystalline silicon electrode and the p-type polycrystalline silicon electrode in a desired shape with a high yield. is there.

The second to fourth embodiments described below correspond to the first embodiment.
The basic steps are the same as those of the embodiment, and the method of introducing impurities into the polycrystalline silicon film is different.

A second embodiment of the present invention will be described with reference to FIG. As in the first embodiment, as shown in FIG. 2A, a p-well 202a and an n-well 202b are formed on the surface of a p-type semiconductor substrate 201, and a field oxide film 203 is formed on an element isolation region. Form. The impurity concentration of the channel region is adjusted by performing ion implantation necessary to achieve a desired transistor operation, and the threshold voltage Vtn,
Vtp is obtained. Gate oxide films 204a, 204
04b is formed to a thickness of about 70 angstroms. Polycrystalline silicon 205 serving as a gate electrode material is formed by LPCVD.
It is deposited to a film thickness of about 2000 Å by using the method. Then, unlike the first embodiment, for example, BF ₂ is applied over the entire surface of the polycrystalline silicon film 205 by accelerating at 35 keV.
Then, the implantation is performed under the condition that the dose amount is 1 × 10 ¹⁵ cm ⁻² . Thus, a p-type polycrystalline silicon film 205b is formed on the entire surface.

As shown in FIG. 2B, a region other than the p-well 202a is covered with a resist film 206. This resist film 2
06 is used as a mask, for example, As is implanted into the polycrystalline silicon film 205b on the p-well 202 at an acceleration voltage of 40 keV and a dose of 6 × 10 16 cm ⁻² . Thus, an n-type polycrystalline silicon film 205a is formed on p well 202a, and p-type polycrystalline silicon film 2 is formed on n well 202b.
05b is formed.

As in the first embodiment, the resist film 206 is peeled off by an oxygen-plasma-asher treatment and a cleaning treatment with a mixed solution of hydrogen peroxide and sulfuric acid. Further, the silicon oxide film 207 formed on the polycrystalline silicon film 205a, which is not covered with the resist film 206 and exposed to oxygen, is formed by, for example, diluting a hydrofluoric acid solution,
Alternatively, it is removed with an ammonium fluoride solution.

Here, the silicon oxide film 207 may be entirely removed. However, considering that the etching rate of the n-type polycrystalline silicon film 205a is slightly higher than that of the p-type polycrystalline silicon film 205b,
The silicon oxide film 207 on 05a may be left selectively. As a result, as a result, the polycrystalline silicon film 205 is formed.
It can be adjusted so that the etching completion timings of a and 205b are almost the same.

Thereafter, the same steps as in the first embodiment are performed. That is, as shown in FIG. 2D, a resist film 208 is formed on the gate electrode formation region. Using this resist film 208, the polycrystalline silicon films 205a, 205
Anisotropic etching is performed on 5b to form gate electrodes 209a and 209b as shown in FIG. Gate electrode 2
After the steps 09a and 209b are formed, an impurity ion implantation step and a thermal diffusion step are performed to form a source / drain region 211a in the p-well 202a, and the n-well 202b
Source and drain regions 211b are formed on the surface of the substrate. Further, an interlayer insulating film 212 is deposited, contact holes are formed on the source and drain regions 211a and 211b, and aluminum wirings 213 are formed to complete a CMOS device.

In the second embodiment, as in the first embodiment, the n-type polysilicon film and the p-type polysilicon film are formed on the surface before anisotropic etching is performed. The silicon oxide film that has been removed is removed. Further, a heat treatment for activating the impurities As and BF ₂ introduced into the polycrystalline silicon film is not performed. Therefore, anisotropic etching can be completed in the n-type polysilicon film and the p-type polysilicon film almost simultaneously. Therefore, the n gate electrode and the p-type gate electrode can be formed in a desired shape with a high yield.

A third embodiment of the present invention will be described with reference to FIG. As in the first and second embodiments, FIG.
As shown in (a), a p-well 302a and an n-well 302b are formed on the surface of a p-type semiconductor substrate 301, and a field oxide film 303 is formed in an element isolation region. The impurity concentration of the channel region is adjusted by implanting impurity ions. Gate oxide films 304a and 304b are formed to a thickness of about 70 angstroms. Polycrystalline silicon film 305
Is deposited to a film thickness of about 2000 angstroms by the LPCVD method or the like.

Unlike the first and second embodiments, a phosphorus diffusion step is performed on the entire surface of the polycrystalline silicon film 305 using phosphorus oxychloride (POCl) to introduce phosphorus. Thus, an n-type polycrystalline silicon film 305a is formed on the entire surface.

As shown in FIG. 3B, a region other than the n-well 302b is covered with a resist film 306. This resist film 3
Using BF as a mask, BF ₂ is implanted into the polycrystalline silicon film 305a on the n-well 302b at an acceleration voltage of 35 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . Thus, an n-type polycrystalline silicon film 204a is formed on p well 202a, and p-type polycrystalline silicon film 3 is formed on n well 302b.
05b is formed.

As in the first and second embodiments, the resist film 306 is peeled off by an oxygen-plasma-asher process and a cleaning process using a mixed solution of hydrogen peroxide and sulfuric acid.
Further, the polycrystalline silicon film 305b
The silicon oxide film 307 formed thereon is removed using a diluted hydrofluoric acid solution or an ammonium fluoride solution.

Thereafter, similarly to the first and second embodiments, a resist film 308 is formed on the gate electrode formation region as shown in FIG. 2D. Using this resist film 308, anisotropic etching is performed on the polycrystalline silicon films 305a and 305b to form a gate electrode 309 as shown in FIG.
a, 309b are formed. Gate electrodes 309a, 309
By implanting impurity ions using b as a mask and further performing a thermal diffusion step to activate the impurities, the p well 30
Source and drain regions 311a are formed in 2a, and source and drain regions 311b are formed on the surface of n-well 302b. An interlayer insulating film 312 is deposited on the entire surface, contact holes are formed on the source and drain regions 311a and 311b, and an aluminum wiring 313 is formed to complete a CMOS device.

According to the third embodiment, the first and second
As in the embodiment, anisotropic etching can be completed in the n-type polycrystalline silicon film and the p-type polycrystalline silicon film almost at the same time, and a gate electrode having a desired shape can be formed. it can.

A fourth embodiment of the present invention will be described below with reference to FIG. As in the first, second, and third embodiments, as shown in FIG.
A p-well 402a and an n-well 402b are formed on the surface of the substrate, and a field oxide film 403 is formed in an element isolation region. Impurity ions are implanted into the channel region to adjust the impurity concentration in this portion. Gate oxide film 404
a, 404b are formed to a thickness of about 70 angstroms.

Next, unlike the above-described embodiment, the LPCV
According to Method D, diborane is used as a reaction gas,
Deposit 00 Å of boron-doped polycrystalline silicon 405.

As shown in FIG. 4B, a region other than the p-well 402a is covered with a resist film 406. This resist film 4
06 is used as a mask, arsenic (As) is applied to the polycrystalline silicon film 405a on the p-well 402b with an acceleration voltage of 40 ke.
V is implanted at a dose of 6 × 10 ¹⁶ cm ⁻² . This allows
An n-type polycrystalline silicon film 405a is formed on p well 202a.
Is formed, and a p-type polycrystalline silicon film 405b is formed on n well 402b.

The resist film 406 is peeled off by an oxygen-plasma-asher process and a cleaning process using a mixed solution of a hydrogen peroxide solution and sulfuric acid as in the above-described embodiment. Further, as shown in FIG. 4C, the silicon oxide film 407 formed on the polycrystalline silicon film 405a by this processing step
Is removed using a diluted hydrofluoric acid solution or an ammonium fluoride solution.

Thereafter, as shown in FIG. 4D, a resist film 408 is formed on the gate electrode formation region. Using this resist film 408, a polycrystalline silicon film 405 is formed.
A and 405b are subjected to anisotropic etching to form gate electrodes 409a and 409b as shown in FIG. Impurity ions are implanted using the gate electrodes 409a and 409b as masks, and a thermal diffusion process is performed to form source and drain regions 411a in the p-well 402a,
A source / drain region 411b is formed in 02b.
An interlayer insulating film 412 is deposited over the entire surface, contact holes are formed on the source and drain regions 411a and 411b, and an aluminum wiring layer 413 is formed to form a CMOS.
Complete the device.

According to the fourth embodiment, similarly to the first, second and third embodiments, the anisotropic etching on the n-type polysilicon film and the p-type polysilicon film is almost completed. The gate electrodes can be completed at the same time and a gate electrode having a desired shape can be formed.

The above-described first to fourth embodiments are merely examples, and do not limit the present invention. For example, the same effect can be obtained by using an n-type semiconductor substrate instead of a p-type semiconductor substrate. Further, when removing the silicon oxide film formed on the p-type and n-type polycrystalline silicon films,
Although hydrofluoric acid or an ammonium fluoride solution diluted with water is used in the embodiment, any treatment may be used as long as it can remove the silicon oxide film.

Next, a reference example of the present invention for forming a salicide structure will be described with reference to FIG. In this embodiment,
After forming the gate electrode, a carbon film is formed uniformly, and anisotropic etching is performed using oxygen to form side walls on the side surfaces of the gate electrode. There is a characteristic in that it is performed.

As shown in FIG. 5A, a p-well 602a and an n-well 602 are formed on the surface of a p-type semiconductor substrate 601.
and a field oxide film 604 is formed by LOCOS or the like. Implanting impurity ions into the device region,
The impurity concentration distribution in the channel region is controlled so as to obtain a desired threshold voltage.

On the n-well 602a and the p-well 602b, a gate oxide film 605a of about 110 Å is formed.
And 605b are respectively formed. A polycrystalline silicon film serving as a gate electrode material is formed to a thickness of about 3500 angstroms. For example, phosphorus is diffused and introduced into the polycrystalline silicon film under the conditions of 900 degrees Celsius for 30 minutes. Gate electrodes 606a and 606b are formed by performing anisotropic etching. Dry oxidation is performed at 900 degrees Celsius for 10 minutes to form post-oxide films 607a and 607b around the gate electrodes 606a and 606b.

Thereafter, carbon (C) is deposited by sputtering or the like to form a carbon film 608 to a thickness of about 1000 Å.

The carbon film 608 is anisotropically etched using oxygen (O ₂ ). The flow rate of oxygen gas is, for example, 10
0SCCM (standard cubic centimeters per minute), that is, 678.6 (Pa · cm ³ / s), and the pressure is 5.3P.
a, The high frequency power is 0.8 W / cm ² . By this anisotropic etching, as shown in FIG.
6a and 606b around the carbon film 608,
A carbon side wall 609 is formed.

Impurity ions are implanted using gate electrodes 606a and 606b, field oxide film 604, and carbon sidewall 609 as a mask. In the p-well 602a, for example, boron fluoride (BF ₂ ) is accelerated at 40 keV,
The implantation is performed at a dose of 5 × 10 ¹⁵ cm ⁻² . In the n-well, for example, arsenic (As) is supplied at 50 keV and 5 × 10 ¹⁵ cm ^−2.
Inject with. Thereafter, in order to activate the implanted impurity ions, for example, at 1050 degrees Celsius for 20 seconds,
High-speed heat treatment is performed in a nitrogen atmosphere. Thus, n-type source / drain regions 610a are formed in p well 602a.
Is formed, and p-type source / drain regions 610b are formed in the n-well 602b. If the carbon side wall has been degraded or peeled by this stage, the carbon side wall may be reconfigured as necessary at this stage or at an earlier stage. Since the selectivity is almost infinite, the device operation does not deteriorate even if the carbon side wall is repeatedly formed.
Next, a silicon oxide film (not shown) formed on the surfaces of the source and drain regions 610a and 610b and on the gate electrodes 606a and 606b is, for example, 100: 3
And treated with a hydrogen fluoride solution diluted with water for 2 minutes to remove.

As shown in FIG. 5B, a titanium (Ti) film 612 is deposited to a thickness of 300 Å on the entire surface by a sputtering method, and a titanium nitride (TiN) film 613 is further deposited thereon to a thickness of 700 Å. Deposits thick. Next, for example, high-speed heat treatment is performed in a nitrogen atmosphere at 750 degrees Celsius for 30 seconds. This process includes
For example, a rapid lamp heating method can be used. With this process, the titanium on the surfaces of the source and drain regions 610a and 610b reacts with titanium to form titanium disilicide (TiSi ₂ ). The other regions do not react with titanium because there is no silicon on the surface.

The titanium film 612 which has not reacted with the silicon
And the titanium nitride film 613 are formed by, for example, sulfuric acid (H ₂ S
O ₄₎ and selectively stripped using a mixture of hydrogen peroxide (H ₂ O _2). As a result, as shown in FIG. 5C, the gate electrode 606a and the source / drain regions 610a, 61
The titanium disilicide film 614 is selectively formed only on the surface of Ob. Thereafter, an oxygen-asher process is performed, for example, for 30 minutes to remove the carbon side wall 609. Then, using the gate electrodes 606a and 606b as a mask, p
Arsenic is implanted into the well 602a, and boron fluoride is implanted into the n-well 602b to form an LDD structure.

Thereafter, a heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 20 seconds to activate the impurities in the LDD regions, respectively.
The material of No. 14 is modified to form a salicide structure.

An interlayer insulating film 617 is deposited on the entire surface, and contact holes are formed on the surfaces of the source and drain regions 610a and 610b. Aluminum is deposited on this surface and processed into a desired wiring pattern to form an aluminum wiring layer 618.

As described above, in this embodiment, after the gate electrode is formed, the carbon film is formed uniformly, and the carbon side wall is formed on the side surface of the gate electrode by anisotropic etching using oxygen.
Here, when performing anisotropic etching using oxygen for the carbon film, oxygen hardly erodes the surface of the silicon substrate. Therefore, an almost infinite selection ratio can be obtained with respect to the silicon substrate. Conventionally, when the side wall is formed with a silicon oxide film to prevent silicidation,
Erosion of the surface of the source and drain regions is prevented, junction characteristics are improved, and retraction of the end of the field oxide film is prevented.

The product produced by this etching is carbon monoxide (CO) or carbon dioxide (C
O ₂ ). Therefore, unlike the case where the side wall is formed by the conventional silicon nitride film, the composition does not change at all by the etching product adhering to the surface of the carbon side wall.

Further, the side wall made of carbon has a function of preventing a metal such as Ti from silicidation after a short-time non-equilibrium heat process by performing a high-speed heat treatment. The experiment revealed this.

Referring to FIG. 8, a 1000 Å carbon film is formed on a silicon oxide film (SiO ₂ ) by sputtering, and 300 Å Ti and T
After iN is formed by sputtering at 700 Å, a rapid lamp heating process at 750 ° C. for 30 seconds is performed in a nitrogen atmosphere, unreacted Ti and TiN are peeled off by a SH process, and the amount of Ti in the carbon film is reduced. The result of having analyzed in the depth direction by AES (Auger spectroscopy) is shown. Ti is detected only below the AES analysis sensitivity, and it is clear that a compound such as TiC is not formed globally.
The spectrum of Ti in the figure is a noise level. For reference, the results of AES analysis of data obtained by subjecting only a carbon film to rapid heat treatment without forming Ti are also shown. Further, FIG. 9 shows an SH treatment (H ₂ SO ₄ and H ₂ O
₃ shows an AES spectrum of the outermost surface of a carbon film after a cleaning treatment (removal of unreacted Ti) with a mixed solution of No. ₂ ; When Ti is present on the surface, it is detected as a peak value near 418 eV, but such a peak value is not found in this document, and it is confirmed that Ti is below the AES detection limit (1 atomic%). it can. That is, TiC even on the surface
The formation of such a compound does not proceed. In addition, it was confirmed that the carbon film that had been subjected to the thermal process after depositing Ti thereon could be easily peeled off by the O ₂ -plasma asher treatment, similarly to the carbon film that had undergone the thermal process without depositing Ti. . Therefore, by forming the carbon side wall on the side surface of the gate electrode, insulation between the gate electrode and the source and drain regions is ensured. Further, the carbon side wall can be easily removed by oxygen-asher treatment. Therefore, electrical insulation between the gate electrode and the source / drain regions is more reliably ensured, and capacitive coupling between them can be reduced. After removing the carbon side wall, an LDD region can be easily formed using the gate electrode as a mask.
For this reason, the LDD structure can be obtained without being affected by an undesired thermal process such as silicidation, so that an excellent effect of preventing a short channel effect can be obtained.

The above reference example is merely an example, and does not limit the present invention. For example, the rapid heat treatment for forming the carbon side wall and performing silicidation on the metal film is not limited to the rapid lamp heating method. The heating condition is 75 degrees Celsius.
The conditions are not limited to 0 degrees and 30 seconds. As long as the silicidation proceeds between the silicon film and the metal film in a portion where silicon is present, such as the gate electrode and the source and drain regions, and heating is performed within a range in which a chemical reaction does not occur between the metal film and carbon. .

In the reference example, on the surface of the gate electrode,
A silicide film is simultaneously formed on the surface of the source and drain regions. However, when the gate electrode is formed as a polycide structure, an insulating film is formed on the surface. Therefore, even if a metal film is formed on the insulating film, silicidation does not occur with silicon. However, in this case, a high-melting-point metal such as titanium is used for the gate electrode, and the purpose of reducing the resistance has been achieved.
The metal film only on the drain region may be silicided.

Further, in this embodiment, the gate electrode is formed using a polycrystalline silicon film in which phosphorus is diffused, but the gate electrode may be made conductive by ion implantation. Further, a dual gate structure may be obtained by introducing an n ⁺ -type impurity into the polycrystalline silicon film on the p-well and introducing a p ⁺ -type impurity into the polycrystalline silicon film on the n-well.

After the salicide step is completed, it is not always necessary to remove the carbon side wall, but the carbon side wall can be left. In addition, the source and drain are GDD (Graded Diffu
sedDrain) structure or DDD (Double Diffused Dra)
In the case of the in) structure, by completing the formation of the source and the drain before forming the carbon side wall, there is no cause for deteriorating the carbon side wall, and the manufacturing process becomes stable.

[0076]

As described above, according to the present invention, after the impurity film is removed by implanting impurity ions using the resist film as a mask to the gate electrode component material film, the insulating film is formed before the gate electrode component material film is etched. Therefore, the etching of a plurality of gate electrode constituent material films having different conductivity types can be completed almost at the same time, and the gate electrode can be formed in a desired shape.

[0077]

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention for each process.

FIG. 2 is a longitudinal sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention for each process.

FIG. 3 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention for each process.

FIG. 4 is a longitudinal sectional view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention for each process.

FIG. 5 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention for each process.

FIG. 6 is an explanatory diagram showing a difference in etching time between an n ⁺ -type polycrystalline silicon film and an n ⁺ -type polycrystalline silicon film caused by a conventional manufacturing method.

FIG. 7 is a longitudinal sectional view showing a conventional manufacturing method for each process.

FIG. 8 is an explanatory diagram showing the results of forming a Ti film and a TiN film on a carbon film, separating the Ti film and the TiN film after rapid heating, and analyzing the amount of Ti in the carbon film.

FIG. 9 is an explanatory view showing an AES spectrum of the surface of the carbon film.

[Explanation of symbols]

101, 201, 301, 401, 601 Semiconductor substrates 102a, 202a, 302a, 402a, 602a
p-well 102b, 202b, 302b, 402b, 602b
n-wells 103, 203, 303, 403, 604 field oxide films 104a, 204a, 304a, 404a, 605a
p-well 104b, 204b, 304b, 404b, 605b
n-well 105, 205, 305, 405, 608 polycrystalline silicon film 105a, 205a, 305a, 405a n-type polycrystalline silicon film 105b, 205b, 305b, 405b p-type polycrystalline silicon film 106, 109, 120, 206, 208 , 306, 3
08, 406, 408 resist films 107, 108, 207, 307, 407 silicon oxide films 110a, 110b, 309a, 309b, 409a,
409b, 606a, 606b Gate electrode 112a, 211a, 311a, 411a, 610a
n ⁺ -type source and drain regions 112b, 211b, 311b, 411b, 610b
p ⁺ type source / drain region 111 sidewall 113, 312, 412, 617 interlayer insulating film 114, 313, 413, 618 aluminum wiring layer 609 carbon sidewall 612 titanium film 613 titanium nitride film 614 titanium disilicide film

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukihiro Ushiku Hiroshi Komukai Toshiba-cho, Kawasaki-shi, Kanagawa 1 Inside Toshiba Research Institute Co., Ltd. Machi 1 Toshiba Research Institute (56) References JP-A-4-92416 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 21 / 28 H01L 29/49

Claims (1)

(57) [Claims] A step of depositing a gate electrode component material on a surface of a semiconductor substrate to form a gate electrode component material film; forming a resist film on the gate electrode component material film; and masking the resist film. Providing a plurality of regions having different conductivity types by selectively injecting impurity ions into the gate electrode component material film; removing the resist film; and A method for manufacturing a semiconductor device, comprising: a step of removing an existing insulating film; and a step of forming a gate electrode by etching the gate electrode constituent material film.