JP3241065B2 - Line memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line memory,
In particular, the present invention relates to a device suitable for use in high definition television (HDTV), clear vision (EDTV), and the like.

[0002]

2. Description of the Related Art As an example of digital signal processing, FIG.
The processing required when converting from a non-interlace signal to an interlace signal using will be described. As shown in FIG. 7A or 8A, the non-interlace signal is
In this manner, all data from the first line to the 525th line are sequence signals arranged in order, and one field constitutes one screen.

On the other hand, the interlace signal means an odd line (1, 1) in an odd field as shown in FIG.
, 3, 5,...), And the even lines (2, 4, 6, 6, etc.) as shown in FIG.
..). As described above, the video signals of the odd lines or the even lines are alternately formed for each field, and one screen is formed of two fields. Here, the total number of lines is an odd number of 525 lines, and the video signal is sequential data. Therefore, the series data of the i-th line in the x-field is represented by Z
(I) If｝ x, ..., ｛Z (1)｝ x, ｛Z
(2)｝ x,..., ｛Z (524)｝ x, ｛Z (52
5) The odd-numbered lines and the even-numbered lines are continuously arranged, such as｝ x, ｛Z (1)｝ x + 1, ｛Z (2)｝ x + 1,. Therefore, only by performing the writing for each line, the signal of the odd line and the signal of the even line can be obtained alternately for each field.

In order to convert such a non-interlace signal into an interlace signal, the following two points must be satisfied. (1) Thinning out non-interlace signals every other line,
In addition, odd-numbered video signals and even-numbered video signals alternately appear for each field. (2) Since the number of scanning lines per field is reduced to い て by thinning out every other line, the frequency of the converted interlace signal is not twice as high as that of the non-interlace signal. Then, the interlaced signal after the conversion is expanded by a factor of two to match the field frequencies before and after the conversion.

Next, the relationship between input data and a line address and output data and a read address during interlace conversion in a conventional line memory will be described. Table 5 shows the case of the odd field, and Table 6 shows the case of the even field.

[0006]

[Table 5]

[0007]

[Table 6] Here, the subscript i of the input data or the output data is 1, 3,
An odd number such as 5,... Indicates that the data is the data of the i-th scanning line. Therefore,
i, i + 2, i + 4,... indicate odd lines, i−1,
i + 1, i + 3,... indicate even lines. In addition, n indicates the number of data samples per line, and addresses exist from 0 to (n-1) corresponding to the number of samples.

In the odd field, as shown in Table 5, the input data x (0) i, x (1) i, x
(2) i,... Are written in the line memory, and input data x (0) i + 1, x (1) i + 1, x (2) i +
1, ... are not written. In the even-numbered field, as shown in Table 6, the input data x (0) i−1, x
(1) i-1, x (2) i-1,... Are written into the line memory, and input data x (0) i, x (1) i of the odd-numbered lines are written.
, X (2) i,... Are not written.

As described above, the input data is written to the line memory by thinning out one line at a time. When the written data is read as output data, the cycle of changing the read address is set to twice the cycle of changing the write address, and the output data is expanded to twice the input data.

FIG. 9 shows a configuration of a conventional line memory. As constituent elements, a write address generator 1, a read address generator 2, a selector 3, a read / write signal generator 4, 910 × l (910 is the number of data samples per line, l is the number of bits per sample) ) The RAM 5 having a capacity of bits is provided.

The write clock terminal 6 is connected to the write clock terminal CK of the write address generator 1, and the write reset terminal 7 is connected to the write reset terminal CL. The read clock terminal 8 is connected to the read clock terminal CK of the read address generation unit 2, and the read reset terminal 9 is connected to the read reset terminal CL. Output terminals Q0 to Q9 of write address generator 1
Are connected to one input terminal of the selector 3 by a write address data line ADW, and the output terminals Q0 to Q9 of the read address generator 2 are connected to the read address data line ADR.
Is connected to the other input terminal of the selector 3.

A write clock terminal 6 is connected to the clock terminal CK of the read / write signal generator 4, and a write enable terminal 11 is connected to the write enable terminal WE. The output terminal RW is connected to another input terminal of the selector 3.

In the RAM 5, the input terminal 10 is connected to the input data terminal 5a, the output terminal of the selector 3 is connected to the address terminal 5b, and the output terminal RW of the read / write signal generator 4 is connected to the read / write terminal 5c. Have been. The chip enable terminal 5d is connected to the chip enable terminal 12
And the output data terminal 5e is connected to the output terminal 13
It is connected to the.

The operation of this line memory will be described with reference to the timing charts of FIGS. A write clock signal WCK is input to a write clock terminal CK of the write address generator 1. The write address generator 1 operates as a counter for generating a write address, and generates the write address by counting pulses of the write clock signal WCK. Further, a write reset signal WCL is input to the write reset terminal CL. The write reset signal WCL counts the write clock signal WCK during the high level and outputs the write address signal A
This is for generating DW and resetting the count value to “0” when it is at the low level.

Similarly, a read clock signal RCK and a read reset signal RCL are input to the read address generator 2. The read address generator 2 outputs the read clock signal RCK while the read reset signal RCL is at the high level.
To generate a read address signal ADR,
When the read reset signal RCL becomes low level, the count value is reset to “0”.

Since the period of the read clock signal RCK is twice as long as the write clock signal WCK as described above, the period of the read address signal ADR changes at twice the period of the write address signal ADW. .

The write address signal ADR and the read address signal ADW are input to the selector 3. Selector 3
Switches the output so as to output one of them according to the read / write signal RW output from the read / write signal generator 4. When the read / write signal RW is "1", the read address signal ADR is selected,
When the read / write signal RW is "0", the write address signal ADW is selected and output. Further, the read / write signal RW is inputted from the terminal 5d as a read / write signal of the RAM 5. When the read / write signal RW is "1", the data {y (n) i} stored at the read address ADR in the RAM 5 is output from the output terminal 5e. When the read / write signal RW is "0", the data {x (n) i} input from the input terminal 5a is written to a cell of the RAM 5 corresponding to the write address ADW.

Here, when the write enable signal WE is "0", the read / write signal RW output from the read / write signal generator 4 is the write clock signal WCK.
When the write enable signal WE is "1", the level is fixed at "1". Therefore, while the write enable signal WE is “0”, the read / write signal RW
The writing and the reading are performed alternately in accordance with the change in the level of. In this case, the read address signal ADR changes in a cycle twice as long as the read / write signal RW.
The read operation is performed twice. here,
As shown in the timing chart of FIG. 10, the output data DO read from the read address signal ADR is output.
Is delayed by a half cycle of the chip enable signal CE. This means that the RAM 5 stores the chip enable signal CE.
Is "0", and becomes standby when "1".

Writing and reading are repeated until the write enable signal WE rises from "0" to "1" level. After the data of the i-th line is written, the data of the (i + 1) -th line is input from the input terminal 10, but since the data is thinned out line by line, R
It is not written to AM5. At the time when the data on the i-th line is written, only about half of the data has been read from the RAM 5. Therefore, the write enable signal WE of “1” is input to the read / write signal generator 4, and the read / write signal RW of “1” is applied to the RAM 5, and the input data becomes the data of the next (i + 2) th line. Until the above, only the read operation is performed.

[0020]

However, such a conventional line memory has a problem that the RAM 5 must have a large capacity. In order to write all the data of the i-th line once, if the number of bits per sample is l, the total number of bits is 910 samples ×
1-bit capacity is required. If the number of samples or the number of bits per sample increases, the capacity of the RAM 5 must also be increased, resulting in an increase in the area of hardware and an increase in cost.

The present invention has been made in view of the above circumstances, and has as its object to provide a line memory capable of reducing the memory capacity and the cost.

[0022]

A line memory according to the present invention is supplied with an input signal having n samples per line, and stores the data necessary for thinning the input signal into k-1 lines every k lines. A storage element to be stored, a write address generator for generating a write address signal to be applied to the storage element, and a read address generation to generate a read address signal to be applied to the storage element so as to output the input signal stored by the storage element After storing m samples in the storage element for the necessary i-th line data of the input signal, the write address value is initialized and the remaining nm samples are set to 1 It is characterized in that data that has not been read out is stored in a storage element so as not to be overwritten.

[0023]

When storing the input signal in the storage element, if it is attempted to store all the data for one line and the number of samples per line is n, the storage element is n ×
Although a capacity of (the number of bits of one sample) is required, the value of the write address is initialized after m intermediate samples have been written, and the remaining data is overwritten on the data once written. By doing so, the capacity required for the storage element is reduced. Here, the number of remaining samples n−
When the input signal of m is stored, the previously written data is overwritten, but the condition that the data of which the value of m has not been read at all is not overwritten is satisfied. There is no problem if it is decided to do so.

[0024]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a line memory according to the present embodiment. The timing at which the value of the write address is reset in the write address generator 20 is different from that of the conventional line memory. Accordingly, the capacity of the RAM 24 is reduced to about half (456 × 1 bit number) of the related art. The connection relationship of each element as a block configuration is common to the conventional line memory shown in FIG. 9, and a description thereof will be omitted.

Table 1 below shows the relationship between input data and a write address and the relationship between output data and a read address in this embodiment. Here, this corresponds to a case where the number n of samples is an even number.

[0026]

[Table 1] In the conventional case, all data for one line is written in the RAM 5. For this reason, the write address generator 1 generates write addresses from 0 to n−1, where n is the number of samples, and when the address becomes n−1, the write address becomes 0.
Had been reset. On the other hand, the write address generator 20 of this embodiment resets the counter value after generating a write address from 0 to n / 2. At this time, of the n data of one line, n / 2 + 1
Pieces of data are written in the RAM 24.

Then, write addresses from 0 to n / 2-2 are generated again from the write address generator 20, and the remaining n / 2-1 data are written. Thus, the remaining data is overwritten on the data once written. As the data is overwritten, previously written data is sequentially erased, but there is no problem as long as the data has already been read.

In this case, the timing at which the write address generator 20 resets the address value to 0 is important. After the reset, while the remaining data is being overwritten, the condition that the value of the write address is smaller than the value of the read address must be satisfied. By resetting at any timing when such a condition is satisfied, data that has not been read yet is prevented from being overwritten and erased. In the above embodiment, the reset is performed when the write address becomes n / 2. However, the write address at the time of resetting does not have to be this value, and if the maximum value of the write address is selected from n / 2 to (n-2), unread data is erased. There is no.

The relationship between the input data and the write address and the relationship between the read address and the output address when the sample number n is an odd number is as shown in Table 2 below.

[0030]

[Table 2] Similarly, in this case, the timing of resetting the value of the write address to 0 is set so that the condition that the value of the write address is larger than the value of the read address is satisfied from after the reset until the remaining data is written. Is set. Here, the reset is performed when the line address becomes (n-1) / 2.

Next, the circuit operation of the present embodiment shown in FIG. 1 will be described with reference to the timing charts of FIGS. As in the conventional case, while the write enable signal WE of “0” is being supplied to the read / write signal generator 23, a read / write signal RW similar to the write clock signal WCK is output and given to the selector 22. And
Write and read operations are performed alternately. The cycle in which the read address signal ADR changes is twice the cycle in which the write address signal ADW changes, and the read operation is performed twice for one read address signal ADR. Assuming that the number of samples of the data of one line is 910, 910/2 + 1 of the i-th line is 45.
After the data for six samples is written, that is, after the value of the write address becomes 455, the write reset signal WCL of “0” is input to the write address generation unit 20. As a result, the value of the write address signal ADW becomes 0
become. The write address signal ADW starts from 0 again, and the remaining 454 data on the i-th line are RA
M24 is written. Thus, the remaining data x
(456) i, x (457) i, x (458) i,... Already written data x (0) i, x (1) i, x
(2) It is sequentially overwritten on i,. However, since these data x (0) i, x (1) i,... Have already been read before being overwritten, there is no problem even if they are erased. In this manner, the writing operation and the reading operation are performed alternately until the operation of writing the last data x (909) i of the i-th line is completed.

When the i-th line is completed, the next line i +
1 is input from the input terminal 29, but this data is thinned out and not written to the RAM 24. During this period, the write enable signal WE input to the read / write signal generator 23 is "1", and writing is prohibited. During this period, the reading of the remaining data on the i-th line stored in the RAM 24 is continued. When the input data becomes the data of the (i + 2) th line, the same operation as that of the i-th line is performed.

According to this embodiment, the capacity of the RAM 24 is about half that of the conventional case. This capacity is
When the number of samples n per line is an even number, (n / 2 +
1) × (the number of bits in one sample), and when n is an odd number, it becomes {(n−1) / 2 + 1} × (the number of bits in one sample).

Next, another embodiment of the present invention will be described. In this embodiment, one line is supplied by thinning out three lines out of four lines in a sequence signal having 192 samples per line. Therefore, in this case, it is necessary to expand the output data by four times the input data. FIG. 4 shows the configuration of the line memory according to this embodiment. Compared to the embodiment shown in FIG. 1, the write address generator 40 receives the write reset signal WCL of “0”, resets the value of the write address, and supplies the read address generator 41. The frequency of the read clock signal RCK is different. The connection relationship between the components is the same as in FIG.

Table 3 shows the relationship between the input data and the write address and the relationship between the output address and the read address in this embodiment.

[0036]

[Table 3] Here, it is assumed that n is a multiple of four. Sequence signals x (n) i, x (n) i + 1, x (n) i + 2, x of four lines
(N) i + 3, ..., one signal x (n) i is taken out, expanded to four times the length, and output. When the write address signal ADW starts from 0 and becomes 3n / 4, it is reset, restarts from 0 and outputs up to n / 4 corresponding to the remaining data. In this case, RAM
The memory capacity P of 44 is sufficient as (3n / 4 + 1) × (the number of bits of one sample) ≦ P ≦ (n−1) × (the number of bits of one sample).

Table 4 shows that the number m of samples per line is n.
The relationship between the input / output data and the address in the case of +2 is shown. Here, n is a multiple of 4 as in Table 3.

[0038]

[Table 4] When the write address signal ADW changes from 0 to 3n / 4 + 1, the value of the write address signal ADW is reset to 0. The input data is written up to x (3n / 4 + 1) i, and the write address signal ADW starts from 0 and is overwritten with the next data x (3n / 4 + 2) i. The data is output until the value of the write address signal ADW becomes n / 4-1 so that all data x (n-1) i are written.

The timing chart of each signal in this embodiment is as shown in FIGS. Read address signal ADR output from read address generator 41
Changes at a period four times as long as the write address signal ADW output from the write address generator 40. While the write enable signal WE is “0”, the write and read operations are performed alternately. At this time, since the read address signal ADR changes in a cycle four times as long as the write address signal ADW, the read operation is performed four times for one read address signal ADR.

As described above, the write address signal AD
When W becomes 3n / 4 + 1, it is reset to 0, and the already written data x (0) i, x (1) i,... Are sequentially erased. However, there is no problem because the data has been read by the time of erasure, as in the embodiment shown in FIG.

In this embodiment, the capacity P of the RAM 44 is (3n / 4 + 2) × (the number of bits of one sample) ≦
It suffices if there is a size represented by p ≦ (n−1) × (the number of bits of one sample). As described above, in the present embodiment, the capacity is greatly reduced as compared with the case where all the data for one line (n × (the number of bits of one sample)) is conventionally written, and the area occupied by the hardware is reduced. Reduction and cost reduction are achieved.

As an embodiment, a description will be given of a case where one line is output for every two lines and one line of data is output, and a case where three lines are output for every four lines and one line of data is output. did. However, these examples are merely examples, and do not limit the present invention. For example, every three to five or more k lines, k-
The present invention can be similarly applied to a case where one line is thinned and one line is output. In this case, it is necessary to set the period at which the read address signal changes to be k times the period at which the write address signal changes.
The timing for initializing the write address signal ADW only needs to keep the condition that the value of the write address is smaller than the value of the read address while all the remaining data is overwritten. As a result, data that is sequentially erased by overwriting after resetting the value of the write address is
The data will be read by the time the data is erased.

In the embodiment, the values of the write address and the read address are counted up as shown in Tables 1 to 4, but may be counted down. In this case as well, it is necessary to prevent the data that has not been read yet from being overwritten, but the timing of initializing the write address signal is determined while the data is being overwritten.
The condition that the value of the write address is larger than the value of the read address must be satisfied. Further, the address does not necessarily need to be a value counted up or down, and may be generated in any way if no duplicate value exists until the address is initialized. In this case as well, the present invention can be applied if the condition that data that has not been read yet is not overwritten is observed.

[0044]

As described above, the line memory of the present invention is supplied with the input signal of the number n of the samples, and writes the number m of the samples at the time of performing the interlace conversion for thinning out the output every fixed line. Thereafter, the value of the write address is reset in the write address generator, and the remaining n-
The m input signals are sequentially overwritten, but during this period, the write address value is reset when a condition smaller than the read address value is satisfied, so that those that have not been read yet are erased by overwriting. Storage capacity can be reduced while preventing
Hardware reduction and cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a line memory according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation waveform of each signal in the line memory.

FIG. 3 is a timing chart showing operation waveforms of signals in the line memory.

FIG. 4 is a block diagram showing a configuration of a line memory according to another embodiment of the present invention.

FIG. 5 is a timing chart showing an operation waveform of each signal in the line memory.

FIG. 6 is a timing chart showing an operation waveform of each signal in the line memory.

FIG. 7 shows an interlace signal in an odd field,
FIG. 3 is an explanatory diagram showing the concept of a non-interlace signal.

FIG. 8 shows an interlace signal in an even field,
FIG. 3 is an explanatory diagram showing the concept of a non-interlace signal.

FIG. 9 is a block diagram showing a configuration of a conventional line memory.

FIG. 10 is a timing chart showing an operation waveform of each signal in the line memory.

FIG. 11 is a timing chart showing an operation waveform of each signal in the line memory.

[Explanation of symbols]

 20, 40 Write address generator 21, 41 Read address generator 22, 42 Selector 23, 43 Read / write signal generator 24, 44 RAM

Claims (1)

(57) [Claims] An input signal having n (n is an integer of 1 or more) samples per line is supplied, and the input signal is k
(K is an integer of 2 or more) a storage element for storing data necessary for thinning out k-1 lines for each line; a write address generator for generating a write address signal to be given to the storage element; And a read address generator for generating a read address signal to be applied to the storage element so as to output the stored input signal. On the other hand, after storing m (m is an integer smaller than n) samples in the storage element, the value of the write address is initialized, and the remaining nm sample data has not been read at all. A line memory wherein data is stored in a storage element so as not to overwrite data.