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JP3139276B2 - Overload protection circuit for power semiconductor devices - Google Patents

Overload protection circuit for power semiconductor devices

Info

Publication number
JP3139276B2
JP3139276B2 JP06090399A JP9039994A JP3139276B2 JP 3139276 B2 JP3139276 B2 JP 3139276B2 JP 06090399 A JP06090399 A JP 06090399A JP 9039994 A JP9039994 A JP 9039994A JP 3139276 B2 JP3139276 B2 JP 3139276B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
protection circuit
semiconductor element
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP06090399A
Other languages
Japanese (ja)
Other versions
JPH07297697A (en
Inventor
昌一 古畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP06090399A priority Critical patent/JP3139276B2/en
Publication of JPH07297697A publication Critical patent/JPH07297697A/en
Application granted granted Critical
Publication of JP3139276B2 publication Critical patent/JP3139276B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は電源に直列接続された負
荷に流す電流を制御する電力用半導体素子を使用中に負
荷側から掛かりやすい過負荷から保護するための回路、
とくに電力用半導体素子とともに集積回路に組み込むに
適する保護回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for protecting a power semiconductor element for controlling a current flowing to a load connected in series to a power supply from an overload which is likely to be applied from a load side during use.
In particular, the present invention relates to a protection circuit suitable for being incorporated in an integrated circuit together with a power semiconductor element.

【0002】[0002]

【従来の技術】電界効果トランジスタ,絶縁ゲートバイ
ポーラトランジスタ等の電力用半導体素子の用途拡大に
伴い、従来から使い勝手の向上のために駆動用や制御用
の関連回路とともに半導体形ないしはハイブリッド形の
集積回路に組み込んでいわゆるインテリジェントパワー
スイッチやインテリジェントパワーモジュールの形態で
提供する傾向が強まって来ており、さらに最近では負荷
の変動や短絡時に掛かる過負荷や過電圧から半導体素子
を保護するための回路もこれに追加して組み込むことが
要求されるようになって来た。
2. Description of the Related Art As power semiconductor devices such as field effect transistors and insulated gate bipolar transistors have been expanded in use, semiconductor or hybrid integrated circuits have been used together with related circuits for driving and control in order to improve usability. In recent years, there has been a growing trend to provide intelligent power switches and intelligent power modules in the form of intelligent power switches and intelligent power modules. It has come to be required to additionally incorporate them.

【0003】図5にかかる要求に沿った保護回路の従来
の代表例を保護特性の面から示す。図5(a) は単純な過
電圧保護回路の保護特性Bを示し、誘導性負荷の遮断時
等に半導体素子に掛かる横軸の電圧Vが電源電圧Vsより
高く設定された最大電圧Vmを越えると、半導体素子をオ
フ動作させて図示のように縦軸の電流Iを遮断する。最
大電圧Vmの値はもちろん半導体素子の耐圧よりは低く,
ふつうは電源電圧Vsの1.5〜2倍の範囲内に設定され
る。
FIG. 5 shows a conventional representative example of a protection circuit in accordance with the requirements in view of protection characteristics. FIG. 5 (a) shows the protection characteristic B of a simple overvoltage protection circuit. When the voltage V on the horizontal axis applied to the semiconductor element when the inductive load is cut off exceeds the maximum voltage Vm set higher than the power supply voltage Vs. Then, the semiconductor element is turned off to interrupt the current I on the vertical axis as shown in the figure. The value of the maximum voltage Vm is, of course, lower than the withstand voltage of the semiconductor element.
Usually, it is set within a range of 1.5 to 2 times the power supply voltage Vs.

【0004】図5(b) は半導体素子が負荷の短絡時等に
過大な電力により熱的に破壊しないようにする過電力保
護回路の保護特性Cを示す。図のように半導体素子に掛
かる電圧Vが電源電圧Vsより低く設定した電圧Vaを越え
ると電流Iの制限を開始し、以後は電流Iを双曲線的な
特性で制限しながら電圧Vが最大電圧Vmに達した時に0
まで絞り込んで半導体素子をオフ状態にする。最大電圧
Vmを上述のように電源電圧Vsの 1.5〜2倍に設定して双
曲線的な特性部分を半導体素子がもつ熱特性にほぼ合わ
せると、電流制限の開始電圧Vaは電源電圧Vsの 0.5〜0.
7 倍の範囲内になるのがふつうである。
FIG. 5B shows a protection characteristic C of an overpower protection circuit for preventing a semiconductor element from being thermally destroyed by excessive power when a load is short-circuited or the like. As shown in the figure, when the voltage V applied to the semiconductor element exceeds the voltage Va set lower than the power supply voltage Vs, the current I starts to be limited, and thereafter, the voltage V becomes the maximum voltage Vm while limiting the current I with a hyperbolic characteristic. 0 when reached
To turn off the semiconductor element. Maximum voltage
When Vm is set to 1.5 to 2 times the power supply voltage Vs as described above and the hyperbolic characteristic portion is substantially matched to the thermal characteristics of the semiconductor element, the current limit start voltage Va becomes 0.5 to 0.
It is usually in the range of seven times.

【0005】[0005]

【発明が解決しようとする課題】前述の図5(a) の保護
特性をもつ過電圧保護回路は回路構成がごく簡単で済む
利点はあるが、容易にわかるように半導体素子を熱的な
破壊から充分に保護できない問題がある。半導体素子に
掛かる電圧Vが最大電圧Vm以下であってもそれに流れる
電流Iが過大な過負荷の状態が持続すると、とくに電圧
Vが電源電圧Vsを越える範囲内で半導体素子の熱的破壊
の危険があるからである。
The overvoltage protection circuit having the protection characteristics shown in FIG. 5 (a) has an advantage that the circuit configuration is very simple, but as will be easily understood, the semiconductor element is not easily damaged by thermal destruction. There is a problem that cannot be sufficiently protected. Even if the voltage V applied to the semiconductor device is less than the maximum voltage Vm, if the overload state in which the current I flowing therethrough is excessive continues, especially in a range where the voltage V exceeds the power supply voltage Vs, there is a risk of thermal destruction of the semiconductor device. Because there is.

【0006】これに対して、図5(b) の保護特性をもつ
過電力保護回路は半導体素子の熱的破壊に対する保護が
良好であり、しかも最大電圧Vmを越える過電圧に対する
保護性能も備えている。しかし、電力制限開始電圧Vaが
前述のように電源電圧Vsより低くなり, 従って電圧Vが
Va〜Vsの範囲内では負荷側が正常であっても電流Iが制
限されてしまうので、半導体素子がその本来もつ負荷駆
動能力を充分発揮できなくなる問題がある。とくに重要
な負荷を駆動している時は、負荷が正常でかつ半導体素
子の電圧Vが電源電圧Vs以下なのに負荷駆動能力が低下
ないし喪失してしまうことは絶対に許されないことがあ
る。また、図5(b) のような双曲線的な特性をもつ保護
回路では、負荷の急変時に過電力時の電流制限動作や過
電圧時の電流遮断動作を高速化するのは必ずしも容易で
ないほか、回路構成が複雑化して高価につきやすい問題
がある。
On the other hand, the overpower protection circuit having the protection characteristic shown in FIG. 5 (b) has good protection against thermal destruction of the semiconductor element and also has protection performance against overvoltage exceeding the maximum voltage Vm. . However, the power limit start voltage Va becomes lower than the power supply voltage Vs as described above, so that the voltage V becomes
In the range of Va to Vs, even if the load side is normal, the current I is limited, so that there is a problem that the semiconductor element cannot sufficiently exhibit its inherent load driving ability. When a particularly important load is being driven, it may not be absolutely permitted that the load driving capability is reduced or lost even though the load is normal and the voltage V of the semiconductor element is lower than the power supply voltage Vs. In addition, in a protection circuit having a hyperbolic characteristic as shown in FIG. 5B, it is not always easy to speed up the current limiting operation at the time of overpower or the current interrupting operation at the time of overvoltage when the load suddenly changes. There is a problem that the configuration is complicated and the cost is high.

【0007】従来技術がもつかかる問題点に鑑み、本発
明は半導体素子に負荷の駆動能力を充分に発揮させるこ
とができ, 過電圧保護を含む保護動作が速やかな過負荷
保護回路を提供することを第1の目的とし、集積回路へ
の組み込みが容易になるようその回路構成を簡単化する
ことを第2の目的とするものである。
[0007] In view of the above problems of the prior art, the present invention provides an overload protection circuit that allows a semiconductor device to sufficiently exhibit the drive capability of a load and has a rapid protection operation including overvoltage protection. A second object is to simplify the circuit configuration so as to be easily incorporated into an integrated circuit.

【0008】[0008]

【課題を解決するための手段】上記の第1の目的は本発
明の過負荷保護回路によれば、半導体素子の主端子間電
圧が所定の最大設定値に達したとき半導体素子の制御入
力端子を制御する最大電圧保護回路と,半導体素子の主
端子間電圧が最大設定値よりも低く設定された中間設定
値を越えたとき半導体素子の制御入力端子に与える電圧
を制御する中間電圧保護回路とを設け、中間電圧保護回
路により負荷電流を電流制限値まで絞り込むよう半導体
素子の制御入力端子に与える電圧を制御し、最大電圧保
護回路により負荷電流を遮断するよう半導体素子の制御
入力端子を制御することによって達成される。なお、上
記の中間設定値は半導体素子に負荷駆動能力を発揮させ
るために電源電圧値と同程度かそれより若干高めに設定
するのがよい。また、この中間設定値を用途や必要に応
じて複数個設定して、半導体素子の主端子間電圧が各中
間設定値を越えるつどに負荷電流を順次低く設定された
電流制限値に絞って行くようにするのが有利である。
A first object of the present invention is to provide an overload protection circuit according to the present invention, wherein when a voltage between main terminals of a semiconductor device reaches a predetermined maximum set value, a control input terminal of the semiconductor device is controlled. A maximum voltage protection circuit for controlling the voltage applied to the control input terminal of the semiconductor element when the voltage between the main terminals of the semiconductor element exceeds an intermediate set value lower than the maximum set value; The intermediate voltage protection circuit controls the voltage applied to the control input terminal of the semiconductor element so as to narrow the load current to the current limit value, and the maximum voltage protection circuit controls the control input terminal of the semiconductor element so as to cut off the load current. Achieved by: Note that the above-mentioned intermediate set value is preferably set to be approximately equal to or slightly higher than the power supply voltage value in order to cause the semiconductor element to exhibit load driving capability. In addition, a plurality of the intermediate set values are set as required and necessary, and each time the voltage between the main terminals of the semiconductor device exceeds each intermediate set value, the load current is gradually reduced to the set current limit value. It is advantageous to do so.

【0009】前述の第2の目的は上記構成の過負荷保護
回路の中間電圧保護回路において、(a) 半導体素子の主
端子間電圧を受けるツェナーダイオードを組み込んで、
そのツェナー降伏電圧を中間設定値として負荷電流を絞
り込み、(b) 主端子間電圧を受ける抵抗分圧回路とその
分圧を受けるしきい値動作回路要素を組み込み、この抵
抗分圧回路の分圧比としきい値動作回路要素のしきい値
とにより中間設定値を設定して、しきい値動作回路要素
が動作したとき負荷電流を絞り込み、あるいは(c) 主端
子間電圧を受ける抵抗分圧回路とその分圧を所定の基準
電圧と比較するコンパレータを設け、抵抗分圧回路の分
圧比と基準電圧値とにより中間設定値を設定して、コン
パレータの出力に応じて負荷電流を絞り込むことにより
それぞれ達成される。なお、上記(b) 項におけるしきい
値動作回路要素としてはゲートが所定の動作しきい値を
もつMOSトランジスタや入力側に動作しきい値を有す
る論理ゲート等を適宜に用いることができる。さらに、
負荷電流を絞り込むための手段としては、中間電圧保護
回路内に半導体素子に対する制御入力電圧を受ける抵抗
分圧回路を設け、半導体素子の主端子間電圧が中間設定
値を越えたときこの抵抗分圧回路による分圧値を半導体
素子の制御入力端子に与えるようにするのが回路構成を
簡単化する上で有利である。
A second object of the present invention is to provide an intermediate voltage protection circuit of the overload protection circuit having the above-mentioned configuration, in which (a) a Zener diode for receiving a voltage between main terminals of a semiconductor element is incorporated.
The Zener breakdown voltage is set as an intermediate set value to narrow down the load current, and (b) a resistive voltage dividing circuit that receives the voltage between the main terminals and a threshold operation circuit element that receives the divided voltage are incorporated. And a threshold voltage of the threshold operation circuit element to set an intermediate set value to narrow down the load current when the threshold operation circuit element operates, or A comparator that compares the divided voltage with a predetermined reference voltage is provided, an intermediate set value is set based on the voltage division ratio of the resistance voltage divider circuit and the reference voltage value, and the load current is narrowed down according to the output of the comparator. Is done. As the threshold operation circuit element in the above item (b), a MOS transistor whose gate has a predetermined operation threshold, a logic gate having an operation threshold on the input side, or the like can be appropriately used. further,
As means for narrowing down the load current, a resistor voltage dividing circuit for receiving a control input voltage to the semiconductor element is provided in the intermediate voltage protection circuit, and when the voltage between the main terminals of the semiconductor element exceeds the intermediate set value, this resistance voltage dividing circuit is provided. Providing the divided voltage value by the circuit to the control input terminal of the semiconductor element is advantageous in simplifying the circuit configuration.

【0010】[0010]

【作用】本発明は過電圧保護を最大電圧保護回路に,過
電力保護を中間電圧保護回路にそれぞれ分担させて半導
体素子に対する保護をいわば段階的に施すことにより、
中間電圧保護回路を動作させる中間設定値を半導体素子
に負荷駆動能力を充分に発揮させるように用途ないし場
合に応じて最適値に自由に設定できるようにし、かつ最
大電圧保護回路と中間電圧保護回路を互いに独立に動作
させて過電圧保護動作と過電力保護動作を高速化しかつ
確実にするものである。
According to the present invention, the overvoltage protection is assigned to the maximum voltage protection circuit, and the overpower protection is assigned to the intermediate voltage protection circuit, so that the protection for the semiconductor element is applied stepwise.
The intermediate voltage protection circuit operates so that the intermediate set value can be freely set to the optimum value according to the application or case so that the semiconductor device can sufficiently exhibit the load driving capability, and the maximum voltage protection circuit and the intermediate voltage protection circuit Are operated independently of each other to speed up and ensure the overvoltage protection operation and the overpower protection operation.

【0011】このため前項の構成にいうように本発明の
過負荷保護回路では、最大電圧保護回路に対しては最大
設定値を設定しておいて半導体素子の主端子間電圧がこ
れに達したとき負荷電力を遮断させて半導体素子を過電
圧から保護し、中間電圧保護回路に対しては中間設定値
を最大設定値より低く設定しておいて主端子間電圧がこ
れを越えたとき負荷電流を電流制限値まで絞り込むよう
半導体素子の制御入力端子に与える電圧を制御させて半
導体素子を過電力から保護する。
Therefore, in the overload protection circuit of the present invention, as described in the configuration of the preceding paragraph, the maximum set value is set for the maximum voltage protection circuit, and the voltage between the main terminals of the semiconductor element reaches this value. When the load current is cut off, the semiconductor element is protected from overvoltage, and the intermediate set value is set lower than the maximum set value for the intermediate voltage protection circuit. The voltage applied to the control input terminal of the semiconductor device is controlled so as to narrow down to the current limit value, thereby protecting the semiconductor device from overpower.

【0012】[0012]

【実施例】以下、図面を参照しながら本発明の実施例を
説明する。図1は本発明の過負荷保護回路の実施例を電
力用半導体素子および関連回路とともに示す回路図およ
び保護特性を例示する線図、図2から図4までは本発明
のそれぞれ異なる実施例を中間電圧保護回路について電
力用半導体素子や主な関連回路とともに示す回路図であ
る。なお、これらの実施例では電力用半導体素子は電界
効果トランジスタとするが、本発明はもちろんこれに限
らず絶縁ゲートバイポーラトランジスタ等の制御入力端
子が電圧制御可能な素子全般の保護に適用できる。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an overload protection circuit according to the present invention together with a power semiconductor element and related circuits, and a diagram illustrating protection characteristics. FIGS. 2 to 4 show intermediate examples of different embodiments of the present invention. FIG. 3 is a circuit diagram illustrating a voltage protection circuit together with a power semiconductor element and main related circuits. In these embodiments, the power semiconductor element is a field-effect transistor. However, the present invention is not limited to this, and the present invention can be applied to general protection of elements such as an insulated gate bipolar transistor whose control input terminal can be voltage-controlled.

【0013】図1(a) のように、電力用半導体素子1な
いし上述の電界効果トランジスタの保護用に本発明では
それぞれ一点鎖線で囲んで示した最大電圧保護回路10と
中間電圧保護回路20を用いるが、その説明に入る前にま
ず図の関連回路を説明する。半導体素子1の出力端子To
と接地端子Eの間に電源2と負荷3が直列接続され、半
導体素子1はその制御入力端子に駆動回路4から負荷3
に流す電流を指定する制御入力電圧Vcを受けている。駆
動回路4は例えばシュミット回路や増幅回路を含み、外
部から受ける駆動指令Sdに応じてこの制御入力電圧Vcを
この実施例では単に5Vのハイの論理状態で出力するも
のである。
As shown in FIG. 1A, in order to protect the power semiconductor device 1 or the above-mentioned field-effect transistor, in the present invention, a maximum voltage protection circuit 10 and an intermediate voltage protection circuit 20, which are respectively enclosed by dashed lines, are provided. Before using the description, first, the related circuit shown in the figure will be described. Output terminal To of semiconductor element 1
A power supply 2 and a load 3 are connected in series between the power supply 2 and a ground terminal E.
Receiving the control input voltage Vc that specifies the current flowing through the control input voltage Vc. The drive circuit 4 includes, for example, a Schmitt circuit and an amplifier circuit, and outputs the control input voltage Vc in a high logic state of only 5 V in this embodiment according to a drive command Sd received from the outside.

【0014】さらに、図の例では負荷3に流れる電流を
検出するために半導体素子1の接地端子E側に電流検出
抵抗1aが接続され、その電圧降下が電流の実際値信号と
して演算増幅器5の一方の入力に与えられる。この演算
増幅器5は他方の入力に基準電圧Vrを図の例では抵抗27
aを介して負荷電流の目標値信号として受け、これと電
流実際値の差信号を上述の制御入力電圧Vcの値をアナロ
グ制御する制御トランジスタ6の図の例ではゲートであ
る入力に与える。容易にわかるように、半導体素子1と
演算増幅器5と制御トランジスタ6を含む高ゲインの自
動制御系により負荷電流は電流検出抵抗1aによるその実
際値が基準電圧Vrによる目標値と正確に一致するように
制御される。
Further, in the example shown in the figure, a current detecting resistor 1a is connected to the ground terminal E of the semiconductor element 1 for detecting a current flowing through the load 3, and the voltage drop of the current detecting resistor 1a is used as an actual current signal of the operational amplifier 5, Given to one input. The operational amplifier 5 has a reference voltage Vr applied to the other input and a resistor 27 in the example shown in FIG.
The control transistor 6 receives the target value signal of the load current as a target value signal via a, and supplies a difference signal between the target value signal and the actual current value to an input, which is a gate in the illustrated example of the control transistor 6 for analogly controlling the value of the control input voltage Vc. As can be easily understood, the load current is controlled by the high gain automatic control system including the semiconductor element 1, the operational amplifier 5 and the control transistor 6 so that the actual value of the current detection resistor 1a exactly matches the target value of the reference voltage Vr. Is controlled.

【0015】最大電圧保護回路10は図のように単一のコ
ンパレータ11からなる簡単な構成のものでよく、図には
駆動回路4と別個に示すが実際にはそれに組み込んでし
まうのがよい。コンパレータ11は一方の入力に半導体素
子1に許容できる最大電圧である最大設定値Vmを, 他方
の入力に出力端子Toの電圧を半導体素子1の主端子間電
圧Vとしてそれぞれ受け、出力が半導体素子1への制御
入力電圧Vcの供給点に接続される。出力端子Toの電圧は
電流検出抵抗1aの電圧降下分を含むが、それによる誤差
は些少なので実用上は半導体素子1の主端子間電圧Vと
してよい。この最大電圧保護回路10は制御電源電圧Vdの
給電下で動作し、主端子間電圧Vが最大設定値Vmに達し
たときコンパレータ11の出力のローにより制御入力電圧
Vcを接地電位に下げて半導体素子1をオフさせる。
The maximum voltage protection circuit 10 may have a simple configuration comprising a single comparator 11 as shown in the figure. The maximum voltage protection circuit 10 is shown separately from the drive circuit 4 in the figure, but is preferably incorporated in the drive circuit 4 in practice. The comparator 11 receives, at one input, a maximum set value Vm, which is the maximum voltage allowable to the semiconductor element 1, and receives, at the other input, the voltage of the output terminal To as a voltage V between the main terminals of the semiconductor element 1. 1 is connected to the supply point of the control input voltage Vc. Although the voltage at the output terminal To includes a voltage drop of the current detection resistor 1a, an error caused by the voltage drop is insignificant, so that the voltage V between the main terminals of the semiconductor element 1 may be used practically. The maximum voltage protection circuit 10 operates under the power supply of the control power supply voltage Vd. When the main terminal voltage V reaches the maximum set value Vm, the output of the comparator 11 becomes low and the control input voltage Vd becomes low.
The semiconductor device 1 is turned off by lowering Vc to the ground potential.

【0016】図1(a) の中間電圧保護回路20では、半導
体素子1の主端子間電圧Vを受けるツェナーダイオード
21の降伏電圧により中間設定値を設定し、主端子間電圧
Vがこの設定値を越えたとき半導体素子1の過電力保護
のため一対の抵抗27aと27bからなる分圧回路と演算増
幅器5を利用して負荷3の電流を低い値に絞り込む。ツ
ェナーダイオード21には電流制限抵抗21aと接地側の検
出抵抗22を接続して、その降伏時に検出抵抗22から検出
信号をナンドゲート24の一方の入力に与える。ナンドゲ
ート24は他方の入力に制御電源電圧Vdを受けており、検
出信号を受けたときその出力のローによって抵抗27bを
接地する。これにより、演算増幅器5は基準電圧Vrの分
圧回路による分圧値を新しい制御目標値として受けて、
負荷3に流す電流をそれまでより低い一定値に制御す
る。
In the intermediate voltage protection circuit 20 shown in FIG. 1A, a Zener diode receiving a voltage V between main terminals of the semiconductor element 1 is used.
An intermediate set value is set by the breakdown voltage of 21. When the voltage V between the main terminals exceeds this set value, the voltage divider circuit composed of a pair of resistors 27a and 27b and the operational amplifier 5 are connected to protect the semiconductor element 1 from overpower. The current of the load 3 is narrowed down to a low value by utilizing this. A current limiting resistor 21a and a ground-side detection resistor 22 are connected to the Zener diode 21, and a detection signal is applied from the detection resistor 22 to one input of a NAND gate 24 at the time of breakdown. The NAND gate 24 receives the control power supply voltage Vd at the other input, and when the detection signal is received, a low level of the output grounds the resistor 27b. Thereby, the operational amplifier 5 receives the divided voltage value of the reference voltage Vr by the voltage dividing circuit as a new control target value,
The current flowing through the load 3 is controlled to a lower constant value.

【0017】図1(b) に図1(a) の実施例に対応する保
護特性Aを示す。図の横軸は半導体素子1の主端子間電
圧V, 縦軸は負荷電流Iであり、図にはこの特性Aのほ
かに前述の図5(b) の従来の特性Cが参考用に重ねて示
されている。本発明の場合の保護特性Aは図示のように
中間設定値Viと最大設定値Vmにより区分された3個の電
圧領域A1,A2,A3に階段状に別れている。主端子間電圧
Vが中間設定値Viより低い電圧領域A1は中間電圧保護回
路20がまだ動作しない領域であって、ここでは負荷電流
Iが前述のように基準電圧Vrにより指定された目標値に
応じて一定制御される。中間設定値Viは本発明ではこの
実施例のように電源電圧Vsと同じか若干高めに設定する
のがよく、これによって電圧領域A1内で半導体素子1に
その負荷駆動能力を充分に発揮させることができる。
FIG. 1 (b) shows a protection characteristic A corresponding to the embodiment of FIG. 1 (a). The horizontal axis in the figure is the voltage V between the main terminals of the semiconductor device 1 and the vertical axis is the load current I. In the figure, in addition to this characteristic A, the above-mentioned conventional characteristic C in FIG. Shown. As shown, the protection characteristic A in the case of the present invention is divided into three voltage regions A1, A2, A3 divided by an intermediate set value Vi and a maximum set value Vm in a stepwise manner. The voltage region A1 in which the main terminal voltage V is lower than the intermediate set value Vi is a region where the intermediate voltage protection circuit 20 does not operate yet. Here, the load current I is set to the target value specified by the reference voltage Vr as described above. Constant control is performed accordingly. In the present invention, the intermediate set value Vi is preferably set to be equal to or slightly higher than the power supply voltage Vs as in this embodiment, so that the semiconductor element 1 can sufficiently exhibit its load driving capability in the voltage range A1. Can be.

【0018】主端子間電圧が中間設定値Viを越えると電
圧領域A2に入るが、この領域内での負荷電流Iは半導体
素子1が熱的に破壊するおそれがない範囲に設定する必
要があるが、実際面では負荷3がもつ特質, とくに誘導
性負荷としての過渡的特性を考慮して設定するのが合理
的である。この負荷電流の値は前述のように中間電圧保
護回路20内の抵抗27aと27bからなる分圧回路の分圧比
により設定され、演算増幅器5が負荷電流Iをこの設定
に応じた一定値に制御する。
When the voltage between the main terminals exceeds the intermediate set value Vi, the voltage enters the voltage region A2. In this region, the load current I must be set within a range where the semiconductor element 1 is not likely to be thermally damaged. However, in practice, it is reasonable to consider the characteristics of the load 3, especially the transient characteristics as an inductive load. The value of the load current is set by the voltage dividing ratio of the voltage dividing circuit including the resistors 27a and 27b in the intermediate voltage protection circuit 20 as described above, and the operational amplifier 5 controls the load current I to a constant value according to this setting. I do.

【0019】最大電圧保護回路10を動作させる最大設定
値Vmは従来の図5(a) の例と同様に電源電圧Vsのふつう
は 1.5〜2倍の範囲に設定するのがよく、主端子間電圧
Vがこの設定値に到達した後の電圧領域A3では半導体素
子1がオフして負荷電流Iが遮断される。図5(a) に対
応する従来の特性Cでは、主端子間電圧Vが高まるにつ
れて負荷電流Iの減少率が図のように小さくなって来る
ため、半導体素子1に許容する最大電圧値が変動したり
ばらついたりしやすいが、本発明では最大電圧保護回路
10によって主端子間電圧Vを最大設定値Vm以下に抑えて
半導体素子1に確実な過電圧保護を施すことができる。
The maximum set value Vm for operating the maximum voltage protection circuit 10 is preferably set to a range of 1.5 to 2 times the power supply voltage Vs, as in the conventional example of FIG. In the voltage region A3 after the voltage V reaches this set value, the semiconductor element 1 is turned off and the load current I is cut off. In the conventional characteristic C corresponding to FIG. 5A, the decrease rate of the load current I decreases as the main terminal voltage V increases as shown in the figure, so that the maximum voltage value allowed for the semiconductor element 1 varies. Although it is easy to fluctuate and vary, in the present invention the maximum voltage protection circuit
By using 10, the voltage V between the main terminals can be suppressed to the maximum set value Vm or less, and the semiconductor element 1 can be reliably protected from overvoltage.

【0020】図2以降には本発明の実施例を中間電圧保
護回路20について示す。図1(a) の電源2と負荷3は図
の簡単化のために省かれている。また、図1(a) の電流
検出抵抗1a, 演算増幅器5および制御トランジスタ6か
らなる負荷電流Iの制御系も省かれているが、以下に述
べる実施例のいずれでもこの電流制御系の利用ないしそ
れとの併用がもちろん可能である。
An embodiment of the present invention is shown in FIG. The power supply 2 and the load 3 in FIG. 1A are omitted for simplification of the drawing. Although the control system for the load current I comprising the current detection resistor 1a, the operational amplifier 5 and the control transistor 6 in FIG. 1A is omitted, the use of this current control system is not required in any of the following embodiments. Of course, it can be used together.

【0021】図2の実施例の中間電圧保護回路20では、
主端子間電圧Vを受ける一対の抵抗23aと23bからなる
抵抗分圧回路と, その分圧を受けるしきい値動作回路要
素としてのナンドゲート24とを用い、抵抗分圧回路の分
圧比とナンドゲートの入力の動作しきい値により中間設
定値Viを設定する。このためナンドゲート24の一方の入
力に抵抗分圧回路による分圧を与えるが、他方の入力に
は図の例では抵抗28とキャパシタ29からなる時定数回路
を介して制御入力電圧Vcのハイを与える。このナンドゲ
ート24の出力は主端子間電圧Vが中間設定値Viを越える
とローになって抵抗27bを接地するので、制御入力電圧
Vcが一対の抵抗27aと27bからなる抵抗分圧回路により
分圧された上で半導体素子1の制御入力端子に与えら
れ、従って負荷電流Iが絞られる。なお、図の例では抵
抗27aと27bを含む抵抗分圧回路により半導体素子1を
直接制御し、その分圧比により負荷電流Iを設定するよ
うになっているが、この抵抗分圧回路によって図1(a)
の演算増幅器5に与える基準電圧Vr側の入力を制御する
ようにしてもよい。
In the intermediate voltage protection circuit 20 of the embodiment shown in FIG.
Using a resistance voltage dividing circuit composed of a pair of resistors 23a and 23b for receiving the voltage V between the main terminals and a NAND gate 24 as a threshold operation circuit element for receiving the divided voltage, the voltage dividing ratio of the resistance voltage dividing circuit and the NAND gate The intermediate setting value Vi is set according to the input operation threshold value. For this reason, although the voltage divided by the resistance voltage dividing circuit is applied to one input of the NAND gate 24, the high of the control input voltage Vc is applied to the other input through a time constant circuit composed of a resistor 28 and a capacitor 29 in the example of FIG. . The output of the NAND gate 24 goes low when the voltage V between the main terminals exceeds the intermediate set value Vi and grounds the resistor 27b.
The voltage Vc is divided by a resistance voltage dividing circuit composed of a pair of resistors 27a and 27b and then applied to the control input terminal of the semiconductor element 1, so that the load current I is reduced. In the example shown in the drawing, the semiconductor element 1 is directly controlled by a resistance voltage dividing circuit including the resistors 27a and 27b, and the load current I is set by the voltage dividing ratio. (a)
Of the reference voltage Vr supplied to the operational amplifier 5 may be controlled.

【0022】図3の実施例の中間電圧保護回路20では2
個の中間設定値を設定する。一方の例えば低い方の中間
設定値は抵抗23aと23bからなる抵抗分圧回路とゲート
動作しきい値をもつトランジスタ25により設定され、ト
ランジスタ25がオンしたとき制御入力電圧Vcを抵抗27a
とこのトランジスタ25のオン抵抗による分圧で低めて半
導体素子1に与えることにより負荷電流Iを絞る。他方
の例えば高い方の中間設定値はツェナーダイオード21と
その電流制限抵抗21aと検出抵抗22を含む直列回路によ
り設定され、検出抵抗22の検出信号により上とは別のト
ランジスタ25がオンしたとき、抵抗27aと今度は2個の
トランジスタ25の並列接続のオン抵抗により制御入力電
圧Vcを分圧, 低下させて半導体素子1に与えることによ
り、負荷電流Iをさらにもう1段絞り込むようにする。
In the intermediate voltage protection circuit 20 of the embodiment shown in FIG.
Set intermediate setting values. On the other hand, for example, the lower intermediate set value is set by a resistor voltage dividing circuit composed of resistors 23a and 23b and a transistor 25 having a gate operation threshold value. When the transistor 25 is turned on, the control input voltage Vc is changed by a resistor 27a.
The load current I is reduced by reducing the voltage by the voltage division due to the on-resistance of the transistor 25 and applying the reduced voltage to the semiconductor element 1. On the other hand, for example, a higher intermediate set value is set by a series circuit including a Zener diode 21, its current limiting resistor 21a, and a detection resistor 22, and when a transistor 25 different from the above is turned on by a detection signal of the detection resistor 22, The control input voltage Vc is divided and reduced by the resistor 27a and the on-resistance of the two transistors 25 connected in parallel, and the divided voltage is applied to the semiconductor element 1, so that the load current I is further reduced by one stage.

【0023】この図3の実施例では、図1(b) の中間設
定値Viを2個設定して負荷電流Iを2段に絞り込むこと
により半導体素子1にその熱特性や負荷3の特質に一層
よく適合した過電力保護を施すことができる。また、ト
ランジスタ25に分圧用抵抗やしきい値動作回路要素の機
能を兼ねさせることにより、2段の保護にも拘わらず回
路全体を簡単な構成で済ませることができる。なお、保
護はこの2段に限らず必要に応じてさらに多段とするこ
とができる。
In the embodiment shown in FIG. 3, two intermediate setting values Vi shown in FIG. 1B are set and the load current I is narrowed down to two stages. Better adapted overpower protection can be provided. Further, by making the transistor 25 also function as a voltage-dividing resistor and a threshold operation circuit element, the entire circuit can be completed with a simple configuration irrespective of two-stage protection. The protection is not limited to the two stages, but may be further increased as necessary.

【0024】次の図4の実施例の中間電圧保護回路20で
は抵抗23aと23bからなる抵抗分圧回路とその分圧を受
けるコンパレータ26とにより中間設定値を設定する。コ
ンパレータ26は主端子間電圧Vの分圧を中間設定値用の
基準電圧Vrと比較して前者が後者を越すとその出力をロ
ーにする。この実施例でもコンパレータ26を構成するト
ランジスタのオン抵抗が抵抗27aとともに抵抗分圧回路
の構成に利用される。従って、コンパレータ26の出力が
ローになると制御入力電圧Vcはこの分圧回路により低め
られた上で半導体素子1に与えられ、これにより負荷電
流Iが分圧比で設定された値に絞られる。
In the intermediate voltage protection circuit 20 of the embodiment shown in FIG. 4, an intermediate set value is set by a resistor voltage dividing circuit composed of resistors 23a and 23b and a comparator 26 receiving the divided voltage. The comparator 26 compares the divided voltage of the voltage V between the main terminals with the reference voltage Vr for the intermediate set value. When the former exceeds the latter, the output is made low. Also in this embodiment, the on-resistance of the transistor forming the comparator 26 is used together with the resistor 27a in the configuration of the resistor voltage dividing circuit. Accordingly, when the output of the comparator 26 becomes low, the control input voltage Vc is reduced by the voltage dividing circuit and then applied to the semiconductor element 1, whereby the load current I is reduced to a value set by the voltage dividing ratio.

【0025】以上の図1〜図5の実施例からもわかるよ
うに、本発明で用いる最大電圧保護回路10と中間電圧保
護回路20はツェナーダイオード,抵抗,論理ゲート,コ
ンパレータ,制御トランジスタ等の回路要素を組み合わ
せたいずれもごく簡単な回路構成なので動作に時間をほ
とんど要せず、かつ動作に狂いが生じることも非常に少
ない。従って、本発明回路によって電力用半導体素子に
対し高速でかつ確実な過負荷保護を施すことができる。
As can be seen from the embodiments shown in FIGS. 1 to 5, the maximum voltage protection circuit 10 and the intermediate voltage protection circuit 20 used in the present invention are composed of circuits such as a Zener diode, a resistor, a logic gate, a comparator and a control transistor. Since all of the combined elements have a very simple circuit configuration, the operation requires little time, and the operation is hardly disrupted. Therefore, the circuit of the present invention can provide high-speed and reliable overload protection for the power semiconductor device.

【0026】[0026]

【発明の効果】以上に述べたとおり本発明の電力用過負
荷保護回路では、半導体素子の主端子間電圧が最大設定
値に達したとき半導体素子の制御入力端子を制御する最
大電圧保護回路と,主端子間電圧が最大設定値より低く
設定された中間設定値を越えたとき半導体素子の制御入
力電圧を制御する中間電圧保護回路とを用い、まず中間
電圧保護回路により負荷電流を所定の電流制限値まで絞
って過電力保護を施し、次に必要に応じて最大電圧保護
回路により負荷電流を遮断して過電圧保護を施すことに
より、次の効果を挙げることができる。
As described above, in the power overload protection circuit according to the present invention, the maximum voltage protection circuit for controlling the control input terminal of the semiconductor element when the voltage between the main terminals of the semiconductor element reaches the maximum set value is provided. And an intermediate voltage protection circuit for controlling a control input voltage of the semiconductor element when the voltage between the main terminals exceeds an intermediate set value lower than the maximum set value. The following effects can be obtained by performing overpower protection by narrowing down to the limit value and then performing overvoltage protection by cutting off the load current by the maximum voltage protection circuit as necessary.

【0027】(a) 中間電圧保護回路を動作させる中間設
定値を半導体素子の熱特性や負荷の特質に応じて最適の
値に設定できるので、これを動作させる過電力保護領域
内において半導体素子にそれが電源電圧の給電下で本来
もっている負荷の駆動能力を充分に発揮させることがで
きる。 (b) 過電力保護を中間電圧保護回路に,過電圧保護を最
大電圧保護回路にそれぞれ分担させかつ互いに独立に保
護動作をさせることにより、過電力保護および過電圧保
護の動作を高速化しかつ確実にすることができる。
(A) The intermediate set value for operating the intermediate voltage protection circuit can be set to an optimum value according to the thermal characteristics of the semiconductor device and the characteristics of the load. This makes it possible to sufficiently exhibit the inherent drive capability of the load under the supply of the power supply voltage. (b) Speeding up and ensuring the operation of overpower protection and overvoltage protection by assigning overvoltage protection to the intermediate voltage protection circuit and overvoltage protection to the maximum voltage protection circuit, and performing protection operations independently of each other. be able to.

【0028】(c) 半導体素子に対する過電力保護と過電
圧保護を段階的に施すことにより、従来のように双曲線
状の保護特性をもたせる保護回路に比べて保護特性を単
純化して、過電力と過電圧の双方に対する保護性能を備
えるにも拘わらず回路の全体構成を簡単化して集積回路
への組み込みを容易にすることができる。なお、中間設
定値を電源電圧値と同程度かそれより若干高めに設定す
る態様は半導体素子に負荷駆動能力を充分発揮させる上
で一層有利であり、中間設定値を複数個設定して主端子
間電圧が各中間設定値を越えるつどに中間電圧保護回路
に負荷電流を順次低下する電流制限値に絞らせる態様は
過電力保護性能を向上する上で有利である。
(C) By providing over-power protection and over-voltage protection for the semiconductor element in a stepwise manner, the protection characteristics are simplified as compared with a conventional protection circuit having a hyperbolic protection characteristic, and over-power and over-voltage protection are performed. Despite having the protection performance for both, the overall configuration of the circuit can be simplified to facilitate incorporation into an integrated circuit. The mode in which the intermediate set value is set to be approximately the same as or slightly higher than the power supply voltage value is more advantageous for sufficiently exhibiting the load driving capability of the semiconductor device. It is advantageous to improve the overpower protection performance by causing the intermediate voltage protection circuit to reduce the load current to a current limit value that decreases sequentially each time the intermediate voltage exceeds each intermediate set value.

【0029】さらに、中間電圧保護回路に対して、(a)
半導体素子の主端子間電圧を受けるツェナーダイオード
を組み込んで、その降伏電圧を中間設定値として負荷電
流を絞り込み、(b) 主端子間電圧を受ける抵抗分圧回路
とその分圧を受けるしきい値動作回路要素を組み込み、
前者の分圧比と後者のしきい値とにより中間設定値を設
定して、しきい値動作回路要素が動作したとき負荷電流
を絞り込み、あるいは(c) 主端子間電圧を受ける抵抗分
圧回路とその分圧を所定の基準電圧と比較するコンパレ
ータを組み込み、前者の分圧比と基準電圧値とにより中
間設定値を設定して、コンパレータの出力に応じ負荷電
流を絞り込む態様は、いずれも中間電圧保護回路の構成
を簡単化しその動作信頼性を高める上で有利である。ま
た、中間電圧保護回路により負荷電流を絞り込む手段と
して半導体素子に対する制御入力電圧を受ける抵抗分圧
回路を設けて、それによる制御入力電圧の分圧値を半導
体素子に与える態様は回路構成を簡単化する上でとくに
有利である。
Further, with respect to the intermediate voltage protection circuit, (a)
Incorporating a Zener diode that receives the voltage between the main terminals of the semiconductor element, narrows down the load current using the breakdown voltage as an intermediate set value, and Incorporating operating circuit elements,
An intermediate set value is set according to the former voltage dividing ratio and the latter threshold, and the load current is narrowed down when the threshold operation circuit element operates, or (c) a resistive voltage dividing circuit receiving the voltage between the main terminals. A comparator for comparing the divided voltage with a predetermined reference voltage is incorporated, an intermediate set value is set based on the former divided ratio and the reference voltage value, and the load current is narrowed according to the output of the comparator. This is advantageous in simplifying the configuration of the circuit and improving its operation reliability. Further, as a means for narrowing down the load current by the intermediate voltage protection circuit, a resistance voltage dividing circuit for receiving a control input voltage to the semiconductor element is provided, and the divided voltage of the control input voltage is applied to the semiconductor element to simplify the circuit configuration. It is particularly advantageous in doing so.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を電力用半導体素子および関連
回路とともに示し、同図(a) は本発明による過負荷保護
回路の一実施例の回路図、同図(b) はその保護特性例を
示す線図である。
1 shows an embodiment of the present invention together with a power semiconductor device and related circuits. FIG. 1 (a) is a circuit diagram of an embodiment of an overload protection circuit according to the present invention, and FIG. 1 (b) is a protection characteristic thereof. It is a diagram showing an example.

【図2】本発明の異なる実施例を中間電圧保護回路につ
いて主な関連回路とともに示す回路図である。
FIG. 2 is a circuit diagram showing a different embodiment of the present invention for an intermediate voltage protection circuit together with main related circuits.

【図3】本発明のさらに異なる実施例を中間電圧保護回
路について主な関連回路とともに示す回路図である。
FIG. 3 is a circuit diagram showing still another embodiment of the present invention together with main related circuits for an intermediate voltage protection circuit.

【図4】本発明のもう一つの異なる実施例を中間電圧保
護回路について主な関連回路とともに示す回路図であ
る。
FIG. 4 is a circuit diagram showing another different embodiment of the present invention for an intermediate voltage protection circuit together with main related circuits.

【図5】従来の保護回路の代表的な例を保護特性面から
示し、同図(a) は従来の過電圧保護回路の保護特性を示
す線図、同図(b) は従来の過電力保護回路の保護特性を
示す線図である。
FIG. 5 shows a typical example of a conventional protection circuit in terms of protection characteristics. FIG. 5 (a) is a diagram showing the protection characteristics of a conventional overvoltage protection circuit, and FIG. 5 (b) is a conventional overpower protection circuit. FIG. 3 is a diagram illustrating protection characteristics of a circuit.

【符号の説明】[Explanation of symbols]

1 保護対象としての電力用半導体素子 2 電源 3 負荷 4 駆動回路 5 負荷電流制御用の演算増幅器 6 負荷電流制御用の制御トランジスタ 10 最大電圧保護回路 11 コンパレータ 20 中間電圧保護回路 21 ツェナーダイオード 22 検出抵抗 23a, 23b 抵抗分圧回路用の抵抗 24 ナンドゲート 25 トランジスタ 26 コンパレータ 27a, 27b 抵抗分圧回路用の抵抗 A 本発明による保護特性 B 従来の過電圧保護特性 C 従来の過電力保護特性 I 負荷電流 V 半導体素子の主端子間電圧 Vc 半導体素子の制御入力電圧 Vd 制御電源電圧 Vi 中間設定値 Vm 最大設定値 Vs 電源電圧 DESCRIPTION OF SYMBOLS 1 Power semiconductor element to be protected 2 Power supply 3 Load 4 Drive circuit 5 Operational amplifier for load current control 6 Control transistor for load current control 10 Maximum voltage protection circuit 11 Comparator 20 Intermediate voltage protection circuit 21 Zener diode 22 Detection resistor 23a, 23b Resistor for resistor divider circuit 24 NAND gate 25 Transistor 26 Comparator 27a, 27b Resistor for resistor divider circuit A Protection characteristic according to the present invention B Conventional overvoltage protection characteristic C Conventional overpower protection characteristic I Load current V Semiconductor Element main terminal voltage Vc Semiconductor element control input voltage Vd Control power supply voltage Vi Intermediate set value Vm Maximum set value Vs Power supply voltage

フロントページの続き (56)参考文献 特開 平5−327440(JP,A) 特開 平3−40517(JP,A) 特開 平5−275999(JP,A) 特開 平5−267580(JP,A) 特開 平3−293814(JP,A) 特開 平3−106217(JP,A) 特開 平2−128205(JP,A) 特開 平5−299990(JP,A) 特開 平6−291631(JP,A) 実開 平6−16884(JP,U) (58)調査した分野(Int.Cl.7,DB名) H03K 17/00 - 17/70 Continuation of front page (56) References JP-A-5-327440 (JP, A) JP-A-3-40517 (JP, A) JP-A-5-275999 (JP, A) JP-A-5-267580 (JP) JP-A-3-293814 (JP, A) JP-A-3-106217 (JP, A) JP-A-2-128205 (JP, A) JP-A-5-299990 (JP, A) 6-291631 (JP, A) Japanese Utility Model Hei 6-16884 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H03K 17/00-17/70

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電源に直列接続された負荷に流す電流を制
御する電力用半導体素子を過負荷から保護するための回
路であって、半導体素子の主端子間に掛かる電圧が所定
の最大設定値に達したとき半導体素子の制御入力端子を
制御する最大電圧保護回路と、半導体素子の主端子間の
電圧が最大設定値より低く設定された中間設定値を越え
たとき半導体素子の制御入力端子に与える電圧を制御す
る中間電圧保護回路とを設け、中間電圧保護回路により
負荷電流を電流制限値まで絞るよう半導体素子の制御入
力端子に与える電圧を制御し、最大電圧保護回路により
負荷電流を遮断するよう半導体素子の制御入力端子を制
御するようにしたことを特徴とする電力用半導体素子の
過負荷保護回路。
A circuit for protecting a power semiconductor element for controlling a current flowing to a load connected in series to a power supply from an overload, wherein a voltage applied between main terminals of the semiconductor element is a predetermined maximum set value. A maximum voltage protection circuit that controls the control input terminal of the semiconductor element when the voltage reaches the intermediate input value that is set lower than the maximum set value. An intermediate voltage protection circuit for controlling the applied voltage, the voltage applied to the control input terminal of the semiconductor element is controlled by the intermediate voltage protection circuit so as to reduce the load current to the current limit value, and the load current is interrupted by the maximum voltage protection circuit An overload protection circuit for a power semiconductor device, wherein a control input terminal of the semiconductor device is controlled.
【請求項2】請求項1に記載の回路において、複数の中
間設定値を設定して半導体素子の主端子間電圧が各中間
設定値を越えるつど中間電圧保護回路により負荷電流を
順次に低下する電流制限値に絞るようにしたことを特徴
とする電力用半導体素子の過負荷保護回路。
2. The circuit according to claim 1, wherein a plurality of intermediate set values are set, and the load current is sequentially reduced by the intermediate voltage protection circuit whenever the voltage between the main terminals of the semiconductor device exceeds each intermediate set value. An overload protection circuit for a power semiconductor device, wherein the overload protection circuit is limited to a current limit value.
【請求項3】請求項1に記載の回路において、中間設定
値を電源電圧の値と同程度ないしそれよりも若干高めに
設定するようにしたことを特徴とする電力用半導体素子
の過負荷保護回路。
3. The overload protection of a power semiconductor device according to claim 1, wherein the intermediate set value is set to be equal to or slightly higher than the value of the power supply voltage. circuit.
【請求項4】請求項1に記載の回路において、半導体素
子の主端子間電圧を受けるツェナーダイオードを中間電
圧保護回路に設けてそのツェナー降伏電圧を中間設定値
として負荷電流を絞り込む制御動作をさせるようにした
ことを特徴とする電力用半導体素子の過負荷保護回路。
4. A circuit according to claim 1, wherein a Zener diode for receiving a voltage between main terminals of the semiconductor element is provided in the intermediate voltage protection circuit, and a control operation for narrowing down a load current is performed by using the Zener breakdown voltage as an intermediate set value. An overload protection circuit for a power semiconductor device, characterized in that:
【請求項5】請求項1に記載の回路において、中間電圧
保護回路内に半導体素子の主端子間電圧を受ける抵抗分
圧回路およびその分圧を受けるしきい値動作回路要素を
設けて、抵抗分圧回路の分圧比としきい値動作回路要素
のしきい値とにより中間設定値を設定し、しきい値動作
回路要素が動作したときに負荷電流を絞り込む制御動作
を行なわせるようにしたことを特徴とする電力用半導体
素子の過負荷保護回路。
5. The circuit according to claim 1, further comprising a resistor voltage dividing circuit for receiving a voltage between the main terminals of the semiconductor element and a threshold voltage operation circuit element for receiving the divided voltage in the intermediate voltage protection circuit. An intermediate set value is set based on a voltage dividing ratio of a voltage dividing circuit and a threshold value of a threshold operation circuit element, and a control operation for reducing a load current is performed when the threshold operation circuit element operates. Characteristic overload protection circuit for power semiconductor devices.
【請求項6】請求項1に記載の回路において、中間電圧
保護回路内に半導体素子の主端子間電圧を受ける抵抗分
圧回路およびその分圧を所定の基準電圧値と比較するコ
ンパレータを設け、抵抗分圧回路の分圧比と基準電圧値
とにより中間設定値を設定し、コンパレータの出力に応
じて負荷電流を絞り込む動作をさせるようにしたことを
特徴とする電力用半導体素子の過負荷保護回路。
6. The circuit according to claim 1, further comprising a resistor voltage dividing circuit for receiving a voltage between the main terminals of the semiconductor element and a comparator for comparing the divided voltage with a predetermined reference voltage value in the intermediate voltage protection circuit. An overload protection circuit for a power semiconductor element, wherein an intermediate set value is set based on a voltage dividing ratio of a resistance voltage dividing circuit and a reference voltage value, and an operation of narrowing a load current according to an output of a comparator is performed. .
【請求項7】請求項1に記載の回路において、中間電圧
保護回路内に半導体素子に対する制御入力電圧を受ける
抵抗分圧回路を設け、半導体素子の主端子間電圧が中間
設定値を越えたときにその分圧を半導体素子の制御入力
端子に与えることにより負荷電流を絞り込むようにした
ことを特徴とする電力用半導体素子の過負荷保護回路。
7. The circuit according to claim 1, further comprising a resistor voltage dividing circuit for receiving a control input voltage for the semiconductor element in the intermediate voltage protection circuit, wherein a voltage between main terminals of the semiconductor element exceeds an intermediate set value. A load current is narrowed by applying the divided voltage to a control input terminal of the semiconductor element.
JP06090399A 1994-04-28 1994-04-28 Overload protection circuit for power semiconductor devices Expired - Fee Related JP3139276B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06090399A JP3139276B2 (en) 1994-04-28 1994-04-28 Overload protection circuit for power semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06090399A JP3139276B2 (en) 1994-04-28 1994-04-28 Overload protection circuit for power semiconductor devices

Publications (2)

Publication Number Publication Date
JPH07297697A JPH07297697A (en) 1995-11-10
JP3139276B2 true JP3139276B2 (en) 2001-02-26

Family

ID=13997513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06090399A Expired - Fee Related JP3139276B2 (en) 1994-04-28 1994-04-28 Overload protection circuit for power semiconductor devices

Country Status (1)

Country Link
JP (1) JP3139276B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7666995B2 (en) 2000-11-03 2010-02-23 Pestka Biomedical Laboratories Interferons, uses and compositions related thereto

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3308545B2 (en) * 1996-04-18 2002-07-29 カネボウ株式会社 Near-infrared absorbing film and multilayer panel including the film
DE19722300A1 (en) * 1997-05-28 1998-12-03 Bosch Gmbh Robert Overtemperature protection circuit
US6717785B2 (en) 2000-03-31 2004-04-06 Denso Corporation Semiconductor switching element driving circuit
JP5645782B2 (en) 2011-09-14 2014-12-24 三菱電機株式会社 Power module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7666995B2 (en) 2000-11-03 2010-02-23 Pestka Biomedical Laboratories Interferons, uses and compositions related thereto

Also Published As

Publication number Publication date
JPH07297697A (en) 1995-11-10

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