JP3132880B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for miniaturizing a MOS (Metal Oxide Semiconductor) transistor.

[0002]

2. Description of the Related Art Conventionally, as the density of semiconductor integrated circuits has increased, it has been required to reduce the gate length of MOS transistors as much as possible. As is well known, the gate length of a MOS transistor is determined by a minimum dimension (also called a minimum rule) that can be resolved by lithography. For example, in photolithography using ultraviolet light,
The minimum rule is about 0.6 μm due to the limit of the exposure wavelength.

[0003]

As described above, as described above, MOS
Since the gate length of a transistor is determined by the minimum rule of lithography, it is difficult to realize a gate shorter than the minimum rule.

The present invention has been made in view of such circumstances, and aims at shortening the channel length of a MOS transistor by making the gate length of the MOS transistor shorter than the minimum rule based on the limit of the resolution of lithography. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be used.

[0005]

The present invention has the following configuration in order to achieve the above object. That is, a method of manufacturing a semiconductor device according to the present invention includes the steps of: depositing a polysilicon film containing a high concentration impurity of a second conductivity type on a semiconductor substrate of a first conductivity type; Forming a source and drain extraction electrode, forming a side wall spacer containing a low-concentration impurity of a second conductivity type on a side surface of the extraction electrode, and forming the extraction electrode and the side wall. By subjecting the substrate on which the spacers are formed to heat treatment, a gate oxide film is formed between the side wall spacers facing each other, and a source, which is a high-concentration impurity diffusion layer of the second conductivity type, is formed in the substrate below each of the extraction electrodes. A diffusion layer and a drain diffusion layer, and a second conductivity type low-concentration impurity diffusion layer in the substrate below the sidewall spacer. A step of forming on, the extraction electrode and the sidewall spacer as a mask, is the gate electrode that includes a step of forming by self-alignment, a.

[0006]

According to the present invention, the side wall spacers are formed on the side surfaces of the source and drain extraction electrodes, and the gate electrodes are formed by self-alignment using these as a mask, so that the opening width between the extraction electrodes can be reduced. When the lithography minimum rule is set, the opening width between the sidewall spacers is shorter than the minimum rule. Therefore, the length of the gate electrode formed as described above is shorter than the minimum rule.

In addition, since the source diffusion layer and the drain diffusion layer are formed by diffusing impurities from the polysilicon film into the substrate, it is possible to make the diffusion layers shallow, which is accompanied by a short channel of the transistor. The punch-through phenomenon is suppressed. In addition, lightly-dope LDD (Lightly-Dope)
Since a transistor having a (drain) structure is formed, generation of hot electrons due to a short channel is suppressed.
Further, since the source diffusion layer and the drain diffusion layer are connected to the extraction electrode made of the polysilicon film, a spike phenomenon seen when the metal film is directly connected is avoided.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an element structure of a semiconductor device (MOS transistor) manufactured by a method according to one embodiment of the present invention. In the figure, reference numeral 1 denotes a P-type silicon substrate. Source and drain extraction electrodes 3a and 3b formed of a polysilicon film are formed in an element region separated by a field oxide film 2 formed on a silicon substrate 1, and opposing side surfaces of the extraction electrodes 3a and 3b. Sidewall spacers 4a and 4b are formed on the side.
The extraction electrode 3a is connected to the N ⁺ source diffusion layer 6, and the extraction electrode 3b is connected to the N ⁺ drain diffusion layer 7. On opposite sides of the source diffusion layer 6 and the drain diffusion layer 7,
N ⁻ diffusion layers 8 and 9 are formed respectively. A gate oxide film 5 is provided on the silicon substrate 1 between the sidewall spacers 4a and 4b, and a gate electrode 10a made of a polysilicon film is formed thereon by self-alignment. An interlayer film 11 is formed so as to cover gate electrode 10a, and through a contact hole opened in interlayer film 11,
The source electrode 12 is connected to the extraction electrode 3a, and the drain electrode 13 is connected to the extraction electrode 3b.

Hereinafter, a method for manufacturing the MOS transistor shown in FIG. 1 will be described with reference to FIGS.

Referring to FIG. 2A. First, a LOCOS (Local Oxidation of Silico) is placed on a P-type silicon substrate 1.
A field oxide film 2 is formed by the n) method to separate element regions.

Referring to FIG. 2B. CVD (Chemic
After depositing the polysilicon film 3 by an Al Vapor Deposition method, arsenic (As ⁺ ) is ion-implanted into the polysilicon film 3 at a relatively high concentration to impart conductivity.

Referring to FIG. 2C. The polysilicon film 3 is patterned by a photo-etching method to form source and drain extraction electrodes 3a and 3b. The width W of the opening between the extraction electrodes 3a and 3b is set to a minimum rule obtained by photolithography.

Referring to FIG. PSG (Phospho Silica) containing phosphorus (P) at a relatively lower concentration than the CVD method
An interlayer film 4 made of te glass) is deposited.

Referring to FIG. By etching back the interlayer film 4 by the plasma etching method, the side wall spacers 4a and 4b are formed on the side surfaces facing the extraction electrodes 3a and 3b. After that, 900 ~ 100
By performing a heat treatment at 0 ° C., a gate oxide film 5 is formed. During this heat treatment, a relatively high concentration of impurity (arsenic) in the extraction electrodes 3a and 3b diffuses into the silicon substrate 1 to form a source diffusion layer 6 and a drain diffusion layer 7 which are N ⁺ regions. . Also, the side wall spacer 4
Relatively low-concentration impurities (phosphorus) in a and 4b diffuse into silicon substrate 1, and N ^- diffusion layers 8 and 9 are formed inside source diffusion layer 6 and drain diffusion layer 7, respectively.

Referring to FIG. Next, a polysilicon film 10 is deposited by the CVD method, and arsenic (As ⁺ ) is ion-implanted into the polysilicon film 10 to impart conductivity. Note that a metal film may be applied instead of the polysilicon film 10.

Referring to FIG. The polysilicon film 10 is patterned by a photo etching method,
The gate electrode 10a is formed.

Referring to FIG. After depositing an interlayer film 11 such as PSG or BPSG (PSG to which boron is added) by the CVD method, contact holes are formed in the source and drain electrode regions. Then, after depositing a metal film such as aluminum, this is patterned to form a source electrode 12 and a drain electrode 13.

As described above, the width W of the opening between the extraction electrodes 3a and 3b is a minimum rule obtained by photolithography. Therefore, when the side wall spacers 4a, 4b are formed on the opposing side surfaces of the extraction electrodes 3a, 3b, the width of the opening therebetween is shorter than the minimum rule. Since the gate electrodes 10a are formed in a self-aligned manner using the extraction electrodes 3a and 3b and the side wall spacers 4a and 4b as a mask, the gate length can be made shorter than the minimum rule of photolithography.

Further, the source diffusion layer 6 and the drain diffusion layer 7 are connected to the extraction electrode 3 made of a polysilicon film.
Since the diffusion layer is formed by diffusing impurities (arsenic) from a and 3b, the diffusion layer becomes shallow. This makes it difficult for the depletion layer to extend from the drain side to the source side, so that a punch-through phenomenon associated with a short channel can be suppressed.

The side wall spacers 4a, 4b
By diffusing a relatively low concentration of impurity (phosphorus) into the silicon substrate 1 from the substrate, a so-called LDD structure in which the N ⁻ diffusion layers 8 and 9 are present on the side opposite to the source diffusion layer 6 and the drain diffusion layer Since it is formed, the generation of hot electrons due to the short channel is suppressed, and the operation of the MOS transistor is stabilized.

Further, the source diffusion layer 6 and the drain diffusion layer 7 have the extraction electrodes 3a,
Since 3b is connected, a spike phenomenon seen when a metal film is connected can be prevented.

In the above embodiment, an N-channel MOS transistor has been described as an example. However, the present invention can be applied to a P-channel MOS transistor. In this case, as shown in FIG.
⁺ Instead of, B ⁺ or BF ₂ ⁺ was implanted into the polysilicon film 3, also, in step shown in FIG. 2 (d), instead of PSG, BSG (Boro-Silicate Glass )
Should be deposited.

[0023]

As is apparent from the above description, according to the present invention, side wall spacers are formed on the side surfaces of the source and drain extraction electrodes, and the gate electrodes are formed by self-alignment using these as a mask. Because
The gate length can be made shorter than the minimum width (minimum rule) between the extraction electrodes regulated by the resolution of lithography.

Further, since the source diffusion layer and the drain diffusion layer are formed by diffusing impurities from the polysilicon film into the substrate, the diffusion layers become shallower, and a punch-through phenomenon accompanying a short channel of the transistor is suppressed. You.

Further, since a transistor having an LDD structure is formed by diffusion of low-concentration impurities from the sidewall spacer, generation of hot electrons due to a short channel is suppressed, and the operation of the transistor can be stabilized. .

Further, since a lead electrode made of a polysilicon film is connected to the source diffusion layer and the drain diffusion layer, a spike phenomenon seen when a metal electrode is directly connected can be avoided.

[Brief description of the drawings]

FIG. 1 shows M obtained by a manufacturing method according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a configuration of an OS transistor.

FIG. 2 is a cross-sectional view illustrating a procedure of a method for manufacturing a MOS transistor according to an example.

FIG. 3 is a cross-sectional view showing a procedure of a method for manufacturing a MOS transistor according to an example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Field oxide film 3 ... Polysilicon film 3a, 3b ... Extraction electrode 4 ... Interlayer film 4a, 4b ... Sidewall spacer 5 ... Gate oxide film 6 ... Source diffusion layer 7 ... Drain diffusion layer 8, 9 ... N ^- diffusion layer 10 ... polysilicon film 10a ... gate electrode 11 ... interlayer film 12 ... source electrode 13 ... drain electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-3940 (JP, A) JP-A-63-122273 (JP, A) JP-A-1-309377 (JP, A) JP-A-5-305 206454 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/225 H01L 21/265 H01L 21/336

Claims (1)

(57) [Claims] 1. A step of depositing a polysilicon film containing a high-concentration impurity of a second conductivity type on a semiconductor substrate of a first conductivity type, and extracting source and drain electrodes by patterning the polysilicon film. Forming a side wall spacer containing a second conductive type low-concentration impurity on a side surface portion of the extraction electrode opposite to the substrate, and heat treating the substrate on which the extraction electrode and the side wall spacer are formed. Thereby, a gate oxide film is formed between the opposed side wall spacers, and a source diffusion layer and a drain diffusion layer, which are high-concentration impurity diffusion layers of the second conductivity type, are formed in the substrate below each of the extraction electrodes. A step of simultaneously forming a second-conductivity-type low-concentration impurity diffusion layer in the substrate below the sidewall spacer, respectively; The method of manufacturing a semiconductor device which is characterized as a mask electrode and the sidewall spacers, a step of a gate electrode is formed by self-alignment, further comprising a.