JP3127873B2 - Waveform reproducing method, waveform reproducing device, waveform output circuit, and sequence reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform reproducing method for reproducing an audio signal from waveform sample data, a waveform reproducing device, a waveform output circuit, and a sequence reproducing device.

[0002]

2. Description of the Related Art In a personal computer or the like, an analog / digital converter (A / D converter, AD
C), digital / analog converter (D / A converter, DA)
C) and an encoding / decoding circuit (CODEC)
By providing CODEC driver software for driving the ODEC, waveform sample data (WA
VE data) can be recorded or reproduced in monaural or stereo. Also, there is known waveform editing software in which a plurality of WAVE data are respectively arranged at arbitrary positions on a time axis and reproduced. In this case, dedicated hardware capable of simultaneously reproducing a plurality of WAVE data is provided.

[0003]

In the above-described conventional method of reproducing waveform sample data, since the CPU generates a trigger for reproducing the waveform, the WAV is used.
The timing of starting the reproduction of the E data could not be controlled with high accuracy. Also, the timing of the end of reproduction cannot be determined with high accuracy. In the multitasking processing, the CPU has not only transmission of waveform samples and reproduction control of WAVE data, but also other processing to be executed simultaneously. Therefore, even when it is time to execute the transmission of a waveform sample or the like, the processing cannot always be executed immediately. in this way,
It was impossible to make the CPU perform precise time control of WAVE reproduction. In particular, when a plurality of WAVE data are reproduced at the same time and the precision of the reproduction timing control is low, the reproduction timing of each WAVE data fluctuates, and the state of interference between waveforms changes.
There was a problem that it would sound different each time it was played.

Accordingly, an object of the present invention is to provide a waveform reproducing method, a waveform reproducing apparatus, a waveform output circuit, and a sequence reproducing apparatus capable of controlling the timing of starting and ending the reproduction of waveform data with high accuracy. . It is another object of the present invention to provide a waveform reproducing method, a waveform reproducing apparatus, a waveform output circuit, and a sequence reproducing apparatus capable of reproducing a high-quality waveform even when simultaneously outputting waveform sample data of a plurality of channels. And

[0005]

According to the present invention, there is provided a waveform reproducing method for reproducing waveform data in response to an instruction from a central processing unit.
B. a step of sequentially transferring the waveform data stored in the memory to the buffer memory via the bus one by one from the head in accordance with an instruction from the central processing unit; Generating a timing signal when detecting a coincidence between a count value of a counter for counting a timing pulse and timing data set by the central processing unit; and
C. A step of sequentially reproducing the waveform data stored in the buffer memory from the beginning in accordance with the timing signal generated in step B. According to such a waveform reproduction method of the present invention, reproduction of waveform data can be started at an accurate timing in accordance with an instruction from the central processing unit.

Also, a waveform reproducing apparatus of the present invention has a central processing unit for controlling the entire apparatus, a first bus connected to the central processing unit, and a plurality of waveform data connected to the first bus. , A second bus provided independently of the first bus, and a storage area for a plurality of channels connected to the second bus and capable of storing a part of waveform data, respectively. A buffer memory having, and according to an instruction of the central processing unit, supply means for sequentially supplying the waveform data to be reproduced in each channel from the head to the storage area corresponding to each channel of the buffer memory from the head, A register in which timing data of each channel is set by the central processing unit, a counter for counting timing pulses, and a count value of the counter and setting in the register Timing generating means for generating a timing signal for each channel based on the timing data stored in the memory; and reading and reproducing waveform data from a storage area of the buffer memory corresponding to the channel in response to the timing signal. Playback means. According to this waveform reproducing apparatus, it is possible to simultaneously reproduce a plurality of waveform data stored in the memory at an accurate timing based on the count value of the counter in response to an instruction to the central processing unit which controls the entire apparatus. Becomes

Further, the waveform output circuit according to the present invention is a waveform output circuit for reading out and reproducing waveform data from a memory for storing a plurality of waveform data connected to a bus. A buffer memory having a plurality of storage areas capable of storing a part of data, and storing the waveform data to be reproduced on each channel from the memory via the bus sequentially from the top, corresponding to each channel of the buffer memory Supply means for supplying the area, a register for storing timing data,
A counter for counting a timing pulse; timing generating means for generating a timing signal for each channel based on the count value of the counter and the timing data set in the register; and a buffer memory in accordance with the timing signal And reading and reproducing means for reading and reproducing the waveform data from the storage area corresponding to the channel. According to this waveform output circuit,
The reproduction of the waveform data on the memory connected to the bus can be started at an accurate timing regardless of the use condition of the bus.

Further, the sequence reproducing apparatus of the present invention is a sequence reproducing apparatus for waveform data using n (n is an integer of 2 or more) channels, wherein a memory for storing a plurality of waveform data, A sequence memory that sequentially stores a plurality of event data indicating reproduction timings of a plurality of waveform data, a buffer memory having n storage areas corresponding to n channels, and an event data stored in the sequence memory, Channel allocating means for sequentially allocating to an open channel out of n channels from a plurality of waveform data; Supply means for sequentially supplying the storage area of the corresponding channel A counter for counting the timing pulse, a detecting means for detecting the reproduction timing of the event data assigned to each channel based on the count value of the counter, and a storage area for the detected channel in response to the detection of the reproduction timing. And read-out means for sequentially reading and reproducing the waveform data stored in the memory, and channel opening means for detecting a channel for which reading by the read-out means has been completed and opening the channel. According to this sequence reproduction device,
It is possible to sequentially reproduce waveform data of a plurality of n channels in sequence at accurate timing.

[0009]

FIG. 1 is a block diagram showing an overall configuration of a waveform recording / reproducing apparatus which is an embodiment of a waveform reproducing apparatus to which a waveform reproducing method of the present invention is applied. In this figure, reference numeral 10 denotes a central processing unit (CPU) for controlling the entire waveform reproducing apparatus; 11, a ROM for storing various programs and constant data; 12, programs and data to be executed are read; A first random access memory (RAM) used as a buffer area or a work area; 13 a display device for displaying various information; 14 an interface circuit for connecting the display device 13 to a local bus 18; A keyboard for inputting various instructions from a user, etc., 16 is an interface circuit for connecting the keyboard 15 to a local bus 18, and 17 is a CPU for measuring time and
This is a timer that interrupts the timer 10. The CPU 10, the ROM 11, the first RAM 12, the interface circuits 14, 15 and the timer 17 are connected to a local bus 18.

Here, on the first RAM 12, a buffer area (PC buffer) for storing waveform sample data of a plurality of channels is secured. This PC buffer can be set in an arbitrary size at an arbitrary position on the memory address space of the CPU. In the waveform sample data, one word is 32 bits or 1 word.
Any type of data such as 6 bits may be used,
Here, it is assumed that one word is 16-bit waveform sample data.

Reference numeral 20 denotes a PCI (Peripheral Component Int)
erconnect) bus 19 is the local bus 18
HOST-PCI for connecting the PC and the PCI bus 20
It is a bridge circuit. Although the PCI bus can be extended to 64 bits, it is assumed here that the PCI bus has a data bus width of 32 bits. The PCI bus 20 has one 32
A bit data bus is used for address and data in a time sharing manner. For example, at the time of data transfer, first, an address is transmitted to the data bus to specify a transfer destination, and then data transfer is performed using the bus.

Reference numeral 21 denotes a second random access memory (R
AM), 22 stores the second RAM 21 in the PCI bus 2
This is an interface circuit for connecting to 0. A hard disk drive 23 stores various waveform sample data and programs, and a CD-ROM 24 stores various waveform sample data and programs.
A SCSI (small computer system interface) 25 for connecting an external storage device such as a hard disk device 23 or a CD-ROM device 24.
ce) An interface circuit. Further, a network interface circuit 27 is a circuit for connecting to an external network 26 via a telephone line, a dedicated line, or the like. Although not shown in FIG.
A MIDI interface or the like for inputting and outputting DI signals may be provided.

Reference numeral 30 denotes a waveform sampled data stored in the PC buffer in the first RAM 12, and the read waveform sample data is subjected to a processing such as adding an effect as necessary, thereby producing a sound. The first RAM 12 converts the audio signal output from the audio input terminal via the microphone 28 or the like into waveform sample data.
Reference numeral 28 denotes a waveform input / output circuit (sound input / output board) stored in a PC buffer therein, 28 denotes a microphone connected to a sound input terminal provided on the sound input / output board 30, and 29 denotes a sound input / output board This is a sound system that amplifies an output audio signal and emits the sound. The sound input / output board 30
Will be described later.

1, the HOST-PCI bridge circuit 19, interface circuit 22, network interface circuit 27, SCSI interface circuit 25, and sound input / output board 30 are connected to the PCI bus 20. Here, the H
OST-PCI bridge circuit 19, network interface circuit 27, SCSI interface circuit 2
5 and the sound input / output board 30
Can be a master, for example, the HOST-PC
By issuing a bus use request to the bus arbiter provided in the I-bridge circuit 19 and acquiring the right to use the bus, the data transfer can be executed using the PCI bus 20.

The bus configuration is not limited to the example shown in FIG. For example, the local bus in FIG. 1 can have various bus configurations such as a configuration including two buses, a CPU bus and a local PCI bus for connecting peripheral I / O and the like. In FIG. 1, the hard disk drive 23 and the CD-R
Although the OM device 24 is connected to the PCI bus 20, a SCSI interface circuit is connected to the local bus 18, and a hard disk device or a CD-ROM is connected to the SCSI interface circuit.
An external storage device such as a ROM device or a DVD device may be connected.

Next, the internal configuration of the sound input / output board 30 will be described. FIG. 2 is a block diagram showing a configuration example of the sound input / output board 30. In this figure, reference numeral 31 denotes a first bus connected to the PCI bus 20.
Is a third random access memory (RAM3) used as a buffer memory. The third RAM 32 has a reproduction buffer (P buffer: Play buffer).
Buffer and recording buffer (R buffer: Record Buffe)
r) are provided, and each channel has a capacity of, for example, 1K words (= 1024 words). In this example, there are a total of 20 channels of 16 channels for reproduction and 4 channels for recording, and each channel can store 1K words of waveform sample data. Also, 3
Reference numeral 3 denotes a second transfer circuit for executing data transfer between the P and R buffers and the mixer 34. As will be described later, the access to the RAM 32 is time-division multiplexed in units of one-half the sampling period (DAC cycle), and the first half of each DAC cycle is the second half.
And the first transfer circuit 31 uses the latter half for access.

Reference numeral 34 denotes a mixer, 35 denotes a signal processor (DSP), and 36 denotes an A / D.
A converter 37 is a D / A converter. The mixer 34 has, for example, an input of 36 channels and an output of 24 channels.
The waveform sample data converted into digital data by the / D converter 36, the waveform sample data from the P buffer transferred by the second transfer circuit 33, and the waveform sample data processed by the DSP 35 are input. A mixing operation is performed based on the control data supplied from the CPU 10, and output to the R buffer, the DSP 35 or the D / A converter 37 via the second transfer circuit 33.

The DSP 35 performs various processes such as adding a predetermined effect and interpolation to the 16-channel waveform samples input from the mixer 34, and outputs the 16-channel waveform samples resulting from the processing to the mixer 34. I do. Note that the DSP 35 is a multi (program) DSP that can execute a plurality of types of signal processing, for example, interpolation calculation, various types of effect processing, and the like during one DAC cycle period. The A / D converter 36 converts an audio signal (voice signal or musical tone signal) input from the microphone 28 into a predetermined sampling rate (D
It is sampled at an AC cycle, for example, 44.1 KHz, converted into waveform sample data of a predetermined number of bits (here, 16 bits), and output to the mixer. Here, the configuration is such that waveform samples of four channels can be input and output. The D / A converter 37 converts the 4-channel waveform sample data output from the mixer 34 into an analog signal and outputs the analog signal to the sound system 29.

In the mixer 34, a 16-channel multi-DSP from the second transfer circuit is provided every sampling period.
Waveform data of a total of 36 channels of 35 to 16 channels and 4 channels from the A / D converter 36 are input, and 20 types of data are set based on level data independently set for each input / output included in the control data. A mixing process is performed, and the mixing result is output as waveform data of a total of 20 channels, that is, 4 channels to the second transfer circuit, 16 channels to the multi-DSP 35, and 4 channels to the D / A converter 37.

Here, the second transfer circuit 33, the multi-DS
How to connect the P35, the A / D converter 36, and the D / A converter 37 can be set by the level data. For example, when it is desired to record the waveform data input from the external microphone 28 in the PC buffer, the volume of the waveform data input from the A / D converter 36 is controlled by the mixer 34 for each DAC cycle, and the multi-DSP 35
The waveform data subjected to equalizer processing and compressor processing by the multi-DSP 35 is input again to the mixer 34 to control the volume, and then stored in a transmission register (not shown) for the transfer circuit 2 in the mixer 34. The connection for recording can be set independently for each of the four channels for recording.

When it is desired to reproduce the waveform data in the PC buffer, the volume of waveform data output from the transfer circuit 2 to the input register (not shown) in the mixer 34 is controlled by the mixer 34 for each DAC cycle. Multi DSP3
5, and the waveform subjected to the chorus effect and reverberation effect processing by the multi-DSP 35 is input again to the mixer 34, and the volume is controlled and then output to the D / A converter 37.
Connections during reproduction can be set independently for each of the 16 channels for reproduction. As still another example, waveform data input from an A / D converter is converted to multi-DS data.
Send to P35 to apply effects to D / A converter 37
It is also possible to set so that the waveform data of the PC buffer reproduced on the reproduction channel is subjected to processing such as equalizer processing by the multi-DSP, and then stored in the PC buffer of another area on the recording channel. .

The mixer 34, the DSP 35, and the D / A converter 3, which perform processing at the sampling period as described above,
7 is called a digital audio circuit. The waveform data input to these digital audio circuits is finally converted into an analog waveform, and further converted into sound by a speaker or the like.

Numeral 38 denotes a counter having a 32-bit configuration, for example, 44.1 KH equal to the DAC cycle.
It is configured to count pulses of z. Therefore, this counter 38 outputs time data counted in units of DAC cycles. 39 is the counter 38
Time data output from the memory and a register 40 described later.
Is a timing generator for controlling the operation of the first transfer circuit 31 or the second transfer circuit 33 based on the result of comparison with various designated time data stored in the first transfer circuit 31 or the second transfer circuit 33. Reference numeral 40 denotes a register, and the first transfer circuit 31, the second transfer circuit 33, the counter 38, the timing generator 39, and the DSP 3 in the sound input / output board 30.
5. Various control data or variables necessary for various controls on the A / D converter 36 and the D / A converter 37 are set by the CPU 10. The details of each data set in the register 40 will be described later.

In the waveform recording / reproducing apparatus configured as described above, when reproducing the waveform, the first RAM 12
The waveform sample data of each channel stored in the upper PC buffer is transferred to the third RAM in the sound input / output board 30 under the control of the first transfer circuit 31.
The data is sequentially transferred to the 32 P buffers in units of 32 samples, and the third RAM 3 is transferred under the control of the second transfer circuit 33.
2 to 1 per DAC cycle for each sounding channel
The mixer 34 (and the multi-D
SP35) to the D / A converter 37,
The audio signal is output from the sound system 29. When recording a waveform, the microphone 2
8 and converted into waveform sample data in the A / D converter 36 (via the multi-DSP 35).
The audio signal output from the mixer 34 is transferred to the third RAM 32 under the control of the second transfer circuit 33.
Under the control of the first transfer circuit 31, the waveform sample data stored in the R buffer in the third RAM is stored in the P buffer in the first RAM 12.
The data is transferred to the C buffer in units of 32 samples.

This will be described with reference to FIG. FIG.
Is a PC buffer provided in the first RAM 12,
FIG. 8 is a diagram for explaining how waveform sample data is transferred between a P buffer or an R buffer provided in the third RAM 32 and the mixer 34;
(A) is a diagram showing a data flow at the time of reproduction, and (b) is a diagram showing a data flow at the time of recording. As described above, in this embodiment, reproduction is performed on 16 channels and recording is performed on 4 channels.
Up to 15 are playback channels, channel numbers 16 to 1
Up to 9 are recording channels. The P buffer and the R buffer are provided independently of each other corresponding to each reproduction channel and each recording channel, and are used cyclically as ring buffers for storing waveform data.

FIG. 3A shows the channel numbers 0 to 0.
15 shows the flow of reproduced data, and here only one channel x is shown. As shown, the PC buffer area corresponding to the x-th channel (x = 0, 1,..., 15) provided in the first RAM 12 has a start address SA [x] and an end address EA [x].
TP [x] is a transfer pointer indicating the read position of the PC buffer area.

The sound input / output board 30 has 1 DA
The C cycle is divided into two, and it is determined whether it is necessary to read the waveform sample data from the PC buffer during the first half of one DAC cycle. If the reading of the waveform sample data is necessary, a use request of the PCI bus 20 is output to the bus arbiter during the latter half of the DAC cycle, and the right to use the bus is acquired.
2 is accessed, 32 consecutive words of data are read from the address specified by the transfer pointer TP [x], and the data is burst-transferred to the P buffer. At this time, the transfer pointer TP [x] is increased by 16 addresses (32 words) for each bus transaction. Also,
The PC buffer will be accessed at a 32-bit address boundary. Here, the burst transfer is a transfer method in which an address is first output to the data bus only once, and then a plurality of data are successively transferred. In the burst transfer, since it is not necessary to specify an address for each data, it is possible to collectively transfer data for a plurality of consecutive addresses from the position of the specified address on the memory. For example, the operating clock of the PCI bus is set to 33 MHz.
In the case of performing burst transfer of 32 samples in one DAC cycle, about 0.1% of the transfer capacity of the bus is used. On the other hand, when 32 samples are transferred without performing burst transfer, the transfer time is about four times less than that.

An interrupt request address IA is provided between the start address SA [x] and the end address EA [x].
[X] can be set, and when the transfer pointer TP [x] reaches the interrupt request address IA [x], an interrupt request is issued to the CPU 10. ing. Therefore, by setting this interrupt request address IA [x] = end address EA [x], the CPU can detect the completion of the transfer of the data of the PC buffer by the interrupt, and at that time, the PC The buffer can be released so that it can be used for reproducing other waveform data on the RAM 12, or the transfer pointer T
By setting P [x] = SA [x], the waveform data stored in the PC buffer can be repeatedly reproduced.

If the following method is used, a small-capacity PC buffer (for example, 4
K to 64K words), large-capacity waveform data (for example, several hundred K to several tens M words) stored in the external storage device such as the hard disk device 23 or the CD-ROM device 24 is sequentially transferred. Direct playback can be performed while reading.

First, when one of the waveform data stored in the external storage device is instructed to be reproduced, the CPU transfers the waveform data at the beginning to the PC buffer [x]. The IA [x] is replaced with the SA [x] and the EA
The reproduction of the same PC buffer is started by setting an intermediate value of [x]. When TP [x] eventually reaches IA [x] and an interrupt occurs, the CPU sets IA [x] = EA [x], reads the subsequent waveform data from the external storage device, and reads the same PC buffer. From the start address SA [x] of [x], half of the capacity is stored. Further, when TP [x] reaches IA [x] and an interrupt occurs, the CPU sets TP [x] = SA [x] and IA [x].
The intermediate value is set in [x], and the subsequent waveform data is read from the external storage device and stored in the latter half of the PC buffer [x]. Thereafter, the above-described interrupt processing at IA [x] set to the intermediate value and the interrupt processing at IA [x] set to EA [x] are alternately repeated, and the external storage device The reproduction of the specified waveform data is performed to the end. Note that the CPU
The transfer of half the amount of the waveform data of the PC buffer [x] described above may be performed by the direct memory access controller DMAC built in the CPU, or burst transfer may be used at that time.

The 32-word waveform sample data read from the transfer pointer TP [x] of the PC buffer on the first RAM 12 and burst-transferred is transferred to the x-channel P buffer on the third RAM 32. Are written in order from the address indicated by the transfer write pointer TWP [x]. As described above, this P buffer has a size of, for example, 1K words for each channel. For each burst transfer, TWP [x] advances by 32 addresses. The reading of the data from the P buffer is executed by the second transfer circuit 33 in the first half of the DAC cycle. The second transfer circuit 33 reads out one sample of the waveform sample data every DAC cycle from the address indicated by the audio reproduction pointer APP [x] of the P buffer, and transfers it to the mixer. As will be described later, the timing of starting / ending the reading is controlled by the timing generator 39.

On the other hand, FIG. 3B shows the flow of data in the recording channel. Audio data input from the microphone 28 and converted to digital data by the A / D converter 36 is subjected to predetermined signal processing by the DSP 35 as necessary, and then output from the mixer 34. The second transfer circuit 33 converts the waveform sample data output from the mixer 34 every DAC cycle into an x channel (x
= 16,..., 19) at the address specified by the audio recording pointer ARP [x] in the R buffer. The audio recording pointer is sequentially incremented every DAC cycle. The size of the R buffer is also 1K words for each channel, similarly to the P buffer.

When a predetermined amount of waveform sample data is written to the R buffer, in the latter half of the DAC cycle,
The first transfer circuit 31 serves as a bus master, and writes the waveform sample data to the PC buffer in the first RAM by burst transfer of 32 words. At this time, the transfer read pointer TRP of the R buffer
32 words of waveform sample data starting from [x] are sequentially read out, and P
Writing is performed sequentially from the transfer pointer TP [x] of the C buffer. The transfer pointer TP [x] has 16 addresses (32 words) for each bus transaction.
Is incremented by one.

In the case of this recording as well, by setting the interrupt request address IA [x] in the same manner as described above, the PC buffers for which recording has been completed are sequentially released, or the PC buffers are reduced. By using it as a double buffer having a large capacity, it is possible to directly record a large amount of input waveform data on a hard disk device or the like.

As described above, in this embodiment,
A sound input / output board 30 serving as a waveform reproducing circuit is connected to a PCI bus 20 having a burst transfer function,
When the first transfer circuit 31 needs to read the waveform sample from the PC buffer, the PCI bus 2
The waveform sample is burst-transferred to the buffer memory of the channel provided on the sound input / output board 30, for example, 32 samples at a time. Therefore, it is possible to prevent a decrease in the operation efficiency of the entire system due to the transfer of the waveform data, and to stably reproduce the waveform data of a plurality of channels simultaneously.

Next, the operation of the thus configured waveform recording / reproducing apparatus will be described with reference to flowcharts. FIG. 4 is a flowchart showing the operation of the main routine executed by the CPU 10. First,
In step S11, the CPU 10 executes initialization processing such as securing each area and initializing variables and flags. Next, it waits for the occurrence of some activation factor (steps S12 and S13). When an activation factor occurs, the process proceeds to step S14, and it is determined what the activation factor is.

When the activation factor is a switch operation such as a mouse click on a switch or a predetermined area on the GUI screen, the process proceeds to step S15, and a process corresponding to the operated switch is performed. Here, when a switch corresponding to waveform reproduction is operated, a waveform reproduction process described later is performed. When the activation factor is an interrupt, the process proceeds to step S16, and processing corresponding to the interrupt is performed. This interrupt processing will be described later. Further, when the activation factor is another process that is neither a switch operation, an interruption, nor an end instruction, the process proceeds to step S17, and a process corresponding to the activation factor is performed. Furthermore, when the activation factor is an end instruction, the process proceeds to step S18, where an end process such as opening a memory area is executed.

Next, the waveform recording / reproducing processing executed in the present invention will be described. Before that, the flags and variables stored in the register 40 shown in FIG. 2 will be described. RF is a run flag (Ru
n Flag), the counter 38 starts counting when the run flag RF is set to “1”, and stops counting when RF = 0. Also, as described above, SA [x] (Start Addr
ess) is the start address of the x-th channel PC buffer, and EA [x] (End Address) is the P-th address of the x-th channel.
Last address of C buffer, IA [x] (IRQ Addres
s) is an interrupt request address of the x-th channel PC buffer, and TP [x] (Transfer Pointer) is a transfer pointer indicating the read position of the x-th channel PC buffer. SUS [x] (Suspend Flag) is a suspend flag indicating that the transfer of the channel by the first transfer circuit 31 is temporarily suspended.

Also, PSC [x] (Playback Start Cou
nt) is a reproduction start count value indicating a reproduction start time in units of a DAC cycle of the x-th channel, and PEC [x].
(Playback End Count) is a reproduction end count value indicating a reproduction stop time in units of DAC cycles of the x-th channel, and TWP [x] (Transfer Write Pointer) is a transfer write indicating a writing position of a P-buffer of the x-th channel. Pointer, TWF [x] (Transfer Write Flag) is x-th
A transfer instruction flag for instructing start / end of transfer from the PC buffer of the channel to the P buffer, APP [x] (Au
dio Playback Pointer) is a playback pointer indicating the read position of the P-buffer of the x-th channel, APF [x] (Au
dio Playback Flag) is a playback instruction flag for instructing start / end of waveform playback of the x-th channel.

Further, RSC [x] (Recording Start
Count) is a recording start count value specifying a recording start time in units of DAC cycles of the x-th channel, REC
[X] (Recording End Count) is the D of channel x
A recording end count value specifying a recording stop time in units of AC cycles, TRP [x] (Transfer Read Pointe
r) is a transfer read pointer indicating the read position of the R buffer of the x-th channel, TRF [x] (Transfer Rea
d Flag) is a transfer instruction flag for instructing start / end of transfer from the R buffer of the x-th channel to the PC buffer;
RP [x] (Audio Rec Pointer) is a recording pointer of the R buffer of the x-th channel, ARF [x] (Audio Rec Pointer)
Flag) is a recording instruction flag for instructing start / end of recording of the x-th channel. Furthermore, RPC (Recordin
g Pre Count) is a recording pre-count value indicating the number of samples before starting recording in the case of pre-trigger recording, that is, ARP when TRF [x] = 1.
This is data specifying how many samples before the transfer is started from the value of [x]. At the timing when TRF [x] = 1 is set, TRP [x] = ARP [x] -RPC is set to the transfer start address. The first transfer circuit starts transfer to the PC buffer.

When recording is desired, the operator first performs a recording preparation operation, and then performs a recording start operation. C
The PU 10 sets the recording instruction flag ARF [x] to 1 in response to the recording preparation operation, and sets TRF [x] to 1 in response to the subsequent recording start instruction. ARF
According to the setting of [x], first, the writing of the waveform data output from the mixer 34 into the R buffer by the second transfer circuit 33 starts, and then, according to the setting of the TRF [x], The transfer of the waveform data of the R buffer to the PC buffer by one transfer circuit starts. The input waveform data is written to the R buffer by the TRF
Since it is performed prior to the timing of setting [x] to 1, the waveform data is transferred to the PC buffer from the sample indicated by the RPC before the sample at the time of the recording start instruction by the transfer start address. be able to.

As described above, according to the present embodiment, the transfer of the waveform data from the recording buffer to the PC buffer can be started at an arbitrary timing. In addition, the input waveform is only written into the R buffer until a recording start instruction is issued, so that no load is applied to the PCI bus 20 in a state of waiting for the instruction. Note that, instead of the operator instructing the start of recording, C
The PU 10 may generate a recording start instruction.

The waveform reproducing process in this waveform recording / reproducing apparatus includes (1) when reproducing the waveform sample data stored in the first RAM 12, (2) sequence reproducing, that is, for each channel. There are various cases such as a case where a waveform is reproduced based on sequence data describing a time for reproducing the waveform sample data and the like, and a case where (3) the waveform stored in the hard disk is directly reproduced as described above.

First, the first RAM 12 of the above (1) is used.
A case where the waveform sample data (WAVE data) stored above is reproduced will be described. FIG. 5 (a)
FIG. 5 is a flowchart for explaining an operation executed by the CPU 10 when the (1) WAVE data reproduction instruction is issued. This process is included in the switch process of step S15 in FIG.

When the operator issues a waveform playback instruction by operating a switch for instructing waveform playback or clicking a button on a GUI screen with a mouse or the like, FIG.
Is started. First, in step S21,
WAV indicating the waveform data to be reproduced stored on the first RAM 12 included in the reproduction instruction
Receive E instruction data.

Next, the process proceeds to step S22, in which the WA that has been instructed to reproduce at the same time in step S21.
The sounding channels are assigned according to the VE data. Here, among the sounding channels, channels that are not currently sounding, that is, channels 0 to 1
Of the five channels, the transfer instruction flag TWF
The channel x to be sounded is designated from the channels for which both [x] and the reproduction instruction flag APF [x] are “0”. If there is no channel for which both TWF [x] and APF [x] are “0”, the channel with the shortest sound and the channel with the lowest volume out of the 16 channels for reproduction are muted. Then, the channel is designated as the sound channel x.

Subsequently, the flow advances to step S23 to execute the WA
The start address and the end address of the PC buffer corresponding to the WAVE data included in the VE instruction data are set to the start address SA of the specified sound channel x.
[X] and the final address EA [x] are set in the register 40. Next, the process proceeds to step S24, where the transfer instruction flag TWF [x] corresponding to the tone generation channel x in the register 40 is set to "1". At this time, the transfer write pointer TWP of the channel x
[X] and the playback pointer APP [x] are initialized. By setting TWF [x] to "1", the transfer (preload) of designated WAVE data to the P buffer by the first transfer circuit 31 is started, as described later. Become.

Subsequently, the process proceeds to step S25, where the reproduction start count value PSC [x] indicating the reproduction start time in units of the DAC cycle corresponding to the tone generation channel and the reproduction end indicating the reproduction stop time in units of the DAC cycle. The count value PEC [x] is set in the register 40. For example, when the reproduction is to be started immediately, the current time data in DAC cycle is calculated based on the current time data in the timer 17, and the value is set as the reproduction start count value PSC [x]. . When the waveform reproduction instruction includes reproduction end time information, a value corresponding to the reproduction end time information is set as the reproduction end count value PEC [x].
In the case where VE data is reproduced as a whole, a value obtained by adding the number of waveform samples to the reproduction start count value PSC [x] is set. Here, it is assumed that the run flag is set to RF = 1 and the counter 38 is operating.

The above is the processing executed by the CPU 10 when a waveform reproduction instruction is issued. In this process, as described above, SA [x], EA [x], PS corresponding to the assigned sounding channel, respectively.
C [x] and PEC [x] are set, and T instructs the start of transfer from the PC buffer to the P buffer.
WF [x] will be set to “1”. The actual reproduction processing is executed by the processing by the first transfer circuit 31 and the second transfer circuit 33 described below.

FIG. 5B shows the first transfer circuit 31.
6 is a flowchart of a transfer preparation process executed in step S1. This transfer preparation process is executed once in the first half of dividing one DAC cycle into two. First, in step S31, the transfer instruction flag TWF
It is determined whether or not [x] or the transfer instruction flag TRF [x] is set to “1”. Here, the flag TWF is set for all channels.
When [x] and TRF [x] are not set, the transfer has not been instructed, so the transfer preparation processing ends (when the determination result in S31 is YES). On the other hand, the flag TWF [x] or TRF [x]
Is set to “1”, that is, when there is a channel for which transfer is instructed,
Proceed to step S32.

In step S32, the suspend flag SUS [x] is set to "1" for the channel for which TWF [x] or TRF [x] is set to "1".
And the data to be transferred is 128
Search for channels with more than words. Here, the suspend flag SUS [x] is a flag for temporarily suspending the transfer of the WAVE data of the channel in order to prevent catch-up. Is stored in the R buffer when the free space becomes smaller than the data amount (32 words in this embodiment) transferred by one burst transfer, or when the channel is a recording channel. Set when waveform samples are less than 32 words. That is, when the SUS [x] flag is set to "1", the transfer of the channel is suspended.

If the SUS [x] flag is set to "1" and a channel having 128 words or more of data to be transferred is found, in step S34,
The SUS [x] flag of this channel is reset to “0”. Here, the "data to be transferred" indicates the free space of the P buffer when the channel is a sounding channel, and indicates the amount of waveform samples stored in the R buffer when the channel is a recording channel. As described above, in steps S32 to S34, the SUS [x] flag is set to "0" for the channel whose data to be transferred is 128 words or more among the channels whose SUS [x] flag is set to "1". To reset the interrupted state of the transfer.

Subsequently, the flow advances to step S35 to transfer the channel whose flag TWF [x] or TRF [x] is set to "1" and whose SUS [x] flag is "0". The channel having the largest data to be searched is searched, and the number x of the channel is set in the register i for specifying the number of the channel to be transferred in the current transfer processing. The above is the flowchart of the transfer preparation processing executed in the first transfer circuit 31. That is, in the transfer preparation processing executed in the first half of the DAC cycle, the channel to be transferred is determined, and the number of the channel is set in the register i.

In step S35, the channel having the largest number of data to be transferred is set as the target channel for the next transfer process. However, the channel to be transferred can be determined by other methods. For example, if the flag TWF [x] or TRF [x] is "1"
And the channels whose SUS [x] flag is “0” may be sequentially set as the transfer target channels in the register i. However, if an address counter or an interpolation circuit for each channel is added to the second transfer circuit 33 so that waveform samples having different sampling rates can be simultaneously recorded and reproduced, the data to be transferred according to the sampling rate is determined. In such a case, the method of determining the channel to execute the transfer by referring to the data to be transferred is preferable because the change speed is different.

Next, the transfer processing executed in the first transfer circuit 31 will be described with reference to the flowchart shown in FIG. This transfer process is 1 DAC
This is executed in the latter half of the cycle divided into two. In this transfer process, first, in step S41, the presence or absence of a channel to be transferred is checked. This is determined by whether or not significant data is set in the register i. If the result of this determination is that the channel number has not been set, there is no channel to transfer, and this transfer process ends.

If the channel number has been written to the register i in the transfer preparation processing, the decision result in the step S41 is NO, the process proceeds to a step S42, and the PCI bus 20 is acquired. That is, the first
Transfer circuit 31 requests the bus arbiter for the right to use the PCI bus, and acquires the right to use. After acquiring the right to use the PCI bus, the flow advances to step S43 to transfer 32 samples of WAVE data of channel i. That is, when the first transfer circuit 31 becomes a bus master and the channel i is a sounding channel, the P in the first RAM 12 corresponding to the sounding channel i
The WAVE data for 32 samples is read from the storage position indicated by the transfer pointer TP [i] of the C buffer, and stored in the burst transfer mode indicated by the pointer TWP [i] of the P buffer corresponding to the i channel of the third RAM 32. Store sequentially in position. When the channel is a recording channel, the transfer read pointer TR of the R buffer corresponding to the i channel of the third RAM 32 is read.
Read 32 samples of waveform data from P [x] and transfer pointer T of the PC buffer in burst transfer mode.
The data is sequentially stored from the storage position indicated by P [i].

In step S43, after the burst transfer, the transfer pointer TP [i] used for the transfer is advanced by 16 addresses (corresponding to 32 samples), and the transfer write pointer TWP [i] used for the transfer or the transfer read pointer TRP is used. [I] is advanced by 32 addresses. When the pointers TWP [i] to TRP [i] have advanced to the corresponding final addresses of the P buffer or the R buffer, the first transfer circuit 31 outputs the pointers TWP [i] to TRP [i]. Is returned to the start address of the corresponding P buffer or R buffer. When this transfer is completed, the process proceeds to step S44,
The PCI bus 20 is released.

Then, the process proceeds to a step S45, wherein it is determined whether or not the amount of data to be transferred of the channel (i-channel) is 32 samples or less. That is, when this i channel is a sounding channel, it is determined whether or not the free space of the P buffer is 32 samples or less.
If the channel is a recording channel, it is determined whether the number of samples stored in the R buffer is 32 or less. If the result of this determination is YES, catch-up will occur at the next transfer, so the suspend flag SUS [i] corresponding to the channel is set to "1" and the transfer on this channel is interrupted. (Step S46).

The above is the contents of one transfer process executed by the first transfer circuit 31. That is, 1 DAC
The transfer preparation process shown in FIG. 5B and the transfer process shown in FIG. 5C are executed once in each cycle, and 32 samples of one channel per DAC cycle. Is transferred. In this manner, for the sounding channels, the WAVE data of each sounding channel is sequentially stored in the P buffer on the third RAM 32 until the free space of the P buffer becomes 32 samples or less. For the recording channel, the waveform samples stored in the R buffer are sequentially transferred to the PC buffer until the remaining R buffer becomes 32 samples or less.

In the data transfer by the first transfer circuit 31 described above, only one channel number x is set in the register i in step S35 of FIG. 5B, and FIG.
The transfer of one channel set in step S43 is performed. In step S35, not only one channel is set, but also n (for example, five) registers i1 to in, including channels with the largest number of data to be transferred, are stored in up to n channels. A number may be set, and data transfer of up to n channels specified in step S43 may be transferred collectively. In this case, particularly when there is a channel whose transfer is delayed, the same channel is registered in a plurality of n registers, and data of 64 samples, 96 samples, or the like is transferred at a time for that channel. Good.

Next, the transfer processing of the WAVE data from the P buffer to the mixer 34 for the tone generation channel and the processing from the mixer 34 to the R buffer for the recording channel are executed by the second transfer circuit 33. The transfer process will be described with reference to the flowchart shown in FIG. This process is also executed once in the first half period of each DAC cycle.

First, in step S51, the second transfer circuit 33 sets an initial value "0" to a register j for storing a channel number. As described above, the 0th
Channels 15 to 15 are sounding channels, and channels 16 to 19 are recording channels. Therefore, when 0 ≦ j ≦ 15, the channel is a sounding channel, and 16 ≦ j
When ≦ 19, the channel is a recording channel. Subsequently, in step S52, it is determined whether or not a reproduction instruction flag APF [j] for instructing start / end of the waveform reproduction corresponding to the channel set in the register j is set to "1". The reproduction instruction flag APF [x] is a flag that is set to “1” at a sound generation start time corresponding to the sound generation channel and set to “0” at a sound generation end time in a timing generation process described later.

Reproduction instruction A corresponding to the sounding channel
If PF [j] is set to "1", in step S53, the P corresponding to the sound generation channel j is determined.
The reproduction pointer APP [j] of the buffer is advanced by one, the waveform sample data (WAVE data) at that address is read, and output to the input register in the mixer 34,
Proceed to step S54. On the other hand, if APF [j] corresponding to the sounding channel is “0”, the process directly proceeds to step S54. Here, when the pointer APP [j] advances to the final position of the corresponding P buffer, APR
[J] is returned to the head of the P buffer again. And
In step S54, j is incremented by one to j + 1, and the above processing is repeated until j becomes 16 or more (step S5).
5).

Next, the processing up to the fifteenth channel is completed, and if the decision result in the step S55 is YES,
Proceeding to step S56, it is determined whether or not the recording instruction flag ARF [j] for instructing start / end of recording of the audio data of the recording channel is "1". The flag ARF [x] is a flag that is set to “1” by the CPU 10 prior to the recording start time, and is set to “0” at the recording stop time by a timing generation process described later.

If the flag ARF [j] is set to "1", the result of the determination in step S56 is YE
The result is S, and the process proceeds to step S57. In step S57, the recording pointer ARP [j] of the R buffer of the recording channel is advanced by one, and the waveform sample data taken in from the A / D converter 36 and stored in the output register in the mixer 34 is taken out. And ARP [j]
Write to the address indicated by. Where the pointer ARP
When [j] advances to the final position of the corresponding R buffer, ARP [j] is returned to the head of the same R buffer again. Nothing is performed for the recording channel whose ARF [j] is “0”. Then, the process proceeds to step S58, j is advanced by one, and the above steps S56 to S58 are repeated until j = 19 (step S59),
The transfer process of the second transfer circuit 33 in this DAC cycle ends.

As described above, the second transfer circuit 33 determines, for each DAC cycle, whether or not an instruction to start sounding has been issued for all sounding channels (channels 0 to 15). For the sounding channel for which the sounding start instruction has been issued, one waveform sample data is read from the P buffer and output to the mixer 34. On the other hand, all recording channels (channels 16 to 19) are read. For the channel (channel), the waveform sample data A / D converted by the A / D converter 36 via the mixer 34 for the recording channel for which the recording start instruction has been issued is written to the R buffer.

Next, the reproduction instruction flag APF [x],
Alternatively, a timing generation process for setting or resetting the transfer instruction flag TRF [x] or the recording instruction flag ARF [x] at a designated timing will be described with reference to FIG.
This will be described with reference to the flowchart shown in FIG. This timing generation process is a process that is always executed by the timing generation unit 39.

As described above, in this embodiment of the present invention, the 32-bit counter 38 for counting the number of DAC cycles (in this embodiment, 44.1 KHz) is provided. Therefore, this counter 3
8, approximately 25 hours can be counted, and in this embodiment of the present invention, the timing of starting and ending the waveform reproduction and recording is controlled by the time in units of a DAC cycle. That is, the start time and the end time of the reproduction or the recording are specified by the time data in the unit of the DAC cycle.

The timing generator 39 includes a reproduction start count value PSC [x] in units of a DAC cycle which specifies the count value of the counter 38 and the reproduction start time of the channel set by the CPU 10, and a reproduction stop time. , A playback end count value PEC [x] in units of a DAC cycle, and a DAC for specifying a recording start time.
Recording start count value RSC in cycle units
[X] and a recording end count value REC [x] in units of a DAC cycle specifying a recording stop time, and a corresponding reproduction instruction flag APF [x] or
Transfer instruction flag TRF [x] or recording instruction flag AR
A process for setting or resetting F [x] is executed. That is, the timing generator 39
First, a flag AP corresponding to each channel is set at the time of initial setting.
F [x] and ARF [x] are reset to "0" (step S61). Then, the count value of the counter 38 and the PS of each channel set in the register 40 are set.
By comparing C [x] and PEC [x] or RSC [x] and REC [x], a match between the count value of the counter 38 and each of the designated times is detected (steps S62 and S63).

Then, the PSC of any channel
[X], PEC [x], RSC [x] or REC
If a match between [x] and the count value of the counter 38 is detected, the process proceeds to step S64 and the corresponding flag AP
F [x] or TRF [x] to ARF [x]
Control. That is, PSC [x] of a certain channel
Is equal to the count value of the counter 38, the flag APF [x] of the channel is set to “1”,
When PEC [x] matches, the flag APF [x] of the channel is reset to “0”. When the RSC [x] of a certain channel matches the count value of the counter 38, the flag TRF of the certain channel is set.
[X] is set to “1”, and when REC [x] matches, the flag ARF [x] is reset to “0”.

Thus, the PSC of the channel
The flag APF [x] for instructing the reproduction of the channel is set to "1" for the time from the time specified by [x] to the time specified by PEC [x]. Further, the flag TRF [x] instructing the transfer at the time specified by RSC [x] of the channel is set to “1”, and the RE
The flag ARF [x] instructing recording at the time designated by C [x] is set to “0”. As a result, by the transfer processing by the second transfer circuit 33 shown in FIG. 6A, the waveform sample data of the sounding channel is transmitted to the mixer 34 or the A / D of the recording channel is changed.
Reading of the converted waveform sample data is executed. Note that an interrupt may be generated for the CPU 10 when the designated time is detected for each of PEC [x] and REC [x]. CPU 10
The channel whose reproduction has been completed is released for the next reproduction in response to the interruption by PEC [x], and the channel whose recording has been completed is released for the next recording in response to the interruption of REC [x].

As described above, in the present invention, the register in which the timing data of each channel is set by the central processing unit, the counter for counting the timing pulse, and the count value of the counter and the value set in the register are set. Timing generating means for generating a timing signal for each channel based on the timing data, and reading and reproducing waveform data from a storage area corresponding to the channel in the buffer memory according to the timing signal. A plurality of waveform data stored in the memory can be simultaneously reproduced at an accurate timing.

Next, the first transfer circuit 31 when the CPU 10 executes the reproduction instruction event processing of FIG.
And the operation of the second transfer circuit 33 will be described. CPU
When the TWF [x] of the channel x used for reproducing the WAVE data is set to 1 in step S24 in step S10, the first transfer circuit 31 sets the flag SUS [x] of the channel x to "0" in step S32. To "." At the start of the transfer, the x-channel P buffer is empty, and it is assumed that the channel to be transferred has a lot of data.
At 35, the channel number indicating the channel x is set in the register i. In this state, by repeatedly executing step S43, the P buffers indicated by the addresses SA [x] and EA [x] are stored in the P buffer of the x channel.
The waveform at the beginning of the WAVE data stored in the C buffer is transferred by 32 samples every DAC cycle. After the waveform sample is prepared in the x-channel P buffer in this way, the timing of PSC [x] set in step S25 is detected in the process of step S63 of the timing generator 39, and the flag APF [x ]
Is set to “1”.

The second transfer circuit 33 performs step S5 of the transfer 2 transfer process (FIG. 6A) executed at the sample period.
At 2, it detects that APF [x] is set to "1", reads out the waveform sample prepared in the P buffer while updating the pointer APP [x], and supplies it to the input register in the mixer 34. The waveform samples supplied to the mixer 34 are appropriately given an effect by the DSP 35, and then output to the D / A converter 37 and output from the sound system 29. While the waveform samples on the P buffer are being reproduced by the second transfer circuit in this way, the first transfer circuit operates in parallel, and the reproduction increases the free area of the x-channel P buffer. In this case, samples of the subsequent waveform following the head portion of the WAVE data are sequentially transferred from the PC buffer to the P buffer.

Now, what has been described above is the first RA.
An operation of reproducing a waveform of a waveform sample of one channel stored in the PC buffer of M12 and an operation of reading waveform sample data input from the microphone 28 or the like and A / D converted by the A / D converter 36. However, as described above, this waveform recording / playback apparatus can execute sequence playback. next,
The operation at the time of such sequence reproduction will be described.

FIG. 7A shows an example of sequence data used when performing sequence reproduction. As shown in this figure, the sequence data is (1)
A header section storing the name, data type, data size, time unit, etc. of the data, (2) initial data used for initial setting, etc., (3) start code, (4) command for time data and WAVE data (playback) Command or control command), and (5) an end code. Here, the time data of (4) indicates the timing at which an instruction for the subsequent WAVE data is issued at the start of operation or relative time data from the previous instruction (for example, time data in units of a DAC cycle). It is.

Here, in the example shown in FIG. 7A, the instruction for the WAVE data is (1)
A waveform playback command to start playback of each WAVE data, such as a "W1 playback command" or a "W3 playback command", and (2) "W
A command for controlling the reproduction level of each WAVE data such as a "4 level control command" and a "W10 level control command" to perform fade-in and fade-out of the WAVE data, and a command for the WAVE data such as the "W1 effect control command". There is a waveform control command for controlling an effect (for example, reverb or the like) to be added. The waveform playback instruction includes the WA
It includes the name of the VE data, the storage location (address), the sampling frequency, the time required for its reproduction, and the like.

As shown in FIG. 7B, each WAVE data is stored in, for example, the hard disk device 23, and WA data required for reproducing the sequence data is stored.
VE data is sequentially read and stored in the first RAM 12. That is, instead of transferring all the WAVE data required for reproducing the sequence data to the RAM 12, a predetermined number of WAs initially required are not transferred.
VE data is transferred to the RAM 12 and one W
After the AVE data has been reproduced, the WA to be reproduced next
VE data is loaded into the RAM 12.

The operation for reproducing such sequence data will be described with reference to the flowcharts shown in FIGS. FIG. 8 is a flowchart of a sequence playback instruction event process executed as a process corresponding to the switch operation in step S15 when a sequence playback instruction event occurs in the main program (FIG. 4). The processing is executed by the CPU 10.

When the sequence reproduction instruction event occurs, the CPU 10 receives the sequence instruction data corresponding to the sequence to be reproduced included in the sequence reproduction instruction event in step S71. Then, the run flag RF is initialized to "0" (S7).
2). Thus, the counter 38 is stopped. Then, the process proceeds to a step S73, in which the sequence data specified by the sequence instruction data received in the step S71 is analyzed, and the maximum number of channels (the maximum number of tracks) required for reproducing the sequence data is analyzed.
n is calculated, and a sound channel corresponding to the maximum track number n is assigned. Here, an area for storing the WAVE data of the n channels is secured in the PC buffer area on the first RAM 12.

Next, in step S74, n WAs are reproduced from the beginning of the sequence data.
The VE data is read from the hard disk device 23 and loaded into the area of the PC buffer on the first RAM 12 secured in the step S73. Then, in step S75, R channels are assigned to the n channels.
A start address SA [x] and an end address EA [x] respectively corresponding to the storage locations of the n pieces of WAVE data on the AM 12 are set in the register 40, and the same addresses as the end address EA [x] are set. Set the interrupt request address IA [x] (IA [x] = EA
[X]).

Next, the transfer start flag TWF [x] of the n channels is set to "1" (S76), and the reproduction start count value PSC [x] and the reproduction stop count value PEC of each n channels are set. [X] is set to a value obtained by analyzing the sequence data (S78). That is,
The playback start count value PSC [x] and the playback stop count value PEC [x] are calculated from the time data and the playback time length (or the number of waveform samples) of the WAVE data included in the waveform playback command. , In the register 40. In the channel in which TWF [x] is set to 1, the first transfer circuit performs the operations shown in FIGS.
Is executed, the leading waveform of the WAVE data to be reproduced on the same channel is sequentially transferred from the PC buffer to the P buffer.

In step S78, the timing at which the waveform control command, that is, the level control command or the effect control command is executed is calculated from the time data in the sequence data, and an interrupt (control interrupt) is generated at that timing. Thus, the count value corresponding to the timing is set in the register. Here, first, the first control instruction (in the example shown in FIG. 7A, "W4
Level control command ”).
Next, in step S79, the counter 38 is reset, the run flag RF is set to "1", and the counter 38 starts counting. As described above, since the counter 38 counts the pulses corresponding to the DAC cycle, the counting of the DAC cycle is started from “0”.

As described above, based on the sequence reproduction instruction, the CPU 10 executes the preparation processing necessary for reproducing the sequence and starts the reproduction. Then, the first RA
Reproduction of the n WAVE data stored in M12 is sequentially started in the same manner as described above. That is, when the timing of the PSC [x] is detected in step S63 of the timing generator 39, the APF of the same channel is detected.
[X] is set to 1, and the reproduction of the P buffer of the same channel by the second transfer circuit 33 as described with reference to FIG. When the P buffer becomes empty due to the reproduction, the subsequent waveform of the WAVE data following the first waveform after the reproduction of the same channel is transferred to the PC buffer by the processing of the first transfer circuit 31 shown in FIGS. 5B and 5C. To the P buffer sequentially. The reproduction by the second transfer circuit 33 is performed by the timing
It continues until the timing of [x] is detected.

Now, in this way, the first RAM
12 is transferred from the PC buffer on the PC buffer 12 to the P buffer on the third RAM 32, and the reproduction of the WAVE data proceeds. However, the transfer pointer TP [x] of the data on the PC buffer indicates the interrupt. When the requested address IA [x] is reached, a channel interrupt occurs as described above. That is, since this channel interrupt occurs when the PC buffer of the channel has been read to the end, it indicates that all the WAVE data has been transferred to the P buffer. R for 1
It can be loaded into the AM12 PC buffer. This load processing is executed by a channel interrupt processing routine.

FIG. 9A is a flowchart for explaining the operation of this channel interrupt processing routine.
As described above, all the WAVE data of the channel in the PC buffer in the first RAM 12 is transferred to the P buffer in the third RAM 32, and when a channel interrupt occurs, in step S81, the hard disk device 23 transfers the data to the PC buffer. It is determined whether there is any WAVE data to be loaded next to the already loaded WAVE data. As a result of this determination, all of the WAVE data for which the tone generation is instructed by the sequence data is already
If the data is loaded into the buffer and there is no more data to be transferred to the hard disk device 23, the process proceeds to step S87, and it is determined whether or not there is a currently reproduced sound channel. As a result, when there is no sound channel for which the waveform is currently being reproduced, since the reproduction of all the WAVE data has been completed, the run flag RF is reset to "0" and the sequence reproduction processing is completed. When there is a sounding channel being reproduced, the channel interrupt processing is terminated.

On the other hand, if the WAVE data to be reproduced remains and the result of the determination in step S81 is YES, the channel number is substituted for a variable k (S8).
2) The WAVE data is read from the hard disk device 23 and loaded into a free area in the first RAM 12 (S83). Then, the process proceeds to step S84, and the area storing the WAVE data in step S83 is used as a new PC buffer of k channels.
Corresponding start address SA [k], end address EA
[K] and the interrupt request address IA [k] (= EA
[K]) is set in the register 40.

Next, the corresponding transfer start flag TWF
[K] is set to “1” (S85), and accordingly,
The first transfer circuit 31 sets the leading waveform of the WAVE data to P
The data is sequentially transferred from the C buffer to the P buffer. Then, the corresponding reproduction start count value PSC [x] and reproduction stop count value PEC [x] are set (S86). As described above, when a channel interrupt occurs, the data to be reproduced next is transferred to the PC buffer, and the preparation processing for reproducing the corresponding waveform is executed. The k-wave WAVE data prepared in this way is shown in FIG.
In the same manner as the n pieces of WAVE data described in the sequence preparation process, the data is reproduced from PSC [k] to PEC [k].

Next, the control interrupt processing corresponding to the other interrupt setting in step S78 (FIG. 8) will be described with reference to the flowchart shown in FIG. 9B. If the count value of the counter 38 is equal to the value of the step S7
When the count becomes the count value set in the register by 8 and the control interrupt is generated, the CPU 10 firstly sets
The control process based on the control command at this timing (“W4 level control command” in the example shown in FIG. 7A) is executed. This is performed, for example, by writing level control data or the like corresponding to the control command into the register 40, and the level of the channel in the mixer 34 is controlled. In the case of an effect control command, a corresponding DSP control parameter or the like is written in the register 40, and the contents of the effect processing performed by the DSP are controlled.

Next, the CPU 10 determines in step S92
To search for the next control instruction in the sequence data. Then, when there is no control instruction, the control interrupt processing is terminated as it is. On the other hand, when the next control instruction is found as a result of step S92, timing information of the control instruction, that is, a count value indicating the timing at which the control instruction is executed is calculated based on the time data. Is set in the register (S93). Then, the control interruption process ends. As a result, when the timing of the next control instruction comes, the control interrupt processing is executed again. In this manner, a plurality of Ws stored in the hard disk drive 23 based on the sequence data
Reproduction of the AVE data at the designated timings, and level control and effect control at the designated timings are performed.

Now, in the above, (1) the first RAM 12
The case where WAVE data stored in the upper PC buffer is reproduced and the case where (2) sequence reproduction is performed have been described. Next, (3) direct reproduction for directly reproducing a waveform stored in a hard disk or the like will be described.

The hard disk device 23 or CD
In the case of direct reproduction in which long-time WAVE data stored in an external storage device such as the ROM device 24 is reproduced while being sequentially read, the interrupt request address IA [x] is stored in the middle of the PC buffer as described above. Repeatedly set to position and final position. In the interrupt processing routine, the waveform sample data is sequentially read from the external storage device into the PC buffer, so that the PC buffer on the first RAM 12 is used as a double buffer, and the long-time WAVE data is stored. Playback can be performed sequentially. It is also possible to play while receiving WAVE data from the network 26 via the network interface circuit 27. Also in this case, as in the case of the direct reproduction, the PC buffer is used as a double buffer.

Further, in the present invention, the CPU 1
It is also possible to reproduce the waveform sample data generated using a so-called software tone generator which generates the waveform sample data by software using 0. In this case, the CPU 10 calculates and generates, for example, 16 channels of tone waveform samples by the CPU 10 based on MIDI data input through a MIDI interface or the like (not shown).
Write to the PC buffer on AM12. Then, in the same manner as in the above-described embodiment, this PC
The waveform sample data written in the buffer is reproduced. According to this method, effects can be added to the tone generated by the DSP 35, and the processing load on the CPU 10 can be reduced as compared with the case of a normal software sound source that executes up to the effect processing on the tone generated by the CPU 10. It is possible to reduce it.
In any of the waveform reproduction described above, highly accurate timing control can be performed as described above.

In the above-described embodiment, 32 samples of one channel are burst-transferred in each DAC cycle. However, burst transfer for a maximum of n channels may be performed in each DAC cycle. Alternatively, a different number of samples may be burst-transferred for each channel. With this change,
Although the bus is occupied for a long time, the transfer by the first transfer circuit is more stable. In the above-described embodiment, one burst transfer is fixed at 32 samples. However, the number of samples to be burst-transferred is set to 48 samples according to the free space of each channel when the free space is large.
If the number is larger, it may be changed to 64 samples. With such a change, the possibility that the transfer delay of the first transfer circuit will occur is reduced, and the transfer stability is improved.

Further, in the above-described embodiment, the size of the buffer memory is fixed at 1K words, but the capacity may be freely set. Increasing the capacity improves the stability of reproduction, while decreasing the capacity simplifies the circuit configuration. Further, a different capacity may be set for each channel. In that case, the buffer memory of the channel to be stably reproduced may be set to a large capacity. Furthermore, in the above-described embodiment, the n pieces of waveform data are loaded from the hard disk device to the memory at the time of the sequence reproduction. However, various changes can be made to this portion. For example, an upper limit of the capacity used for storing waveform data may be provided on the memory, and a plurality of pieces of waveform data to be reproduced in a sequence may be sequentially loaded from the one reproduced first to the memory until the upper limit is reached. . Alternatively, it is possible to load the memory up to the waveform data reproduced at a position (future) a predetermined time ahead of the position currently being reproduced in the sequence.

Furthermore, in the above-described embodiment, the number of channels to be secured and the number of waveform data to be loaded are both n in common, but may be different from each other. Furthermore, in the above-described embodiment, the number of channels necessary for starting the sequence reproduction is detected to determine the number n of channels to be used.
This n is specified in advance for each sequence data,
You may set n manually. Furthermore, in the above-described embodiment, the PC buffer is the first
Although described as being provided on the RAM 12, the present invention is not limited to this, and a PC buffer may be provided on the second RAM 21. In short, the CP
It is sufficient that the PC buffer is arranged in the memory space of U10. Furthermore, in the embodiment described above, the A / D converter 36 and the D / A converter 37 are provided on the sound input / output board 30, but these circuits are not provided on the sound input / output board. , USB (Univ
esal Serial Bus) or a digital audio device or the like via a serial interface such as IEEE1394. In this case, input and output can be performed using digital data, and noise and the like can be prevented from being mixed.

In the above embodiment, the counter 38 counts the number of DAC cycles.
Although the case of the bit configuration has been described, the invention is not limited to this. For example, the number of bits of the counter is not limited to this, and the
Pulses having a period of あ る い は or の of the C cycle may be counted to further improve the resolution of the counted time data. Furthermore, the sizes of the P buffer and the R buffer, the number of channels for reproduction and recording, the number of channels of the mixer, the number of bits of the waveform sample data, and the like are all limited to the numerical values described in the above embodiment. However, each can be changed to an arbitrary value. Furthermore, in the above-described embodiment, the sound input / output board 3
0 has been described as being connected to the PCI bus, but is not limited to this.

[0098]

As described above, according to the waveform reproducing method, the waveform reproducing apparatus, the waveform output circuit and the sequence reproducing apparatus of the present invention, the reproduction of the waveform is started based on the time data in the unit of the DAC cycle. Since the end timing can be controlled, highly accurate timing control can be performed. In addition, since the CPU does not directly control the reproduction, the waveform reproduction timing does not fluctuate according to the execution state of the processing of the CPU, and the waveform can be reproduced with high accuracy. This makes it possible to prevent interference between waveforms even when reproducing waveforms of a plurality of channels.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a waveform recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a sound input / output board in the embodiment shown in FIG.

FIG. 3 is a diagram for explaining a data flow in the embodiment shown in FIG. 1;

FIG. 4 is a flowchart of a main routine in the waveform recording / reproducing apparatus according to the embodiment of the present invention.

FIG. 5 is a flowchart for explaining a reproduction instruction event process and an operation of a first transfer circuit in the waveform recording / reproducing apparatus according to the embodiment of the present invention;

FIG. 6 is a flowchart illustrating an operation of a second transfer circuit and a timing generation process in the waveform recording / reproducing apparatus according to the embodiment of the present invention;

FIG. 7 is a diagram illustrating an example of use of sequence data and a storage area in a first RAM in a waveform recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating a sequence playback instruction event process in the waveform recording / playback apparatus according to one embodiment of the present invention.

FIG. 9 is a flowchart for explaining a channel interruption process and a control interruption process in the waveform recording / reproducing apparatus according to the embodiment of the present invention.

[Explanation of symbols]

10 CPU, 11 ROM, 12, 21, 32 RA
M, 13 display, 14, 16, 22 interface circuit, 15 keyboard, 17 timer, 18 local bus, 19 HOST-PCI bridge circuit, 20
PCI bus, 23 hard disk drive, 24 CD
-ROM device, 25 SCSI interface circuit,
26 network, 27 network interface circuit, 28 microphone, 29 sound system, 30 sound input / output board, 31, 33 transfer circuit, 34 mixer, 35 DSP, 36 A / D converter, 37 D / A converter, 38 counter, 39 timing generator, 40 registers

Continuation of the front page (56) References JP-A-11-95752 (JP, A) JP-A-10-20860 (JP, A) JP-A-10-97259 (JP, A) Patent 2671747 (JP, B2) Patent 2798077 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) G10L 11/00-13/08 G10L 19/00-21/06 G10H 1/00-7/12

Claims (4)

(57) [Claims] 1. A waveform reproducing method for reproducing waveform data according to an instruction of a central processing unit, comprising: A. a step of sequentially transferring the waveform data stored in the memory to the buffer memory via the bus, partly from the beginning, in accordance with an instruction from the central processing unit; B. generating a timing signal when detecting a coincidence between a count value of a counter for counting timing pulses and timing data set by the central processing unit; A step of sequentially reproducing the waveform data stored in the buffer memory from the beginning according to the timing signal generated in step B. 2. A central processing unit for controlling the entire apparatus; a first bus connected to the central processing unit; a memory connected to the first bus and storing a plurality of waveform data; A second bus provided independently of the first bus, a buffer memory connected to the second bus, each having a storage area for a plurality of channels capable of storing a part of waveform data, Supply means for sequentially supplying the waveform data to be reproduced in each channel from the head to the storage area corresponding to each channel of the buffer memory in accordance with an instruction of the processing device; A register in which timing data is set; a counter for counting timing pulses; a count value of the counter and the timing set in the register Timing generation means for generating a timing signal for each channel based on data, and read / reproduction means for reading and reproducing waveform data from a storage area corresponding to the channel in the buffer memory in accordance with the timing signal. A waveform reproducing apparatus comprising: 3. A waveform output circuit for reading and reproducing waveform data from a memory for storing a plurality of waveform data connected to a bus, wherein a part of the waveform data can be stored for each of a plurality of channels. A buffer memory having a plurality of storage areas; and a supply unit that supplies the waveform data to be reproduced in each channel from the memory to the storage area corresponding to each channel of the buffer memory sequentially from the top via the bus. A register for storing timing data; a counter for counting timing pulses; timing generating means for generating a timing signal for each channel based on the count value of the counter and the timing data set in the register; Corresponds to the corresponding channel of the buffer memory according to the signal And a reading / reproducing means for reading and reproducing waveform data from the storage area. 4. A sequence data reproducing apparatus using n (n is an integer) channels, comprising: a memory for storing a plurality of waveform data; and a plurality of events indicating reproduction timings of the plurality of waveform data. A sequence memory for sequentially storing data, a buffer memory having n storage areas corresponding to n channels, and an event data stored in the sequence memory.
Channel allocation means for sequentially allocating to the open channels of the n channels from the earlier timing; and, among the plurality of waveform data, waveform data indicated by event data allocated to each channel,
Supply means for sequentially supplying the storage area of the corresponding channel partly from the head portion; a counter for counting timing pulses; and a reproduction timing of event data assigned to each channel based on the count value of the counter. Detecting means for detecting; reading and reproducing means for sequentially reading and reproducing the waveform data stored in the storage area of the detected channel in response to detection of the reproduction timing; detecting the channel on which reading by the read and reproducing means has been completed. And a channel opening means for opening the channel.