JP3114655B2 - Integrated circuit for test board failure detection of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a tester for confirming the function of an integrated circuit, wherein the test board used in the tester can be efficiently wired.

[0002]

2. Description of the Related Art A test board used for a function confirmation test of an LSI has been increasingly complicated in its manufacture due to the recent trend of increasing the number of pins of the LSI. This test board includes an LSI under test inserted into a socket or the like, for example.
This is a wiring board for making an electrical connection with the SI tester. As a method for checking the failure of the test board itself, the test board is inspected by a method of manually measuring the resistance for each terminal by using a resistance measuring instrument provided with a probe in the related art.

[0003] In addition, a non-defective sample of a plurality of LSI products is prepared, and this is sampled by using an untested test board.
In some cases, a tester test detects a failure of a test board.

[0004] For example, in Japanese Patent Application Laid-Open No. Hei 5-264633, one measurement terminal is connected to all other input terminals via resistors, and when a voltage is applied to each input terminal, an input appearing at the measurement terminal appears. By measuring a unique resistance value for each input terminal that appears for each terminal, a failure of the test board is detected.

FIG. 5 is a diagram showing a configuration of a test board wiring continuity test circuit proposed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 5-264633, wherein reference numeral 55 denotes a semiconductor test device for testing a semiconductor device under test, and 53 denotes a device under test. Semiconductor device and semiconductor test equipment 5
A test board used as the connection medium between
52 is a semiconductor socket, 56 is a test board wiring continuity test circuit for testing wiring continuity of the test board 53, and m terminals of the circuit 56 are connected to the m terminals of the test board 53 via the semiconductor socket 52. Of the semiconductor test apparatus 55 via connection pins called pogo pins.
It is connected to each terminal of the book. 58 is a diode,
57 is a resistor having one end connected to the cathode of the diode 58; 59 is an m number of resistors connecting between the other end of the resistor 57 of the (m-1) th terminal and the mth terminal, and between the other ends of the resistors 57; And the resistor 59 has the same resistance value as the resistor 57.

[0006]

The first problem with the conventional test board inspection method is that, in the case of a method using a resistance measuring instrument, the reliability of the inspection itself is low.
And it takes considerable time for inspection.

The reason for this is that, due to the increase in the number of pins in the LSI package and the reduction in the pitch of the leads, the detectability has been reduced due to a contact error or the like for manual inspection.

A problem with the configuration described in Japanese Patent Application Laid-Open No. 5-264633 is that if there is a defect in the measurement terminal, it is impossible to inspect all other terminals. In addition, no inspection was performed on the power supply and the GND terminal.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a test board which has been generated with complicated wiring in recent years, in which problems such as erroneous wiring of the test board are eliminated. An object of the present invention is to provide a semiconductor integrated circuit that can detect a signal correctly and in a short time. Another object of the present invention is to provide a power supply / GND on a test board.
An object of the present invention is to provide a semiconductor integrated circuit capable of inspecting all terminals by enabling continuity inspection of terminals.

[0010]

Means for Solving the Problems] To achieve the above object, a semiconductor integrated circuit of the present invention includes input and output terminals of the plurality of the reset circuit previously of the input output terminals, and a signal selection circuit, An output circuit with a data retention / output switching mechanism,
When a signal is input to an arbitrary input / output terminal of the plurality of input / output terminals, the signal is output to a specific plurality of input / output terminals so that the wiring property of the test board can be confirmed. It is characterized by having done.

[0011]

Embodiments of the present invention will be described below. The semiconductor integrated circuit of the present invention, in a preferred embodiment thereof, includes a circuit in which, when a signal is applied to an arbitrary input / output terminal, the signal is output to a specific plurality of circuits.
Test board wiring can be checked.

When a high-level signal is input to one terminal, a high-level output appears from, for example, two terminals. Therefore, by detecting the signal and comparing it with an expected value, whether or not there is an error in the wiring of the board is determined. Can be detected.

If the wiring is normal, a low-level signal is output from terminals other than the terminal to which the high-level signal is input and the two terminals from which the high-level signal is output.

On the other hand, if there is a miswiring, the expected value High
Since the actual output becomes Low level with respect to the level,
It turns out to be wrong.

When a low-level signal is input to all the terminals first, the output of the flip-flop (FF) is held at the low level, and the state is output from all the terminals. Further, a Low signal is input to the enable terminal of the flip-flop (FF) at the output stage of each terminal, and the output of the flip-flop (FF) is cut off.

Next, a high-level signal is input to one terminal. When a high-level signal is input to one terminal, a high-level signal is output from the two terminals. By detecting this, it is checked whether there is an error in the wiring.

Further, in the embodiment of the present invention, there is provided a circuit for connecting the power supply and the GND terminal to the signal terminal on a one-to-one basis. When a high-level signal is input from four or more predetermined terminals, all the power supplies and the GND terminals are
In an integrated circuit, it is connected one-to-one with a signal terminal. Thus, by detecting the output level of the signal terminal connected to the power supply and the GND, it is possible to detect the abnormality of the wiring of the power supply and the GND on the test board.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing an embodiment of the present invention. Referring to FIG. 1, SR flip-flops (FF) 21 to 28 are provided for each of the terminals (input / output terminals) 1 to 8. For example, a reset (R) terminal of the flip-flop 21 is an input of the corresponding input / output terminal 1. And the output of a NOR gate which receives the input of the input and output terminals 4 and 6 as an input, and the set (S) terminal receives the input of the input and output terminals 4 and 6 of the OR gate. In the enable terminal, a signal obtained by delaying the output of the flip-flop 29 by the delay circuit 30 is commonly input to all flip-flops 21 to 28. The inputs of the flip-flop 29 are terminals 1 to 8
Are supplied by ORing the inputs from.

First, by inputting a low-level signal to all the terminals 1 to 8, the outputs of the flip-flops (FF) 21 to 28 in the output stages of all the terminals are held at the low level. The outputs of the NOR gates respectively connected to the reset (R) terminals of the flip-flops (FF) 21 to 28 become High level.

A low-level signal passes through the flip-flop (FF) 29 and is input to the enable (E) terminal of the FF 21, and all the terminals enter a high impedance state.

Next, when a high-level signal is input to the terminal 1, the flip-flops FF26 and FF26 input the input of the terminal 1 to the set (S) terminal through an OR gate.
24 is inverted to High level.

Thereafter, a high-level signal is input to the enable terminals of the FFs 21 to 28 through the flip-flop (FF) 29 and the delay circuit 30, and the FFs are enabled, and signals are output from all terminals.

Signals output from all terminals except the terminal 1 are detected and compared with expected values to determine whether or not wiring is correct.

For example, when a high-level signal is input to terminal 1, if the board is correctly wired, terminals 6 and 4 connected to the outputs of flip-flops 26 and 24
Outputs a High level signal.

Similarly, a test is performed by inputting a High level signal for each terminal for all terminals.

FIG. 2 is a time chart for explaining the operation of one embodiment of the present invention. The case where the test of the terminals 1 to 3 is performed will be described below.

(1) By inputting a low-level signal to all terminals 1 to 8, the FF 21 in the output stage of all signal terminals
The outputs of 〜28 go to the low level. At this time, the output of the FF enters a high impedance state.

(2) By inputting a high-level signal to the terminal 1, the output of the FF at the output stage of the terminals 6 and 4 is inverted to the high level.

(3) The signal passed through the delay circuit enters the enable terminal of the FF, and a high-level signal is output from terminals 6 and 4.

(4) To test the next terminal, a low-level signal is input to all terminals. This is the same as the operation (1) at that time.

(5) By inputting a high-level signal to the terminal 2, the output of the FF at the output stage of the terminals 7 and 5 is inverted to the high level.

(6) The signal that has passed through the delay circuit enters the enable terminal (E) of the FF, and a high-level signal is output from the terminals 7 and 5.

(7) To test the next terminal, input a low-level signal to all terminals. The operation at that time is the same as (1).

(8) By inputting a high-level signal to the terminal 3, the output of the FF at the output stage of the terminals 8 and 6 is inverted to the high level.

(9) The signal that has passed through the delay circuit enters the enable terminal of the FF, and a high-level signal is output from the terminals 8 and 6.

FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention.

FIG. 3 shows a specific circuit for enabling the continuity test of the power supply / GND terminal on the test board as compared with FIG.

Referring to FIG. 3, regarding terminal 1,
The transistor 61 is connected between the terminal 1 and the power supply VDD4, the transistor 71 is connected between the transistor 61 and the common line 92, the output of the flip-flop 81 is connected to the gate of the transistor 61, and the inverted output is connected to the gate of the transistor 71. It is connected to the set and reset input terminals of the flip-flop 81 (signals complementary to each other are input) and the output of the AND gate 89. This AND gate 89 has an OR gate output of terminals 2 and 3,
The OR gate outputs of the terminals 6 and 7, the OR gate outputs of the terminals 10 and 11, and the OR gate outputs of the terminals 14 and 15 are input, and the outputs are commonly input to the flip-flops 81 to 88.

The terminals 2, 3, 6, 7, 10, 11, 14,
15, when a High-level signal is input, the outputs of the flip-flops FF81 to 88 are inverted, the transistors 61 to 68 are turned on, and the transistors 71 to 78 are turned off.
It becomes F.

For example, since the voltage of the power supply VDD4 appears from the terminal 1, conduction can be confirmed by detecting the level. Similarly, it can be confirmed whether all the power supplies and the GND terminals are correctly wired on the board.

It should be noted that the above-mentioned circuit is constructed by connecting H or more terminals from four or more terminals.
The configuration is such that it does not operate unless a high-level signal is input, and can coexist with the circuit shown in FIG.

FIG. 4 is a time chart for clearly showing the operation of the embodiment of the present invention. The procedure for detecting the miswiring of all power supplies and GND terminals of the test board will be described below.

(1) A low-level signal is input to all terminals.

(2) Terminals 2, 3, 6, 7, 10, 11,
After inputting a High level signal from 14, 15
The output levels of the terminals 1, 4, 5, 8, 9, 12, 13, and 16 are detected, and the pass / fail is determined by comparing the output level with an expected value.

[0046]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that a defect in a signal wiring of a test board can be accurately detected in a short time.

The reason is that, in the present invention, when a signal is input from one terminal in the integrated circuit for test board failure detection, the signal is output from the other two terminals, so that the output signal and the expected value are compared. This is because the configuration is such that it is possible to detect whether there is a defect in the wiring of the test board by comparing. This is because, according to the present invention, it is possible to input and output signals at high speed by the LSI tester without using any manual operation.

A second effect of the present invention is that a defect of the power supply / GND terminal on the test board can be detected in a short time and accurately.

The reason is that in the test board failure detecting integrated circuit of the present invention, the signal terminal and the power supply or the GND terminal can be connected one-to-one. This makes it possible to input and output signals at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional test board wiring continuity test circuit.

[Explanation of symbols]

 1-16 input / output terminal 21-29 flip-flop 30 delay circuit 61-68, 71-78 transistor 81-88 flip-flop 89 AND gate 90 GND 91 VDD

Claims (4)

(57) [Claims] [Claim 1 further comprising a plurality of input and output terminals of the reset circuit previously of the input output terminals, and a signal selection circuit,
An output circuit with a data holding / output switching mechanism, comprising: when a signal is input to an arbitrary input / output terminal of the plurality of input / output terminals, the signal is output to a specific plurality of input / output terminals, A semiconductor integrated circuit characterized in that the wiring properties of a test board can be confirmed. 2. A semiconductor integrated circuit having a plurality of input / output terminals, wherein when a signal of a predetermined logic level is input to one of the plurality of input / output terminals, an output of a predetermined logic level is output from the plurality of terminals. It is configured so that an output of a logic level opposite to the predetermined logic level appears at the other terminals. By detecting these signals and comparing them with expected values, a defect or error in the wiring of the test board is detected. A semiconductor integrated circuit characterized in that it is possible to detect whether or not it is present. 3. A circuit for connecting a power supply and a ground terminal to a signal terminal on a one-to-one basis. When a signal of a predetermined logic level is input from a predetermined number or more of terminals, each power supply and a ground terminal are connected to an integrated circuit. , One-to-one with the corresponding signal terminal
A semiconductor integrated circuit characterized by detecting an output level of a signal terminal connected to a power supply and a ground and detecting an abnormality of wiring of the power supply and the ground on a test board. 4. A semiconductor integrated circuit having a plurality of input / output terminals , wherein an input from one of the plurality of input / output terminals is provided.
Signal, and the one input / output terminal is different from a predetermined one.
Controlled by input signals from multiple other input / output terminals
A flip-flop that is set when any one of the input signals from the predetermined plurality of other input / output terminals is at a high level, and that is set when the input signal from the one input / output terminal and the predetermined A flip-flop that is reset when input signals from the plurality of other input / output terminals are both at a low level , corresponding to each of the plurality of input / output terminals.
Multiple comprising, before setting the active state of the enable terminal of the plurality of flip <br/> flop after said plurality of predetermined delay time from the time when any of the signals becomes high level of input and output terminals Te
The outputs of the plurality of flip-flops are connected to the plurality of input / output terminals.
Comprises means Ru is outputted from the child once, after all the plurality of input terminals to a low level,
When a high-level signal is input to one of the plurality of input / output terminals, a high-level output appears from the plurality of terminals, and a low-level output appears at the other terminals. A semiconductor integrated circuit characterized in that it is possible to detect whether there is a defect or an error in a wiring of a test board by detecting and comparing with an expected value.