JP3112182B2 - Multi-level read-only memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a multi-valued read-only memory (ROM) device having a memory cell in which one memory cell indicates one of multi-level states.

In one memory cell, one of multi-value states, for example, quaternary, "00", "01", "10", "11"
Has been proposed. Use of such a multi-value ROM has an advantage that the degree of integration of the ROM device is improved. FIG. 9 shows a conventional four-valued RO.
5 shows a plan configuration of one ROM cell in the M device,
By combining the storage states of two normal ROM cells formed opposite to each other, the above-mentioned four multi-value states are expressed. However, the quaternary ROM cell has low integration because it uses two ordinary ROM cells. Therefore, one RO
A multi-level ROM cell has been proposed in which one of the multi-level values is indicated by an M cell.

The first such conventional multi-value ROM cell is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-148360. This publication discloses that the gate width is changed according to the multi-value state. When the gate width is changed, the conductance of the MOS transistor changes. By detecting this change in conductance as a change in current between the source and the drain, any of the multi-valued storage states can be identified. Japanese Patent Application Laid-Open No. 55-80888 discloses that a bit line is connected to a voltage V _dd on the premise of such a change in conductance.
It is disclosed that any one of the multi-value storage states is determined by detecting a voltage difference caused by a difference in a discharge curve or a difference in conductance ratio. Further, Japanese Patent Application Laid-Open No. 61-263263 discloses that the conductance is effectively changed by changing the depletion region without changing the gate width.

[0004]

Problems to be Solved by the Invention
In order to form the four-value ROM cell disclosed in Japanese Unexamined Patent Publication No. 60-261 and Japanese Unexamined Patent Publication No. 61-263263, a masking step and an implantation step are further required.
Therefore, in order to form these quaternary ROM cells, it is necessary to add the above process in addition to the normal process, which leads to an increase in equipment and manufacturing costs, and further, an increase in product prices and a decrease in yield. Occurs. Further, for example, a programmable logic array (P
In the case where a multi-level ROM cell is mixedly mounted in an LA) or the like, the conventional process has a problem in process affinity. JP-A-55-
In the multi-value state detection method disclosed in Japanese Patent Publication No. 80888,
The discharge time varies depending on the gate width, and in the case of a ROM cell having a small transistor size, it takes too much time to detect the voltage difference, and there is a problem that the operation speed is low. Accordingly, it is an object of the present invention to provide a multi-level read-only memory device that does not require an additional manufacturing process, has a high degree of integration, and has a high operation speed.

[0005]

In order to solve the above-mentioned problem, a multi-value read-only memory device according to the present invention comprises a plurality of data storage transistors having a channel length corresponding to multi-value information and a different channel length. A plurality of reference transistors, a comparison unit that compares the output signal of the selected data storage transistor with the output signal of the plurality of reference transistors, and the selected data storage transistor based on the comparison result of the comparison unit. possess a discriminator for discriminating the multi-value information stored, the plurality of reference
The channel length of each transistor is
Of adjacent channel lengths
It is set to the length between . Also, in the multi-valued read-only memory device of the present invention, the comparison section has a plurality of comparison circuits for comparing an output signal of the selected data storage transistor with one corresponding output signal of the plurality of reference transistors. and, determine the multivalued information the judgment unit is stored in the selected data storage transistor based on the comparison result of the plurality of comparison circuits.

[0006]

[Action] Varying the channel length of the data SL 憶To transistors constituting the memory cell conductance changes. Allowed to change the channel length of the data SL 憶To transistor in accordance with the multi-level memory state, to detect a change in conductance as a storage state value of multi-level memory states. No special process is required to form this transistor, and the process is excellent in affinity. Configuring the multi-level read-only memory device with reference to the data SL 憶To run <br/> register. In this case, data SL 憶To multilevel memory cell formed by transistor, as a specific example, based on defining the reference voltage (signal) for determining the voltage of the multi-level ROM cells (signal) Junto transistor Indicates neighboring multi-valued memory states
De - the channel length of the length between the discrete channel length data SL 憶To transistor. Voltage and the selected de from the group Junto transistor - data SL 憶To transistors, i.e., compares the output voltage of the multi-level ROM cells, one of the storage states of the multi-level memory state by decoding the comparison results Determine. Preferably, de - minimize the variation of the operation depends on the load state and precharged in accordance with the load state of the motor SL 憶To transistor - a select line of data SL 憶To transistors connected de the bit line The operation speed of the multi-value read-only memory device is improved.

[0007]

FIG. 1 is a plan view showing the configuration of each ROM cell in a four-value ROM device as an embodiment of a multi-value read only memory (ROM) device according to the present invention. (A) of FIG.
(G) each show a plan view of one MOS transistor. FIG. 2 is a partial sectional perspective view of these MOS transistors, and FIG. 3 shows an equivalent circuit thereof. FIG. 1 (A)
Each of the MOS transistors shown in FIGS.
^- a source region S and drain region D of the gate width W is formed on the substrate, the channel length across the S _i O ₂ insulating layer L
Gate G is formed. The gate width W of each of the MOS transistors in FIGS. 1A to 1G is the same. However, the channel lengths are different from L1 to L7, respectively.
In this embodiment, the channel lengths L1 to L7 are respectively
1.0 μm, 1.25 μm, 1.5 μm, 1.75 μ
m, 2.0 μm, 2.25 μm, and 2.5 μm, and the gate width W is 2.5 μm for all transistors. Of these, MOS transistors having channel lengths L1, L3, L5, and L7 whose channel lengths are separated by 0.5 μ are respectively set to “00”,
It is used as a data storage transistor for storing “01”, “10”, and “11”, that is, a ROM cell.
Transistors formed with channel lengths L2, L4 and L6 other than those described above are connected to reference voltages REF2, REF4 and REF6.
Is used as a reference voltage defining transistor. These channel lengths L2, L4, L6 are respectively
The channel length of adjacent quaternary ROM cells, for example, channel L2 is the channel length between channel length L1 and channel length L3, and channel lengths L2, L4, and L6 are also separated by 0.5 μm, respectively. Channel length between the channel lengths of the read ROM cells.

Table 1 shows the above-mentioned channel lengths and application types of the transistors. Table-1 Channel length Gate width W Application L1 = 1.0 μm 2.5 μm 4-value ROM = “00” L2 = 1.25 μm 2.5 μm Reference voltage = REF2 L3 = 1.5 μm 2.5 μm 4-value ROM = “01” L4 = 1.75 μm 2.5 μm Reference voltage = REF4 L5 = 2.0 μm 2.5 μm 4-value ROM = “10” L6 = 2.25 μm 2.5 μm Reference voltage = REF6 L7 = 2.5 μm 2 0.5 μm 4-value ROM = “11”

A four-valued RO which is a data storage transistor
Each of the M cells is formed in advance with any one of the above-described channel lengths L1, L3, L5, and L7 according to which of the four values it indicates. If the channel length L of the transistor is different, the conductance is different. When this difference in conductance is detected, one storage state of the four-valued storage state can be identified. The quaternary ROM cell is formed in advance with any one of the channel lengths L1, L3, L5, and L7, and indicates any of the quaternary storage states as shown in Table 1. Forming MOS transistors as data storage transistors with different channel lengths as described above can be realized by a normal CMOS process, and does not require an additional process. The size of such a four-valued ROM cell and the RO by the option of two diffusion layers shown in FIG.
Comparing the size of a 4-value ROM cell using M cells, the planar size was reduced by about 60 to 70% per ROM cell.

FIG. 4 shows a partial circuit configuration of a quaternary read-only memory device in which the quaternary ROM cell is applied to a quaternary ROM device. The multi-valued read-only memory device shown in FIG. 4 includes a first dummy ROM cell array 10, a first dummy word line driver circuit 11, a first ROM cell array 12, and a first dummy ROM cell array 12 for the first dummy ROM cell array. A first word line driver circuit 13 for the ROM cell array, a second ROM cell array 14, a second word line driver circuit 15 for the second ROM cell array, a second dummy ROM cell array 16, A second dummy word line driver circuit 17 for a dummy ROM cell array, first to third and fifth switch circuits SW1 to SW3, SW5 , and three comparison circuits CMP1 to CMP3;
It has a CMP3, a decoder circuit 20, and a converter circuit 22.

In the first ROM cell array 12, a plurality of quaternary ROM cells are connected in a matrix so as to be selected by a bit line BL and a word line WL (not shown). The first ROM cell array 12 is illustrated for illustrative purposes only.
Although not shown, the first word line driver circuit 13 is connected to the first ROM cell array 1.
2 is driven. First dummy RO
In the M cell array 10, a quaternary RO is applied to the bit line BL.
Channel lengths L2, L4, L6 shown in Table 1 for providing reference voltages REF2, REF4, REF6 necessary for identifying information stored in the M cell into one of four values
MOS transistor RTR for defining reference voltage formed by
2, RTR4, RTR6 are formed, and these transistors RTR2, RTR4, RTR6 are connected to the dummy word line DWL. The first dummy word line driver circuit 11 is connected to the first dummy ROM cell array 10.
Drive the dummy word line DWL in the memory. Second RO
In the M cell array 14, a plurality of ROM cells formed in advance with any of the channel lengths L1, L3, L5, and L7 corresponding to the quaternary storage state are formed, and bit lines BL and word lines WL (not shown) are formed. And are connected in a matrix. The second word line driver circuit 15 drives a word line WL in the second ROM cell array 14. A second dummy ROM cell array 16 is provided corresponding to the first dummy ROM cell array 10, and a second dummy word line driver circuit 17 is provided for the dummy word line DWL in the second dummy ROM cell array 16.
Drive.

A word line WL and a bit line BL in the second ROM cell array 14 are selectively driven to generate a second R signal.
When one ROM cell storing any one of the four values in the OM cell array 14 is selected, the voltage indicating the storage state of the selected ROM cell is changed to the switch circuit SW5.
Is applied to the comparison circuits CMP1 to CMP3. The first dummy ROM cell array 10 also operates in response to the operation of selecting the ROM cells in the second ROM cell array 14. And the switch circuits SW1 to SW
3, reference voltage regulating transistors RTR2 and RT
Reference voltages REF2, REF4, R from R4, RTR6
EF6 is output to the comparison circuits CMP1 to CMP3. The comparison result of the comparison circuits CMP1 to CMP3 is output to the decoder circuit 20, and the storage state of the selected ROM cell in the second ROM cell array 14 whose voltage level has been identified is decoded. Do 4
The value is converted to any binary data and output as read data.

Tables 2 (A) to 2 (D) show the comparison circuit CMP1.
ＣCMP3 and the result of the decoder circuit 20
The determination logic of the value storage states “00” to “11” is shown. In Table 2 below, the symbols LVL1, LVL3, LVL5,
LVL7 is the channel length L1, L3, L5, L7, respectively.
5 shows the output voltage level of the storage ROM cell. Table-2 (A): 4-level "11" decode logic comparison circuit Reference voltage read data comparison circuit output CMP1 REF2 LVL7 low level CMP2 REF4 LVL7 low level CMP3 REF6 LVL7 low level Table-2 (B): 4-level "10" Logic logic circuit reference voltage read data comparison circuit output CMP1 REF2 LVL5 Low level CMP2 REF4 LVL5 Low level CMP3 REF6 LVL5 High level Table-2 (C): 4-value "01" decode logic comparator circuit reference voltage read data comparison circuit circuit output CMP1 REF2 LVL3 low CMP2 REF4 LVL3 high CMP3 REF6 LVL3 high level table -2 (D): decode logic comparator circuit reference voltage reading data comparator circuit output CMP1 REF2 LVL 4 value "00" High CMP2 REF4 LVL1 high CMP3 REF6 LVL1 high level converter circuit 22 converts the data of four values the determination result.

When the four-valued storage state is coded by changing the channel length, the channel is changed in the same manner as when the four-valued storage state is coded by changing the gate width as in the above-mentioned prior art. As the length increases, the on-resistance increases, and the operating time of the bit line decreases due to an increase in the RC time constant. That is, the detection time varies depending on the channel length, and the longer the channel length, the longer the detection time. A plurality of quaternary ROs connected to a bit line BL
The load state of the bit line BL varies considerably depending on the storage state of the M cell, that is, the channel length, and the data read time varies. To solve this problem, as shown in the circuit configuration of FIG. 5A, a P-channel precharge transistor connected to the bit line BL supplied with the voltage V _DD and driven according to the selection of the word line WL. Of the bit line (precharge) voltage V _PR at the reference voltage REF6 corresponding to the transistor having a long channel length.
Set near. FIG. 5 (B) shows an equivalent circuit of the circuit configuration shown in FIG. 5 (A), but the resistance value R _P of the word line driver transistor WD is constant, four-value data storage state of the selected memory for ROM cell Indicates that the resistance value R _n (n = 1 to 4) of the ROM cell changes in the range of R _{1 to} R ₄ in accordance with.

The operation timing of the four-value ROM device of the first embodiment shown in FIG. 4 will be further described with reference to FIG. FIG.
In, T _PR precharge time, WL is the voltage change of the word line, SA indicates the operating voltage of the sense amplifier.
The potential of the node N illustrated in FIG. 5A is determined by a difference in size between a P-channel transistor and an N-channel transistor. For a line to which a selected ROM cell is connected to a ROM cell having a long channel length and a low operation speed, the amount of voltage change is performed by a P-channel transistor, and the voltage is increased to a voltage higher than the precharge voltage level. You. On the other hand, the potential of the line to which the selected ROM cell is connected to the ROM cell having a short channel length is reduced to a voltage lower than the precharge voltage by the N-channel transistor. As a result, in the present embodiment, the voltage is compared with the voltage drop level of the P-channel transistor and the N-channel transistor instead of relying on the discharge curve as in the prior art.
A high-speed quaternary level discriminating operation can be performed on the basis of a reliable level comparison even for a variation in the capacity of the word line WL.

FIG. 7 is a circuit diagram of a four-value ROM device according to a second embodiment of the multi-value read-only memory device of the present invention. The circuit configuration of this quaternary ROM device basically corresponds to the quaternary ROM device shown in FIG.
M device, the first dummy ROM cell array 10
Four MOS transistors RTR1, RTR2, RTR3, and RTR4 having channel lengths L1, L2, L3, and L4 are formed as reference voltage defining transistors in A. These four transistors RTR1, RTR2,
Four switch circuits S corresponding to RTR3 and RTR4
W1 to SW4 and four comparison circuits CMP1 to CM
P4 is provided. In the four-value ROM device of FIG. 7, the ROM cells in the second ROM cell array 14A are also formed to have channel lengths of L1, L2, L3, and L4.

In the four-value ROM device of the first embodiment shown in FIG. 4, as shown in FIG. 1, four types of transistors having channel lengths L1, L3, L5 and L7, and a reference voltage Three channel lengths L for output
2, L4, and L6 transistors, that is, transistors of a total of seven types of channels are formed. On the other hand, in the four-value ROM device shown in FIG.
Reference voltage defining transistors 1, L2, L3, and L4 are formed. Also, the channel length of the storage ROM cell is 4
It is formed of any one of L1, L2, L3, and L4. That is, in the four-value ROM device of FIG. 7, only four types of transistors having channel lengths L1, L2, L3 and L4 shown in FIG. do not need. As a result, the degree of integration of the first dummy ROM cell array 10A and the second ROM cell array 14A is
Value is higher than ROM devices. On the other hand, the output voltages of the storage ROM cells having the above four types of channel lengths and the reference voltage defining MOS transistors RTR1, RTR2, RTR3, R
By comparing TR4 with each other, it is possible to identify the storage state of any of the four values in the ROM cell.

Tables 3 (A) to 3 (D) show the quaternary decision logic in the decoder circuit 20A of FIG. Table-3 (A): 4-level "11" decode logic comparison circuit reference voltage read data comparison circuit output CMP1 REF1 LVL4 high level CMP2 REF2 LVL4 high level CMP3 REF3 LVL4 high level CMP4 REF4 LVL4 Undefined Table-3 (B): 4-level "10" decode logic comparison circuit reference voltage read data comparison circuit output CMP1 REF1 LVL3 high level CMP2 REF2 LVL3 high level CMP3 REF3 LVL3 undefined CMP4 REF4 LVL3 low level Table-2 (C): decode of 4-level "01" logical comparison circuit a reference voltage reading data comparator circuit output CMP1 REF1 LVL2 high CMP2 REF2 LVL2 indefinite CMP3 REF3 LVL2 low CMP4 REF4 LVL2 low table -2 (D : The decode logic comparison circuit a reference voltage reading data comparator circuit output CMP1 REF1 LVL1 indefinite CMP2 REF2 LVL1 low CMP3 REF3 LVL1 low CMP4 REF4 LVL1 low level converter circuit 22 of the four values "00" binary discrimination result of the decoder circuit 20A To the data.

FIG. 8 is an operation signal waveform diagram of the four-value ROM device shown in FIG. 7 and corresponds to FIG. ROM for storage
The saturation voltage of the cell is determined by the reference voltage transistors RTR1 and RT
It is equal to the saturation voltage of R2, RTR3, and RTR4, respectively. The other operations shown in FIG. 8 are the same as the operations described with reference to FIG.

The implementation of the multi-level read-only memory device of the present invention is not limited to the above-described embodiment, but may take various other modified forms. For example, in the above-described example, four values are described as multi-values, but the present invention can be similarly applied to other multi-values, for example, eight values or more.

[0021]

As described above, according to the present invention, it is possible to form a single memory cell showing a certain value in a multi-valued storage state, and the degree of integration of a multi-valued read-only memory device is improved. Greatly improve. Since the conductance of the memory cell is changed by changing the channel length, no special additional process is required for its manufacture, the price can be prevented from increasing, and the yield does not decrease. More standard commercials
The affinity with the OS process is also maintained. Furthermore, by optimizing the bit line precharge voltage level, reliable and high-speed reading operation can be performed. Since the difference voltage can be larger than that of a dynamic RAM or the like, a stable operation can be ensured even if the multi-value read-only memory device of the present invention is used for a DSP or the like having large substrate noise. Since the voltage difference is generated by transistors having various channel lengths with the same chip and the same precharge, this variation is small and stable.

[Brief description of the drawings]

FIG. 1 is a plan view of a ROM cell as an example in a multi-level ROM device as an embodiment of the multi-level read-only memory device of the present invention.

Figure 2 is a one part component cross-sectional perspective view of a four-value ROM cell of Figure 1.

FIG. 3 is an equivalent circuit of the quaternary ROM cell shown in FIG. 2;

FIG. 4 shows a first example of a multi-value read-only memory device according to the present invention;
1 is a configuration diagram of a four-value ROM device as an embodiment.

5 is a partial view of a read circuit for surely and stably performing a read operation in the four-value ROM device shown in FIG. 4,
(A) is a circuit diagram, and (B) is an equivalent circuit thereof.

6 is an operation signal waveform diagram of the four-value ROM device shown in FIG.

FIG. 7 shows a second example of the multilevel read-only memory device according to the present invention.
1 is a configuration diagram of a four-value ROM device as an embodiment.

8 is an operation signal waveform diagram of the four-value ROM device shown in FIG. 7;

FIG. 9 is a configuration diagram of a conventional four-value ROM.

[Explanation of symbols]

 10, 10A ··· first dummy ROM cell array, 11 ··· first dummy word line driver circuit, 12 ··· first ROM cell array, 13 ··· first word line driver circuit, 14, 14A ··· 2 ROM cell array, 15 second word line driver circuit, 16 second dummy ROM cell array, 17 second dummy word line driver circuit, 20, 20A decoder circuit, 22 converter Circuits, CMP1 to CMP4, comparison circuits, SW1 to SW5, switch circuits.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 G11C 16/04 H01L 27/112

Claims (2)

(57) [Claims] A plurality of data storage transistors each having a channel length corresponding to multi-valued information; a plurality of reference transistors each having a different channel length; an output signal of a selected data storage transistor; possess a comparator for comparing the output signal, and a discrimination unit for discriminating a multi-level information stored in the selected data storage transistor based on the comparison result of the comparing unit, a plurality of reference transistors Each channel of
Length is the possible channel length of the data storage transistor
A multi-valued read-only memory device that is set to a length between adjacent ones . Wherein a plurality of comparison circuits for comparing the corresponding one output signal and an output signal and the plurality of reference transistors of the comparison section selected data storage transistors, the judgment unit is the more 2. The multi-value read-only memory device according to claim 1, wherein the multi-value information stored in the selected data storage transistor is determined based on the comparison result of the comparison circuit.