JP3111619B2 - Input signal processing device for comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator for comparing an input signal with a reference voltage signal and outputting a signal which is inverted according to the comparison result. , then until a predetermined time has elapsed, the input signal or the reference voltage signal is input to the comparator, an input signal
The present invention relates to an input signal processing device for a comparator that deviates in a direction in which a difference from a reference voltage signal increases .

[0002]

2. Description of the Related Art Conventionally, for example, a detection signal from a magnet pickup coil used for detecting a rotation speed, etc.
When shaping the waveform of an input signal that changes periodically, the input signal is compared with a reference voltage signal to determine whether or not the input signal is larger than the reference voltage signal. A comparator that generates a pulse signal is used.

[0003] In this type of comparator, when noise is added to an input signal, the output may fluctuate due to the noise. For this reason, in this type of comparator, when the output from the comparator is inverted, as disclosed in, for example, Japanese Patent Publication No. 1-18604, an input signal or a reference voltage signal is input for a predetermined time thereafter. Signal and base
To deviate in the direction where the difference from the quasi-voltage signal increases
Further, an input signal processing device for preventing erroneous determination due to noise is provided. In the following description, this specification
Then, as described above, the input signal or the reference voltage signal
This is called a “mask” and is used to input signals or reference voltage signals.
The time to deviate the signal is referred to as the "mask time",
The current or voltage for shifting the reference voltage
Current "or" mask voltage ".

When the input signal or the reference voltage signal is displaced after the inversion of the comparator output, if the time (mask time) is fixed, the frequency of the input signal (input frequency) becomes high. In the case of, the mask time becomes longer than the inversion period of the input signal, the phase of the output signal from the comparator and the input signal are shifted, and conversely, if the input frequency is low, the inversion period of the input signal However, the mask time becomes too short, and erroneous determination is likely to occur due to noise after the mask time has elapsed.

Therefore, conventionally, in this type of signal processing apparatus, as disclosed in Japanese Patent Application Laid-Open No. 58-188923, for example, by changing the mask time in accordance with the input frequency, good noise is always obtained. It is also considered that the removal characteristics and the phase characteristics can be obtained.

[0006]

However, when the mask time is changed in accordance with the input frequency as described above, for example, a signal from an engine speed sensor for detecting a speed ranging from several tens to 10,000 [rpm]. Under such conditions that the frequency of the input signal changes over a wide range, it is difficult to match the input frequency and the mask time in the entire frequency domain,
Conventionally, as shown in FIG. 7A, in the high frequency range (f> fmax) of the input signal, the mask time T M has to be saturated.

As a result, the high frequency region (f> f) of the input signal
max), there is a problem that the mask time TM becomes longer than the inversion period of the input signal, and the phase of the output signal from the comparator and the phase of the input signal are shifted. That is, for example, FIG. 8 shows that the reference voltage signal VTH
Represents a signal waveform when the input signal VIN is displaced in a triangular waveform relative to the input signal VIN. In this case, the masking time T M can be set according to the input frequency. .Ltoreq.fmax), as shown in FIG.
In the high frequency region (f> f1) of the input signal VIN where the phase of the input signal VIN and the output signal VHL can be matched, but the mask time T M cannot be set according to the input frequency, as shown in FIG. , Input signal VIN and output signal V
There is a problem in that the phase shift from HL and the higher the input frequency are, the larger the shift amounts Δt1 and Δt2 are.

In order to solve this problem, a circuit capable of setting the mask time according to the input frequency may be used even when the input frequency varies over a wide range. It is difficult. That is, for example, to set the mask time T M, the frequency-voltage converter (f
/ V converter) as shown by the dotted line in FIG.
It is conceivable that the f / V conversion characteristic is degraded so that the mask time is not saturated up to the high frequency region. However, in this case, the mask time T in the low frequency region of the input signal is
Since it becomes impossible to set M with high accuracy, a special circuit is required to improve the accuracy in the low frequency region.
It will be very costly. Therefore, in order to make the input signal processing circuit inexpensive, in order to maintain the accuracy of the mask time T M in the low frequency region of the input signal, FIG.
As shown by the solid line in (b), f / V saturated in the high frequency region
An f / V converter having conversion characteristics must be used, and the above problem cannot be solved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an input signal processing circuit for a comparator which can suppress a phase shift occurring in a high frequency region of an input signal and can be realized simply and at low cost. With the goal.

[0010]

That is, the present invention, which has been made to achieve the above object, compares an input signal that changes periodically with a reference voltage signal, and outputs a signal that is inverted according to the comparison result. When the output signal from the comparator is inverted, the input signal or the reference voltage signal input to the comparator is provided until a predetermined time elapses.
The difference between the input signal and the reference voltage signal
In the input signal processing device of the comparator,
And frequency detecting means for detecting the frequency of the input signal, in response to the frequency of the detected said input signal at said frequency detecting means, so as to be shorter the higher the frequency, the input
Time setting means for setting a time for excursion of the signal or the reference voltage signal, and when the frequency of the input signal detected by the frequency detection means is equal to or higher than a predetermined frequency,
As gist input signal processing apparatus of the comparator, characterized in that it and a time change rate changing means for changing the rate of change to a larger value with respect to the input signal frequency of the time set by the time setting means I have.

[0011]

In the input signal processing apparatus of the present invention configured as described above, the frequency detecting means detects the frequency of the input signal, and the time setting means responds to the detected frequency of the input signal by: The time to deviate the input signal or the reference voltage signal so that the higher the frequency of the input signal is, the shorter the time is.
Time) . When the frequency of the input signal detected by the frequency detecting means is equal to or higher than a predetermined frequency , the time change rate changing means sets the change rate of the mask time set by the time setting means with respect to the input signal frequency. To a larger value.

That is, in the present invention, the masking time is not only set in accordance with the frequency of the input signal as in the conventional device, but also when the frequency of the input signal becomes higher than a predetermined frequency. Increase the rate of change of time. For this reason, in the present invention, compared to the conventional device,
The mask time of the input signal in the high frequency region is shortened, and the phase shift between the input signal and the output signal is suppressed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a schematic configuration diagram illustrating a configuration of the entire input signal processing device provided in the comparator 2, and FIG. 2 is a time chart illustrating an operation thereof.

As shown in FIG. 1, an inverting input terminal (-) of a comparator 2 is connected to a rotation signal V from a magnet pickup coil 1 for detecting an engine speed via a resistor R1.
The non-inverting input terminal (+) of the comparator 2 is connected to an input terminal 4 for inputting IN and a reference voltage source 6 via a resistor R2.
It is connected to the. The signal from the magnet pickup coil 1 is supplied to a CR filter circuit 3 for noise removal.
Through the input terminal 4.

The comparator 2 employs a well-known Schmitt trigger for providing a hysteresis to the reference voltage signal input to the non-inverting input terminal (+) to determine the magnitude of the rotation signal VIN. As shown in a), the reference voltage VTH for comparing the magnitude with the rotation signal VIN changes every time the determination result is inverted. The output terminal of the comparator 2 is connected to an inverter 8. The comparator 2 performs a waveform shaping of the rotation signal VIN into a rectangular shape via the inverter 8 in FIG.
The detection signal VHL shown in (b) is output. Therefore, the detection signal VHL is generated when the rotation signal VIN is lower than the reference voltage VTH.
When the rotation signal VIN is higher than the reference voltage VTH, the signal goes high.

The detection signal VHL is transmitted to the engine control unit 5
The engine control device 5 controls the fuel injection amount, fuel injection timing, ignition timing, and the like according to the detection signal VHL. Each time the detection signal VHL is inverted, the input signal processing device outputs the rotation signal V in accordance with the change direction of the rotation signal VIN.
By increasing IN or the reference voltage VTH, the comparator 2
Is intended to accurately shape the waveform of the rotation signal VIN without being affected by noise superimposed on the rotation signal VIN. As shown in FIG. VfV , frequency detection means
And f / V converter 10 of, along with charging and discharging the capacitor C1 in synchronism with the inversion period of the detection signal VHL as shown in FIG. 2 (c), the charging and discharging currents IC1 f / V converter 10
Time setting means for controlling according to the output voltage VfV from the
And a terminal voltage V of the capacitor C1 charged and discharged by the control circuit 12.
C1 is limited to a predetermined range of VTH1 to VTH2, and the terminal voltage V
In accordance with the increase / decrease state of C1 (shown in FIG. 2D), the comparator 2
2 (g) by flowing a mask current IMH shown in FIG. 2 (e) and a mask current IML shown in FIG. 2 (f) into the inverting input terminal (-) and the non-inverting input terminal (+) of FIG. As shown, the rotation signal input to the comparator 2 (in other words,
Input signal) VIN and reference voltage (in other words, reference voltage signal
No.) and a mask current generating circuit 14 for increasing VTH.

As shown in FIG. 3A, the control circuit 12
A first constant current generating circuit 21 for generating a constant current I1 that changes at a predetermined rate of change α in accordance with the output voltage VfV from the f / V converter 10, and as shown in FIG. Converter 1
When the output voltage VfV from 0 is equal to or higher than the predetermined voltage VB,
A second constant current generating circuit 22 for generating a constant current I2 which changes at a predetermined change rate β according to the output voltage VfV.

Each of the constant current generating circuits 21 and 22 includes a PNP transistor TR having an emitter receiving a power supply voltage VCC.
1 is connected to the collector and the base of the PNP transistor TR1.
A current IT (= I1 + I2) flows through the first and second sides. Also, this PNP transistor TR1 has
The PNP transistor TR2 is connected so as to form a current mirror, so that currents IT and A.IT can be taken out from the multi-collector of the PNP transistor TR2.

Next, the current IT of the PNP transistor TR2
The side collector is the external terminal 1 to which the capacitor C1 is connected.
6, the mask current generating circuit 14, and the collector of the NPN transistor TR4 whose emitter is grounded. The collector of the current A.multidot.IT side of the PNP transistor TR2 is connected to the switch circuit 24 whose other end is grounded, and is connected to the NPN transistor TR4 so as to form a current mirror with the NPN transistor TR3.
Connected to the collector and base.

The switch circuit 24 detects the detection signal VHL
Operates when the detection signal VHL is at the high level, and turns off when the detection signal VHL is at the low level.
State. In the control circuit 12 configured as described above,
As shown in FIG. 3 (c), until the collector current IT of the PNP transistor TR1 becomes higher than the predetermined voltage VB of the output voltage VfV of the f / V converter 10, in other words, the frequency f of the rotation signal VIN is maintained at a predetermined frequency. Until the frequency fB or more, the output voltage VfV of the f / V converter 10 increases at a rate of change α corresponding to an increase in the output voltage VfV (that is, an increase in the frequency f of the rotation signal VIN). Is greater than or equal to a predetermined frequency fB, the rate of change γ (= α +
β). In FIG. 3, Vmax is f /
The upper limit value of the output voltage VfV corresponding to the maximum frequency fmax at which the V converter 10 can perform the f / V conversion of the rotation signal VIN is shown. The output voltage VfV of the f / V converter 10 exceeds this maximum frequency fmax. When the rotation signal VIN is input, it saturates,
Vmax.

When the detection signal VHL is at the high level, the switch circuit 24 is turned on, so that the NPN transistors TR3 and TR4 are turned off, and conversely, the detection signal VHL is at the low level. In this case, since the switch circuit 24 is turned off, the NPN transistors TR3 and TR4 are turned on, and a current A · IT flows through each of the transistors TR3 and TR4.

For this reason, as shown in FIG. 2C, when the detection signal VHL is at the high level, the PNP transistor T
When the current IT flows from R2 to the capacitor C1 side, the capacitor C1 is charged. Conversely, when the detection signal VHL is at the low level, the NPN transistor TR
The current of (A-1) IT flows to the side 4 and the capacitor C1
Is discharged.

Next, as shown in FIG. 4, the mask current generating circuit 14 generates a lower limit voltage VTH1 and an upper limit voltage VTH of the terminal voltage VC1.
Three voltage dividing resistors R11 to R13 for dividing the power supply voltage VCC to set TH2, the upper limit of the terminal voltage VC1 is limited to the upper limit voltage VTH2, and masking is performed when the terminal voltage VC1 increases due to charging of the capacitor C1. Current IMH to comparator 2
Of the rotation signal waveform shaping circuit 30 which flows into the inverting input terminal (-) of the
And the lower limit of the terminal voltage VC1 is limited to the lower limit voltage VTH1, and when the terminal voltage VC1 decreases due to the discharge of the capacitor C1, the mask current IML is changed to the non-inverting input terminal (+) of the comparator 2.
And a reference voltage waveform shaping circuit 32 for increasing the reference voltage waveform VTH of the comparator 2.

The rotation signal waveform shaping circuit 30 has a constant current generating circuit 34 for generating a constant current I3.
This constant current generating circuit 34 is connected to a PNP through a resistor R3.
Connected to the emitter of the transistor TR5,
The constant current I3 is connected to the emitter of the NP transistor TR6 and supplied to the transistors TR5 and TR6 in a divided manner.

The terminal voltage VC1 of the capacitor C1 is applied to the base of the PNP transistor TR5, and the collector and base of the NPN transistor TR7 whose emitter is grounded are connected to the collector. on the other hand,
The upper limit voltage VTH2 generated by the voltage dividing resistors R11 to R13 is applied to the base of the PNP transistor TR6, and the collector is connected to the anode of the diode D1 whose cathode is grounded.

Next, an NPN transistor TR8 forming a current mirror is connected to the NPN transistor TR7, and a collector and a base of a PNP transistor TR9 whose emitter receives the power supply voltage VCC are connected to the collector of the NPN transistor TR8. Further, a PNP transistor TR10 forming a current mirror is connected to the PNP transistor TR9. The collector of the PNP transistor TR10 is connected to a switch circuit 36 that is turned on when the detection signal VHL is at a high level. When the switch circuit 36 is turned on, a current flowing through the PNP transistor TR10 is output as a mask current IMH. Have been to be.

On the other hand, the rotation signal waveform shaping circuit 32 includes a constant current generating circuit 38 for generating a constant current I4, and the constant current generating circuit 38 includes an NPN transistor TR11.
And through a resistor R4, N
It is connected to the emitter of the PN transistor TR12 and controls so that the sum of the currents flowing from the transistors TR11 and TR12 becomes the constant current I4.

The terminal voltage VC1 of the capacitor C1 is applied to the base of the NPN transistor TR11, and the collector of the NPN transistor TR11 is connected to the cathode of a diode D2 whose anode receives the power supply voltage VCC. On the other hand, NPN
The base of the transistor TR12 has the above-mentioned voltage dividing resistor R
The lower limit voltage VTH1 generated by the transistors 11 to R13 is applied, and the collector is connected to the collector and the base of the PNP transistor TR13 whose emitter receives the power supply voltage VCC.

Next, a PNP transistor TR14 forming a current mirror is connected to the PNP transistor TR13.
Is connected to the collector of the PNP transistor TR14. When the detection signal VHL is at the low level, the detection signal VHL is received through the inverter 40.
The switch circuit 42 in a state is connected, and when the switch circuit 42 is turned on, a current flowing through the PNP transistor TR14 is output as a mask current IML.

In the mask current generating circuit 14 configured as described above, as shown in FIG. 2E, when the rotation signal waveform shaping circuit 30 charges the capacitor C1, its terminal voltage VC1 reaches the upper limit voltage VTH2. Mask time up to △
As shown in FIG. 2 (f), the reference voltage waveform shaping circuit 32 causes the terminal voltage VC1 to fall to the lower limit voltage VTH1 when the capacitor C1 is discharged, as shown in FIG. Mask time to reach △
The mask current I which decreases according to the terminal voltage VC1 by the amount of TM2
Generate ML.

As a result, the inverting input terminal (-) of the comparator 2
The mask time ΔT during which the mask current IMH is output from the rotation signal waveform shaping circuit 30 when the capacitor C1 is charged.
During M1, a voltage corresponding to the mask current IMH is added, and the non-inverting input terminal (+) of the comparator 2 receives the mask current IMH from the reference voltage waveform shaping circuit 32 when the capacitor C1 is discharged.
During the mask time ΔTM2 when ML is output, the mask current IML
Are added to each other, and the rotation signal VIN and the reference voltage VTH input to the comparator 2 are converted into the rotation signal VIN 'and the reference voltage VTH' shown in FIG. Be shaped.

As described above, in the input signal processing device of the comparator according to the present embodiment, the rotation signal VIN of the charging current IT and the discharging current (A-1) IT to the capacitor C1 is generated.
Is set to α until the frequency of the rotation signal VIN becomes higher than a predetermined frequency, and to γ (= α + β) when the frequency of the rotation signal VIN becomes higher than the predetermined frequency. The mask time {TM1,} until the terminal voltage VC1 of the capacitor C1 charged and discharged by the current changing at the rate α or γ changes from the lower limit voltage VTH1 to the upper limit voltage VTH2 or from the upper limit voltage VTH2 to the lower limit voltage VTH1.
During TM2, the waveforms of the rotation signal VIN and the reference voltage VTH input to the comparator 2 are shaped according to the terminal voltage VC1.

For this reason, each of the above mask times ΔTM1, ΔT
As shown in FIG. 5, M2 changes at a constant rate corresponding to the frequency f until the frequency f of the rotation signal VIN becomes equal to or higher than the predetermined frequency fB. The output signal VfV from the f / V converter 10 at fB or higher.
Until the frequency reaches the upper limit frequency fmax at which the saturation state is reached, the frequency changes at a larger change rate in accordance with the frequency f.

Therefore, according to the present embodiment, the rotation signal VIN
Can be shortened in the high frequency region where the frequency is equal to or higher than the predetermined frequency fB, compared with the conventional device. In the frequency region where the rotation signal VIN exceeds the maximum frequency fmax, the phase difference is determined by the comparator 2. , The waveform of the rotation signal VIN can be shaped.

In the above embodiment, the control circuit 12
Does not describe the specific configuration of the constant current generating circuits 21 and 22 merely as having the constant current generating circuits 21 and 22. However, the constant current generating circuits 21 and 22 of the control circuit 12 Can be more specifically configured as shown in FIG. 6, for example. Hereinafter, a specific circuit of the control circuit 12 shown in FIG. 6 will be described.

As shown in FIG. 6, this control circuit 12 includes:
In addition to the first and second constant current generating circuits 21 and 22, a constant current generating circuit 20 for generating a constant current flowing through each of the constant current generating circuits 21 and 22 is provided. The constant current generating circuit 20 includes a diode D20 having an anode receiving the power supply voltage VCC, a resistor R20 having one end connected to the cathode of the diode D20, and a resistor R2 having a collector and a base connected to the resistor R2.
0, and an NPN transistor TR20 whose emitter is grounded.
0 emitter current I20 is (VCC-VDD20-VBE20) / R
20 (where VD20: forward voltage of diode D20, VBE20: base-emitter voltage of transistor TR20, R20: resistance value of R20). Further, a current mirror circuit including an NPN transistor TR21 and a resistor R21 is connected to the NPN transistor TR20, and an emitter current I20 (for example, 200
μA) is reduced to I21 (for example, 50 μA) and taken out.

The collector of the NPN transistor TR21 is connected to the collector of the PNP transistor TR22, and the emitter of the NPN transistor TR21 is connected via a resistor R22.
PNP connected to the base of NP transistor TR22
It is connected to the collector and the base of the transistor TR23. These PNP transistors TR22, TR23,
The resistor R22 is connected to the PNP in the first constant current generation circuit 21.
The transistors TR24 and TR25 form a current mirror circuit. Therefore, the first constant current generating circuit 2
A constant current I21 flows through each of the collectors of the PNP transistors TR24 and TR25.

Next, the output voltage V from the f / V converter 10 is supplied to the first constant current generation circuit 21 via a resistor R23.
fV, and when this voltage VfV is lower than the predetermined voltage VA,
A PNP transistor TR26 is provided which is in the N state and grounds the collector of the PNP transistor TR24. At the connection point between the PNP transistor TR26 and the PNP transistor TR24, the NPN transistor TR whose collector is connected to the collector of the PNP transistor TR1 and whose emitter is grounded via the resistor R24.
27 bases are connected. The collector and the emitter of the NPN transistor TR27 are connected to the NPN transistor TR27, respectively.
The collector and the emitter of the transistor TR28 are connected, and the base of the NPN transistor TR28 is connected to the other collector of the PNP transistor TR24 and the emitter of the PNP transistor TR29 whose collector is grounded.

The base of the PNP transistor TR29 is grounded via a resistor R25,
It is connected to one collector of NP transistor TR25. The base of the PNP transistor TR1 which forms a current mirror circuit together with the PNP transistor TR2 is connected via a resistor R26 to a collector-grounded P-type transistor.
The emitter of the NP transistor TR30 is connected, and PN
The base of the PNP transistor TR30 is connected to the collector of the P transistor TR1.

In the first constant current generating circuit 21 thus configured, the output voltage V from the f / V converter 10
When fV is lower than the predetermined voltage VA, the NPN transistor TR27 is turned off, and the current value I1 flowing through the resistor R24 is reduced.
Is a constant current VA / R24 (where R24 is the resistance value of the resistor R24). Also, the output voltage V from the f / V converter 10
When fV exceeds a predetermined voltage VA, the NPN transistor TR
28 is turned off and the NPN transistor TR27 is turned on, so that the current value I1 flowing through the resistor R24 is VfV / R
24, which changes according to the output voltage VfV from the f / V converter 10 (that is, the frequency f of the rotation signal VIN). Further, the output voltage VfV from the f / V converter 10 increases,
Maximum voltage Vmax (= VCC-VBE1-VBE30-VCE27, where VBE1, VBE30: PNP transistors TR1, TR
30 (base-emitter voltage, VCE27: collector-emitter voltage of the NPN transistor TR27), the PNP transistor TR26 turns off,
Since the emitter of the NPN transistor TR27 is fixed at Vmax, the current I1 flowing through the resistor R24 is
Is Vmax / R24.

Next, the second constant current generating circuit 22 has a collector and a base connected to the resistor R of the first constant current generating circuit 21.
24, a resistor R27 having one end connected to the emitter of the NPN transistor TR31, a resistor R28 having one end connected to the other end of the resistor R27, and the other end grounded; Is connected to the collector of the PNP transistor TR25 in the first constant current generating circuit 21 and the other end is grounded;
The base is connected to a connection point between the resistor R29 and the collector of the PNP transistor TR25, and the emitter is connected to the resistor R2.
And an NPN transistor TR32 whose collector receives the power supply voltage VCC at the ground.

In the second constant current generating circuit 22 configured as described above, the output voltage V from the f / V converter 10
When fV is lower than the predetermined voltage VB, the voltage between the base and the emitter of the NPN transistor TR31 is small.
The N transistor TR31 is turned off, and the resistor R
The current I2 flowing through 28 becomes "O". However, f / V
When the output signal VfV from the converter 10 exceeds a predetermined voltage VB, the emitter of the NPN transistor TR31 and the NPN transistor
Between the emitter of the transistor TR32 and (VfV-V
B), a difference voltage of (VfV−
A current I2 of VB) / R5 flows. When the output voltage VfV from the f / V converter 10 exceeds the maximum voltage Vmax,
Since the base voltage of the NPN transistor TR31 is fixed at Vmax, the resistor R28 has (Vmax-VB) /
A constant current I2 of R5 flows.

As a result, the collector current IT of the PNP transistor TR1 has a current value I1 flowing through the first constant current generating circuit 21 until the output voltage VfV of the f / V converter 10 becomes higher than the predetermined voltage VB. And the f / V converter 10
Is less than VB and less than Vmax, the first
Is the sum of the current value I1 flowing through the constant current generating circuit 21 and the current value I2 flowing through the second constant current generating circuit 22, and as described above, the frequency of the rotation signal VIN of the charging / discharging current of the capacitor C1. When the rate of change with respect to f is less than the predetermined frequency fB,
It changes with the above cases.

In the control circuit 12 shown in FIG. 6, the switch circuit 24 is constituted by an NPN transistor TR33 whose emitter is grounded, and the detection signal VHL is at the high level by receiving the detection signal VHL at its base. At this time, the NPN transistor TR33 is turned on,
The capacitor C1 is charged with the charging current IT, and the detection signal VHL
Is low level, the NPN transistor TR33
Turns off and discharges the capacitor C1 with the discharge current (A-1) I
It is designed to discharge at T.

Although the specific circuit of the control circuit 12 has been described above, the control circuit 12 and the mask current generating circuit 14 can have various configurations without departing from the gist of the present invention. For example, in the above embodiment,
A description has been given of the case where the waveforms of the rotation signal VIN and the reference voltage VTH are shaped by flowing the mask currents IMH and IML into the input terminals of the comparator 2. However, in order to prevent erroneous determination due to noise superimposed on the rotation signal VIN. Indicates that each time the detection signal VHL from the comparator 2 is inverted , the rotation signal VIN and the reference
The rotation signal VIN or the reference
Since the voltage VTH may be shifted, a mask current may be applied to one input terminal of the comparator 2 in a different direction each time the detection signal VHL from the comparator 2 is inverted.

In the above embodiment, the mask currents IMH, IMH
Although the ML is gradually decreased with the passage of time, the present invention adds a preset mask voltage to the rotation signal VIN and the reference voltage VTH during the mask times ΔTM1 and ΔTM2. It is applicable even if it is set as described above.

Further, in the above embodiment, the output of the comparator 2 is configured to be output via the inverter 8.
For example, the rotation signal VIN is supplied to the non-inverting input terminal (+) of the comparator 2.
And a resistor R2 is connected to the inverting input terminal (−) of the comparator 2.
If the reference voltage source 6 is connected via the above, the same detection signal VHL as described above can be obtained without using the inverter 8.

[0048]

As described above, in the input signal processing apparatus of the present invention, when the frequency of the input signal is equal to or higher than the predetermined frequency, the rate of change of the mask time with respect to the input signal frequency is changed to a large value. I am trying to do it.
Therefore, according to the present invention, the mask time in the high frequency region where the input signal is equal to or higher than the predetermined frequency can be shortened as compared with the conventional device. The input device can shape the input signal without causing a phase shift. In the present invention, the mask time in the high frequency region of the input signal is not made to correspond to the frequency of the input signal, but the frequency characteristic of the mask time in the high frequency region is changed. it can.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration of an entire input signal processing device according to an embodiment.

FIG. 2 is a time chart showing an operation of the input signal processing device shown in FIG.

FIG. 3 is an explanatory diagram illustrating charge / discharge characteristics of the capacitor C1 shown in FIG.

FIG. 4 is an electric circuit diagram showing a circuit configuration of a mask current generation circuit 14 shown in FIG.

FIG. 5 is an explanatory diagram illustrating characteristics of a mask time corresponding to a frequency of a rotation signal VIN.

6 is an electric circuit diagram showing a specific configuration of the control circuit shown in FIG.

FIG. 7 is an explanatory diagram illustrating a mask time characteristic and an f / V conversion characteristic with respect to an input frequency of a conventional device.

FIG. 8 is an explanatory diagram showing output characteristics of a comparator according to a conventional device.

[Explanation of symbols]

2 ... Comparator 6 ... Reference voltage source 8 ... Inverter
DESCRIPTION OF SYMBOLS 10 ... f / V converter 12 ... Control circuit 14 ... Mask current generation circuit 21 ... First constant current generation circuit 22 ... Second constant current generation circuit 24,36,42 ... Switch circuit 30 ... Rotation signal waveform shaping circuit 32: Reference voltage waveform shaping circuit 20, 34, 38 ... Constant current generating circuit

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroyuki Ban 1-1-1 Showa-cho, Kariya-shi, Aichi, Japan Inside Denso Corporation (72) Inventor Tomohisa Yamamoto 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Denso Corporation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 5/08

Claims (1)

(57) [Claims] 1. A comparator for comparing a periodically changing input signal with a reference voltage signal and outputting a signal which is inverted according to the comparison result, wherein the output signal from the comparator is inverted. Then, at a prescribed time
Until elapse between an input signal inputted to the comparator
Alternatively, the reference voltage signal is
In an input signal processing device for a comparator, which deviates in a direction in which the difference increases, a frequency detecting means for detecting a frequency of the input signal, and a frequency corresponding to the frequency of the input signal detected by the frequency detecting means. , so as to be shorter the higher the frequency, the upper fill
And <br/> between setting means when setting the time to offset the force signal or reference voltage signal, when the frequency of the detected input signal is equal to or higher than a predetermined frequency set in advance by the frequency detecting means, the input signal processing apparatus of the comparator, characterized in that it and a time change rate changing means for changing the rate of change to a larger value with respect to the input signal frequency of the time set by the time setting means.