JP3109168B2 - Digital video signal recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording and reproducing digital video signals, and more particularly to a digital VTR using a rotary head and a magnetic tape.

[0002]

2. Description of the Related Art In a conventional analog VTR, a pair of magnetic heads are attached to a rotating drum at an angular interval of 180 °, and a magnetic tape is wound around the peripheral surface of the drum in a range of about 180 °. The magnetic tape is fed at a constant speed, the magnetic head scans the magnetic tape alternately, and video signals are recorded as oblique tracks. As described above, since the tape winding angle is set to about 180 °, the periods in which the magnetic head scans the tape do not temporally overlap. Therefore, it is sufficient to provide one system of recording and reproducing circuits.
The circuit scale does not increase.

Recently, in a digital VTR which records and reproduces a video signal in the form of a digital signal, since a large amount of data is required for the digital video signal, a plurality of tracks are generally scanned by one scanning of a magnetic head. A multi-channel method of forming simultaneously is adopted. Regarding the digital VTR, a comparison is made between a case where the tape winding angle is set to 180 ° and a case where the tape winding angle is set to 270 °. As an example, it is assumed that data of 600 Mbps is recorded by a magnetic head having a total of eight channels opposed to four channels. Each parameter in this case can be calculated as follows.

As described above, when the winding angle is increased, the drum diameter can be reduced. This makes it possible not only to reduce the size and weight of the device, but also to reduce spacing loss and tape damage due to a decrease in relative speed. Of course, the mounting of the movable head is facilitated by the reduction of the centrifugal force. Further, since the recording rate is reduced, the efficiency of the rotary transformer and the magnetic head is increased, which is advantageous for high-density recording. A conventional digital VTR having a winding angle of 270 ° will be described. FIG. 5 shows a circuit configuration for recording. A / D converters 1, 2, and 3 convert a luminance signal Y and color difference signals PB and PR, which are components of a color video signal, into digital signals. A / D
The sampling clock CK1 supplied to the converter 1 is
For example, the frequency Fs is 37.5 MHz, and the frequency of the sampling clock supplied to the A / D converters 2 and 3 is そ の of the frequency. Therefore, the A / D converter 2
And the data amount of the digital chrominance signal from 3 is half that of the luminance signal. The sampling rate of the data obtained by summing the digital data from the A / D converters 1, 2, and 3 is 2Fs.

[0005] Output signals of the A / D converters 1, 2, and 3 are supplied to a head interleave circuit 4. As shown in FIG. 6, eight magnetic heads 14A to 14H are mounted on a drum 13 rotating at 150 Hz (5 times the frame frequency). On the peripheral surface of the drum 13, the magnetic tape 1
5 is wound at a winding angle θ (eg, θ = 270 °). The magnetic heads 14A, 14B, 14C and 14D are arranged close to each other, and four tracks are simultaneously formed on the magnetic tape 15 by these four magnetic heads. Four magnetic heads 14E to 14H are attached to the drum 13 in close proximity to the magnetic heads 14A to 14D at an angular interval of 180 °. Magnetic heads 14E-14
H causes four tracks to be formed on the magnetic tape 15 at the same time. Although not shown, the magnetic tape 15 is fed at a constant speed by a tape feed mechanism.

[0006] The head interleave circuit 4 in FIG.
In order to form data to be recorded by each magnetic head, the digital component signal is distributed to eight channels of A to H signals. In FIG. 7, as indicated by S1, the output signal of this head interleave circuit 4 is
This is channel data, and the sampling frequency of each channel is (2Fs / 8 = 1 / 4Fs). The signal of channel A is supplied to the outer-code encoder 5. As a countermeasure against errors that occur during the recording and reproduction processes, data is error-correction-coded by both the outer code and the inner code. More specifically, an outer code is encoded in the vertical direction of a matrix of a predetermined amount of data, and an inner code is encoded for each sync block in the horizontal direction.

[0007] Output data of the encoder 5 is supplied to a shuffling circuit 6. The shuffling circuit 6 performs shuffling for rearranging the data of one channel in one field in an order different from the original order, and is configured by a memory. Shuffling prevents time-continuous data from becoming an error due to a burst error, and enables good error correction. The write clock CKW and the read clock CKR are supplied to the shuffling circuit 6, and desired shuffling is performed by controlling the address of the memory. At the same time, the frequency of the clock CKW is set to 1 / 4Fs, and the frequency of the clock CKR is set to 1 / 3Fs. As a result, the output data of the shuffling circuit 6 is compressed on the time axis to ／ of the input data. Further, the reading of data from the shuffling circuit 6 coincides with the phase at which the magnetic head of the corresponding channel A records data on the magnetic tape.

[0008] The output signal of the shuffling circuit 6 is supplied to an ID adding circuit 7 and an ID signal for control is added. I
The output signal of the D addition circuit 7 is supplied to the inner code encoder 8, and the inner code is encoded. The output signal of the inner code encoder 8 is supplied to the sink addition circuit 9. The recording data is divided by a sync block, and video data, parity of an error correction code, and an ID signal in the sync block are encoded by an inner code. Record data having a sync block structure is generated from the sync addition circuit 9, and the record data is supplied to the channel encoder 10. The channel encoder 10 performs channel encoding for reducing a DC component. The output signal of the channel encoder 10 is supplied to the parallel / serial conversion circuit 11. The parallel / serial conversion circuit 11 supplies serial recording data. Although not shown, the recording data is supplied to the magnetic head 14A via a recording amplifier.

[0009] As shown in broken lines 12B to 12H, the circuit configuration relating to channel A from the outer code encoder 5 to the parallel / serial conversion circuit 11 is the same as that of the other B to H.
For each channel. The recording data from the blocks 12B to 12H is transferred to the magnetic head 14B.
To 14H via a recording amplifier. The shuffling circuit 6 and the shuffling circuits in the circuit blocks 12B to 12H compress the time axis and read data from the memory to match the recording phase of the corresponding magnetic head. Therefore, the shuffling circuit 6
7 is generated at the output of the shuffling circuit of each of the circuit blocks 12B, 12C, and 12D, and the circuit blocks 12E, 12F, 12G,
In the output of each shuffling circuit of 12H, FIG.
Medium data S3 is generated.

In FIG. 7, T is the period T of one rotation of the drum 13 (= 1/150 second), and the winding angle θ is 2
Since the angle is set to 70 degrees, the channels A to 14D are scanned while the magnetic heads 14A to 14D scan the magnetic tape 15.
D is recorded as four tracks, and then during a period in which the magnetic heads 14E to 14H are scanning the magnetic tape 15 with a delay of 1 / 2T, the recording data of channels E to H is recorded as four tracks. Be recorded.

A conventional reproducing circuit for reproducing the data recorded as described above will be described with reference to FIG. Channel A is provided by magnetic heads 14A to 14H.
The reproduction data of .about.H are supplied to a channel code decoder via a reproduction amplifier, not shown. The reproduced data of channel A from the channel code decoder is PLL2.
1 is supplied. The PLL 21 extracts a clock necessary for processing of the reproduction circuit from the reproduction data. The output signal of the PLL 21 is supplied to the serial / parallel conversion circuit 22. series/
The output signal of the parallel conversion circuit 22 is a TBC (time axis compensator)
23, and the time axis fluctuation in the reproduction data is removed.

The output signal of the TBC 23 is
4 for error correction by the inner code. The output signal of the decoder 24 is supplied to the deshuffling circuit 25. The deshuffling circuit 25 is configured by a memory, and is supplied with a write clock CKW and a read clock CKR. The frequency of the clock CKW is 1 / 3Fs, which is equal to the reproduction data and the clock rate, and the frequency of the clock CKR is 1 / 4Fs.
By the address control, the deshuffling circuit 25
The shuffling at the time of recording is returned to the original arrangement. At the same time, a time base expansion process is performed according to the clock frequency ratio. Further, by controlling the read phases of the channels A to D, data of eight channels in parallel is formed.

An output signal of the deshuffling circuit 25 is supplied to an outer code decoder 26, where an error correction process using an outer code is performed. The output signal of the outer code decoder 26 is supplied to a head deinterleave error correction circuit 28.
Supplied to In this circuit 28, data of eight channels is decomposed into a luminance signal and two color difference signals, and an error which cannot be corrected by the inner code and the outer code is corrected. D / A converters 29, 30 and 31 are connected to the circuit 28, and the digital luminance signal is converted into an analog luminance signal Y by the D / A converter 29, and the digital chrominance is converted by the D / A converters 30 and 31. The signals are converted into analog color difference signals PB and PR, respectively.

The same configuration as that of the reproduction circuit from the PLL 21 to the outer code decoder 26 for the channel A is provided for the other channels B to H, as shown by broken lines 27B to 27H in FIG. At the output of the serial / parallel conversion circuit 22 and the serial / parallel conversion circuits in the circuit blocks 27B to 27H, reproduced data indicated by S4 in FIG. 9 is generated. The reproduction data S4 corresponds to the reproduction phase of the magnetic head. Also, the outer code decoder 2
At the output of No. 6 and the output of the outer code decoder in the circuit blocks 27B to 27H, reproduced data of 8 channels in parallel of channels A to H as shown by S5 in FIG. 9 is generated.

[0015]

SUMMARY OF THE INVENTION The above described digital VT
In R, the winding angle θ of the magnetic tape 15 is set to 270 °, which is larger than 180 °. In a digital VTR,
When the recording wavelength is constant and the number of rotations of the drum and the number of recording heads are specified, the diameter of the drum 13 can be reduced or the track length can be increased by increasing θ to more than 180 °. Can be lowered.
However, a section in which the scanning of the magnetic head overlaps occurs. As a result, as shown in FIG. 5 or FIG. 8, it is necessary to provide a number of signal processing systems equal to the number of magnetic heads (channels) in parallel. And the recording circuit,
There is a problem that the circuit scale of the reproducing circuit becomes large.

It is therefore an object of the present invention to provide a digital video signal recording / reproducing apparatus capable of reducing the size of a recording circuit and a reproducing circuit even when a tape winding angle is large.

[0017]

SUMMARY OF THE INVENTION The present invention provides a magnetic tape which is wound around the peripheral surface of a rotating drum by an N number of magnetic heads attached to the rotating drum within an angular range where scanning of the magnetic head overlaps. In a recording apparatus for recording a digital video signal, a circuit (44) for distributing an input digital video signal to a number of channels smaller than the number N of heads, and an encoder (45, 48) and the digital recording processing circuits (53A to 53D) and the digital recording processing circuits (53A to 53D), the number of which is equal to the number N of the heads, and which matches the respective recording phases of the magnetic heads. Readout from there,
A memory circuit for outputting N recording signals (51A,
51E) for recording a digital video signal.

According to the present invention, a digital video signal is transmitted from a magnetic tape wound around the peripheral surface of the rotating drum by an N number of magnetic heads attached to the rotating drum in an angular range where scanning of the magnetic head overlaps. In a reproducing apparatus for reproduction, reproduction data of a magnetic head is supplied, and the reproduction data is time-axis-compressed so as to remove time-axis fluctuations of the reproduction data and to remove temporal overlap of the reproduction data. TBC for
(63) and a circuit (7) that combines the output data of the TBC (63) and forms reproduced data less than the number N of heads.
2A to 72D) and the combining circuits (72A to 72D), respectively, and the error correction code decoders (64, 6).
6) Digital playback signal processing circuits (73A to 73)
D) for reproducing a digital video signal.

[0019]

According to the present invention, a recording video signal is distributed to a number of channels smaller than the number of heads, and digital recording processing circuits of the same number as the number of channels are provided. Form recording data. Therefore, the number of digital recording processing circuits can be reduced, and the circuit scale can be reduced as compared with providing a recording processing circuit having the same number of channels as the number of heads.

Further, according to the present invention, reproduced data from a plurality of magnetic heads are supplied to the TBC, and the TBC removes the time-axis fluctuation and the temporal overlap of the reproduced data. . Therefore, it is possible to combine with reproduction data of a channel smaller than the number of magnetic heads, and to perform reproduction processing such as error correction after the combination. Therefore, the circuit scale can be reduced as compared with providing a reproduction processing circuit having the same number of channels as the number of heads.

[0021]

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as in FIG.
Eight magnetic heads are mounted on a drum rotating at 0 Hz, and four magnetic heads are provided close to each other, and an angular interval of 180 ° is provided between them. The magnetic tape is attached to the peripheral surface of the drum by θ (= 270 °).
Is wrapped around.

FIG. 1 shows the configuration of the recording circuit of this embodiment. The luminance signals Y,
The color difference signals PB and PR are respectively converted into digital signals. The frequency of the sampling clock CK1 is Fs (for example, 37.5 MHz), and the frequency of CK2 is 1 / 2F.
s. The digital component signal is supplied to the head interleave circuit 44. The head interleave circuit 44 generates four time-division multiplexed signals (clock rate is 1/2 Fs). One is A and E
Is a time-division multiplexed signal alternately containing samples (or several samples) recorded as channels. Others are time division multiplexed signals on channels B and F, C
And G channel time division multiplexed signals, and D and H channel time division multiplexed signals. The time-division multiplexed channels correspond to pairs of magnetic heads facing each other at an angular interval of 180 °. S11 in FIG. 2 indicates four time division multiplexed signals generated from the head interleave circuit 44. Although video data is continuously input, FIG. 2 shows processing of only video data supplied in the cycle T for simplicity.

The time-division multiplexed signals of the A and E channels are supplied to the shuffling circuit 4 via the outer code encoder 45.
6. In order to correct an error that occurs in the process of recording and reproduction, an error correction code using both an outer code and an inner code is used. Shuffling circuit 46
Performs shuffling to rearrange the order of data within, for example, one field in order to disperse burst errors. The shuffling circuit 46 is configured by a memory, and the write clock CKW and the read clock CKR are supplied to the shuffling circuit 46. These clocks C
The frequencies of KW and CKR are equally 1/2 Fs. In the shuffling circuit 46, a signal that has been time-division multiplexed on a sample basis is input to the channel A in the first half of the period T.
Is converted to a signal S12 in which data recorded as channel E exists, and data recorded as channel E exists in the latter half thereof.

An ID signal for control is added to an output signal of the shuffling circuit 46 by an ID adding circuit 47. The output signal of the ID addition circuit 47 is the inner code encoder 4
8 and the inner code is encoded. The output signal of the inner code encoder 48 is supplied to a sync adding circuit 49, and a sync signal is added for each sync block. The data having the structure of the sync block from the sync adding circuit 49 is supplied to the channel encoder 50, and the channel is encoded.

The output signal of the channel encoder 50 is F
It is supplied to the IFO memories 51A and 51E. The FIFO memories 51A and 51E have parallel / serial conversion circuits 52A,
52E are respectively connected. The recording data for the magnetic head of channel A is generated from the parallel / serial conversion circuit 52A, and the recording data for the magnetic head of channel E is generated from the parallel / serial conversion circuit 52E. The frequency of the write clock W for the FIFO memories 52A and 52E is Ｆ Fs, and the frequency of the read clock R is Ｆ Fs. Also, FI
The data of the channel A in the first half of the cycle T is written to the FO memory 51A, and the data of the channel E in the second half of the cycle T is written to the FIFO memory 51E. Therefore, by the FIFO memories 52A and 52E,
Time axis expansion is performed, and data existing in a 1 / 2T section is expanded to data existing in a 3 / 4T section.

As shown by broken lines in FIG. 1, the same circuit blocks 53B, 53C, 53 as the circuit configuration 53A from the outer code encoder 45 to the channel encoder 50 described above.
D is also provided for the other three output signals from the head interleave circuit 44. Furthermore, circuit blocks 54B, 54F, 54C, 54G, 54D, 54H similar to the serial connection 54A, 54E of the FIFO memory and the parallel / serial conversion circuit are provided for these circuit blocks.
Are connected to each other, and recording data of each of the channels B to H is generated from each circuit block. The recording data is supplied to eight magnetic heads via recording amplifiers, though not shown.

As shown in FIG.
From each shuffling circuit of 53D, a signal S12 including data in which two channels are allocated to the first half and the second half of the cycle T of one rotation of the magnetic head is read. Then, from each of the FIFO memories in the circuit blocks 54A, 54B, 54C, and 54D, the recording data S of the channels A, B, C, and D which are expanded in the time axis and exist in the 区間 T section are provided.
13 is read. The section of the recording data S13 is
The recording phases for scanning the magnetic tape by the magnetic heads of the channels A to D coincide with each other, and data of these channels are simultaneously recorded on the magnetic tape as four tracks.

Similarly, the data of the channels existing in the latter half of the cycle T are also stored in the circuit blocks 54E, 54F, 54G,
Channels E, F, G, and H, which are expanded in time axis by each FIFO memory in 54H and exist in a section of 3 / 4T
Is generated. The section of this recorded data is
The magnetic heads of the channels E to H coincide with the recording phase for scanning the magnetic tape, and the data of these channels are simultaneously recorded on the magnetic tape as four tracks. As can be understood from FIG. 1, the recording processing circuit has four channels (53A to 53D) from the outer code encoder 45 to the channel encoder 50 in parallel, and
The circuit scale can be made smaller than in the conventional configuration in which channel circuit systems are provided in parallel. The connection point of the FIFO memory is preferably after the inner code encoder 48,
It is not limited to the configuration shown in FIG.

Next, with reference to FIGS. 3 and 4, the reproducing circuit of this embodiment will be described. Reproduction data of channels A to H from each of the eight magnetic heads is supplied to a channel code decoder via a reproduction amplifier, though not shown. The reproduction data of channel A from the channel code decoder is supplied to the PLL 61. The PLL 61 extracts a clock necessary for the processing of the reproducing circuit from the reproduced data. An output signal of the PLL 61 is transmitted to a TBC (time axis compensator) 6 via a serial / parallel conversion circuit 62.
3 is supplied.

The TBC 63 is composed of a memory, in which data is written with a clock having a frequency of 1/3 Fs synchronized with reproduction data, and data is read with a stable clock of 1/2 Fs. As a result, the time axis fluctuation in the reproduction data is removed. At the same time, in the TBC 63, the time axis of the data is compressed to 2/3 according to the clock frequency ratio. Accordingly, 3 in the cycle T of one rotation of the magnetic head.
The reproduction data of the channel A existing in the section of / 4T is compressed to the length of the section of 1 / 2T. Furthermore, TB
The timing of reading data from C63 is delayed by T time with respect to input data. The output signal of the TBC 63 is supplied to the switching circuit 72A.

The above-mentioned PLL 61 and serial / parallel conversion circuit 6
The circuit configuration 67A including the TBC 2 and the TBC 63 is provided for the reproduction data of the other channels B to H, respectively, as shown by the dashed blocks 67B to 67H in FIG. Reproduction data of the channel E from the TBC in the circuit block 67E is supplied to the switching circuit 72A. The switching circuit 72B includes a circuit block 67.
Reproduction data of channels B and F from B and 67F are supplied. Switching circuit 72C includes channels C and G from circuit blocks 67C and 67G.
Is supplied. The reproduction data of channels D and H from the circuit blocks 67D and 67H is supplied to the switching circuit 72D. These switching circuits 72A to 72D are for alternately selecting reproduction data of two channels input thereto and generating reproduction data of one channel.

The reproduced data in which the channels A and E generated by the switching circuit 72A are located in the first half and the second half of the period T, respectively, is supplied to the inner code decoder 64, where the error is corrected by the inner code. The output signal of the decoder 64 is supplied to the deshuffling circuit 65. The deshuffling circuit 65 is composed of a memory, and has a write clock CKW and a read clock CKR.
Are supplied. The clocks CKW and CKR have a frequency of 1/2 Fs. By the address control, the deshuffling circuit 65 performs a process of returning the shuffling at the time of recording to the original arrangement. At the same time, time-division multiplexed data in which the data of the two channels A and E are alternately positioned on a sample basis is formed.

An output signal of the deshuffling circuit 65 is supplied to an outer code decoder 66, where an error correction process using an outer code is performed. An output signal A / E of the outer code decoder 66 is supplied to a head deinterleave error correction circuit 68. In this circuit 68, four-channel time-division multiplexed data is decomposed into a luminance signal and two color difference signals, and an error that cannot be corrected by the inner code and the outer code is corrected. D / A converters 69, 70 and 71 are connected to the circuit 68, the digital luminance signal is converted into an analog luminance signal Y by the D / A converter 69, and the digital chrominance is converted by the D / A converters 70 and 71. The signals are converted into analog color difference signals PB and PR, respectively.

In FIG. 3, a circuit block 7 indicated by a broken line
3B, 73C and 73D are the above-described inner code decoder 64,
The circuit configuration is the same as the circuit configuration 73A including the deshuffling circuit 65 and the outer code decoder 66, and is connected to the switching circuits 72B, 72C, and 72D, respectively. The circuit block 73B generates a time-division multiplexed signal B / F in which reproduction data of channels B and F are alternately positioned in sample units, and the circuit blocks 73C and 73D.
, Time-division multiplexed signals C / G and D / H are similarly generated. These time-division multiplexed signals are supplied to a head interleave error correction circuit 68, and a luminance signal and a color difference signal are generated from the circuit 68 as described above.

In the above-described reproducing circuit, the reproduced data S14 in FIG. 4 is generated at the output of each of the serial / parallel conversion circuits of the circuit blocks 67A to 67H. In this case,
At each output of the switching circuits 72A to 72D, as shown in FIG. 4, reproduced data in which reproduced data of two channels are respectively located in the first half and the second half of the period of T is generated. Further, the circuit blocks 73A to 73A
At the output of each outer code decoder of 3D, a time-division multiplexed signal in which two channels are alternately positioned in sample units is generated. Note that the magnetic head reproduces data even after the operation shown in FIG. 4, but FIG. 4 shows only processing of video data reproduced by one rotation of the drum for simplicity.

In the reproducing circuit of this embodiment, a processing circuit for four channels may be provided on the output side of the switching circuits 72A to 72D, and the circuit scale is smaller than that required for a processing circuit of eight channels. Can be significantly reduced.

[0037]

According to the present invention, the magnetic tape is wound around the peripheral surface of the rotating drum over 180 ° for the purpose of reducing the diameter of the drum and reducing the relative speed. There is a temporal overlap in the periods. However, according to the present invention, by using the time axis conversion processing, the number of recording or reproducing circuit systems may be smaller than the number of magnetic heads, and the scale of these circuits can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration for recording according to an embodiment of the present invention.

FIG. 2 is a timing chart used for describing an operation at the time of recording.

FIG. 3 is a block diagram showing a circuit configuration for reproduction according to an embodiment of the present invention.

FIG. 4 is a timing chart used for describing an operation at the time of reproduction.

FIG. 5 is a block diagram showing a circuit configuration for recording a conventional digital VTR.

FIG. 6 is a schematic diagram showing a head arrangement of a digital VTR.

FIG. 7 is a timing chart used to describe an operation at the time of recording of a conventional VTR.

FIG. 8 is a block diagram showing a circuit configuration for reproducing a conventional digital VTR.

FIG. 9 is a timing chart used to describe an operation at the time of reproduction of a conventional VTR.

[Explanation of symbols]

 44 head interleave circuit 46 shuffling circuit 51A, 51E FIFO memory 63 TBC 72A-72D switching circuit 65 deshuffling circuit

Claims (2)

(57) [Claims] 1. A digital video signal is recorded on a magnetic tape wound by an N number of magnetic heads attached to a rotating drum on a peripheral surface of the rotating drum in an angular range where scanning of the magnetic head overlaps. Means for distributing an input digital video signal to a number of channels smaller than the number of heads N, digital recording processing means connected to each of the channels and including an encoder for an error correction code, The magnetic head is coupled to the processing means, and is read out therefrom in a number equal to the number of heads N so as to match the respective recording phases of the magnetic heads.
A digital video signal recording device comprising: a memory means for outputting a plurality of recording signals. 2. A digital video signal is reproduced from a magnetic tape wound around the peripheral surface of the rotating drum by an N number of magnetic heads attached to the rotating drum in an angular range where scanning of the magnetic head overlaps. In the reproducing apparatus, the reproduction data of the magnetic head is supplied, and the reproduction data is time-axis-controlled so as to remove the time-axis fluctuation of the reproduction data and to remove the temporal overlap of the reproduction data. Memory means for compression; and output data of the memory means are synthesized, and the number of heads N
A digital video signal reproducing apparatus comprising: means for forming a smaller number of reproduced data; and digital reproducing signal processing means including an error correction code decoder respectively coupled to the synthesizing means.