JP3108454B2 - ID filtering method in multiplex transmission - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called CSMA / CD (Carr
TECHNICAL FIELD The present invention relates to a multiplex transmission system using an ier Sense Multiple Access / Collision Detection (transmission) transmission system, and particularly to an ID filtering system in multiplex transmission of received data.

[0002]

2. Description of the Related Art Conventionally, in this type of multiplex transmission system, one of a plurality of terminals (multiplex nodes) commonly connected to a multiplex transmission line (multiplex bus) composed of a pair of electric wires or the like is transmitted to a destination. Data is transmitted for each frame having an address, and when the multiplex node specified by the destination address receives the frame normally, the specified multiplex node returns an acknowledgment signal (ACK signal) following the frame. A multiplex transmission scheme of the distributed control type using the CSMA / CD scheme has been proposed.

FIG. 4 is a configuration diagram showing a schematic configuration of an automobile multiplex transmission system using the CSMA / CD system. In the figure, a plurality of multiplex nodes, for example, a front multiplex node FN, a combination switch multiplex node CS, a meter multiplex node MT, and a rear multiplex node RN are connected to a multiplex bus MB composed of twisted pair wires. For example, a front turn right signal lamp 6, a front turn left signal lamp 7, a front small lamp 8, and a horn 9 are connected to the front multiplex node FN. The combination switch multiplex node CS
For example, a turn light switch 10, a turn left switch 11, a small lamp switch 12, a horn switch 13, and a headlamp high beam switch 14 are connected. For example, a turn right indicator 15, a turn left indicator 16,
The headlamp high beam indicator 17 is connected. The rear multiplex node RN includes, for example, a rear turn light signal lamp 18, a rear turn left signal lamp 19, and a tail lamp 20 (the tail lamp 2).
0 is lit when the small lamp switch 12 is on)
Is connected. In the above-described multiplex transmission system for vehicles, vehicle driving information is transmitted for each frame F having a configuration as shown in FIG.

[0004] Here, the frame F is an SD (Start Delimit).
er) The frame has a code, a priority code, a frame ID code, data, and a check code (error detection code). SD code is frame F
Is a specific code indicating the start of The priority code is a code used for controlling the priority. When a plurality of multiplex nodes transmit data at the same time and the data collides on the multiplex bus MB, the priority code indicates which data is transmitted with priority. This is to determine the order of priority for instructing. When the above-mentioned data collision occurs, data having a higher priority is transmitted first. The frame ID code is a code for identifying what kind of data is assigned to each bit of the data area, that is, what kind of data is combined to form the data area. In the data area, on / off data such as a headlamp, turn right, turn left, horn, small lamp, headlamp high beam, and headlamp low beam are written for each bit.

[0005] When the receiving multiplex node receives the SD code, it recognizes the start of the frame F, and can identify the contents of data in the data area of the transmitted frame F by the frame ID code. In other words, since data can be selected at the multiplex node on the receiving side, options can be easily handled. Further, the receiving multiplex node recognizes the end of the frame F when receiving the check code following the data. Also, in order to ensure data transmission, the receiving multiplex node determines the frame F received from the check code.
Is determined if there is no error. If there is no error, an ACK signal indicating the own station address is returned to the multiplex bus MB after a certain time within a predetermined time, and the data cannot be normally received (check When an error is detected by a code) or at the time of a framing error (when data actually transmitted is shorter or longer than a specified data length), the receiving multiplex node does not return an ACK signal. .

In the multiplex node that has transmitted the frame F, upon receiving the ACK signal, it is possible to confirm that the data has been normally received on the receiving side, and the ACK signal is transmitted within a predetermined time after the frame transmission is completed. If not, the frame F has been retransmitted. Each multiplex node includes, as shown in FIG. 6, an interface circuit (I / F) 21 connected to the multiplex bus MB, a multiplex transmission control circuit 22, and a control circuit (CPU) 23. . When an arbitrary multiplex node transmits the frame F, in other multiplex nodes, the I / F 21 receives the frame F from the multiplex bus MB and sends it to the multiplex transmission control circuit 22. When the CPU 23 receives an interrupt due to the reception of the frame, the switch 23, the motor 25, and the other load devices 2
6 is interrupted, the frame ID code of the frame F captured by the multiplex transmission control circuit 22 is read, and it is determined whether or not subsequent data is necessary for the own station. Here, when the above data is required, the data following the frame ID code is fetched.

However, in the above conventional example, every time the frame F is taken into the multiplex transmission control circuit 22, the CPU 23
Interrupts the control of each load device and resets frame I to frame I.
To read the D code and determine the necessity of data,
The time required for U23 to receive data becomes longer, for example, when the multiplex bus MB is congested, there is a problem that the CPU 23 cannot play a role of controlling each load device.

Therefore, as shown in FIG. 7, some multiplex transmission control circuits 22 shown in FIG. 6 are provided with a storage circuit 27 such as a RAM, which can freely read and write data. In this conventional example, the frame ID code previously assigned to the data required by the own station is registered in the storage circuit 27 in byte units or the frame ID code as it is, and the frame ID code received from the I / F 21 is registered. ID
It is determined whether or not the code is the same as the registered frame ID code. If the code is the same, the received frame ID code and subsequent data are stored in the storage circuit 27 in byte units.

[0009]

However, in the above conventional example, the amount of data that can be stored is also limited due to the limitation of the capacity of the storage circuit, and all the data required by the receiving node cannot be stored. There was a point. Also,
In order to increase the amount of data that can be stored, the storage circuit may be configured with a large capacity, but in this case, there is a problem that the manufacturing cost of the entire system increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can store a frame ID code without increasing the storage capacity of a storage circuit.
It is an object of the present invention to provide an ID filtering method in multiplex transmission that can shorten data occupation time compared to an ID filtering method by a D code registration method and reliably perform data transmission.

[0011]

In order to solve the above-mentioned object, according to the present invention, there are provided a plurality of multiplex nodes mutually dispersedly connected through a common multiplex transmission line, wherein the multiplex nodes have multiplex transmissions which are mutually connected. There line transmission of data for each frame by the control means, the frame of data in the data area
In a multiplex transmission system having an identification code for identifying contents, each of the multiplex transmission control means has a storage means for storing the type of the identification code in bit units, and receives a frame from the multiplex transmission path. The received frame
Comparing the identification code of the received frame with the identification code stored in the bit unit, and
An ID filtering scheme in multiplex transmission for identifying a signal is provided.

[0012]

The bit string corresponding to the identification code is stored in the storage means provided in the multiplex transmission control means, and the necessity of the received frame is determined from the bits. Accordingly, the frame ID code can be stored without increasing the storage capacity of the storage means, and the occupation time required for data reception can be reduced as compared with the conventional ID filtering method based on the frame ID code registration method.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 3, the same components as those in the conventional example of FIG. 6 are denoted by the same reference numerals for convenience of explanation. FIG. 1 is a configuration diagram showing a schematic configuration of a multiplex node according to the present invention. 1 differs from the conventional example of FIG. 6 in that a multiplex transmission control circuit 22 is provided with a storage circuit 30 for storing a frame ID code in bit units.

That is, for example, an 8-bit frame ID
In multiplex transmission using a code, the storage circuit 30
The multiplex transmission control circuit 22 only needs to have a storage capacity of 56 bits.
The D code can correspond to each bit. When it is desired to determine a specific frame ID code corresponding to data required by the own station from among the frame ID codes, for example, a bit corresponding to the specific frame ID code is set to logic “1”, and other Required frame ID
The bit corresponding to the code is set to a different code such as logic "0". Thereby, the multiplex transmission control circuit 22
A maximum of 256 frame ID codes can be determined.

When a frame ID code of less than 256 bits, for example, 128 kinds of frame ID codes is sufficient, the multiplex transmission control circuit 22 may be provided with a storage circuit 30 having a capacity of 128 bits. . Further, a 1-bit storage circuit representing the maximum digit bit (for example, 128 bits) is provided, and the bit string used is 2 bits.
It is also possible to distinguish between the 56-bit upper bits and the lower bits. As described above, in the case where a small bit capacity is used, the storage circuit can be made small, and a storage circuit of a plurality of bits is additionally provided to specify which part of the 256-bit frame ID code is used. Can be. That is, an 8-bit frame I
A method of receiving identification by storing an ID bit pattern of a frame to be received of an arbitrary bit of the D code in a second storage device different from the above storage device is considered. For example, the upper 2 bits of the ID code are
If the bit pattern of “01” is stored here, the upper 2 bits of the ID code are “01”, and the lower 30 bits of the ID code are stored in the storage unit 30 in all bit strings. A function of receiving / non-receiving a bit corresponding to a pattern and receiving only a frame for which reception is specified here is a function of the storage unit 30.
It is possible to identify an 8-bit frame ID code with a total storage capacity of only 66 bits, that is, 64 bits in the second storage means and 2 bits in the second storage means, and the storage capacity can be greatly reduced.

Next, the operation of the multiplex node shown in FIG. 1 will be described. First, in each multiplex node according to the present embodiment, a specific frame I corresponding to data required by the own station is used.
When the D code is determined, when the CPU 23 performs initialization, a logical “1” is set in the storage circuit 30 in accordance with a write enable signal from the multiplex transmission control circuit 22 to distinguish it from unnecessary frame ID codes. Write to the bit corresponding to the frame ID code. An I / F 2 for interfacing the multiplex bus MB and the multiplex transmission control circuit 22
1 receives the frame F from the multiplex bus MB and sends the frame F to the multiplex transmission control circuit 22. The multiplex transmission control circuit 22 checks whether the frame ID code of the frame F is stored in the storage circuit 30. to decide. In other words, the multiplex transmission control circuit 22 outputs the captured frame F
It is determined whether or not “1” is set in the bit corresponding to the frame ID code of “1”. If “1” is set in the corresponding bit, an interrupt signal is sent to the CPU 23. In the case of “0”, the frame F is ignored.

When the CPU 23 receives the interrupt signal, it interrupts the control of each of the load devices 24-26, recognizes that it has received the frame F of the required data, and multiplexes the data of the frame F. The data is read from the control circuit 22 and stored in a storage circuit (not shown) in the CPU 23, and is used for control as a control parameter of the own station. FIG.
FIG. 6 is a configuration diagram showing a schematic configuration of a second embodiment of the multiplex node according to the present invention. In the figure, a multiplex transmission control circuit 2
2 is provided with two storage circuits 30 and 31,
0 has the same configuration as the storage circuit 30 of FIG. 1, and the storage circuit 31 stores data following the frame ID code, and corresponds to the data storage area 31a for the data and the data storage area 31a. And a flag area for setting a flag indicating the end of one frame of data.

In the above embodiment, as in the case of FIG. 1, the specific frame ID code corresponding to the data required by the own station is stored in the storage circuit 30 in advance, and the I / F 21 transmits the frame from the multiplex bus MB to the frame. F, and receives the frame F
Is transmitted to the multiplex transmission control circuit 22, the multiplex transmission control circuit 22 determines whether or not the frame ID code of the frame F is stored in the storage circuit 30. here,
If the frame ID code is stored, the multiplex transmission control circuit 22 sets the frame ID code to CP
U23, and the data following the frame ID code is stored in the data storage area 31a of the storage circuit 31,
In addition, a flag indicating the end of the data for one frame is set in a flag area provided corresponding to the data storage area 31a.

The CPU 23 stores the received frame ID code. Data stored in the storage circuit 31;
The frame ID codes stored in the CPU 23 are arranged and corresponded in the order in which they are stored. The CPU 23 reads out the data stored in the storage circuit 31 when necessary, and controls an actuator or the like as a load device. As a third embodiment, as shown in FIG. 3, there is a configuration in which two storage circuits 30 and 30a for the frame ID code in the above embodiment are provided.

The storage circuit 30 has the same configuration as the storage circuit 30 of FIG. 1, and determines the frame ID code to notify the CPU 23 of its own station of data reception by, for example, an interrupt signal. The storage circuit 30a includes, besides the frame ID code stored in the storage circuit 30, a specific frame ID corresponding to data that is not directly necessary for the CPU 23 of the own station, but is required by a subordinate node subordinate to the own station. The code is also stored together, that is,
This is to determine a frame ID code corresponding to data that needs to be stored in the storage circuit 31 of the own station.

The storage circuit 31 has a data storage area 31a for storing the frame ID code stored only in the storage circuit 30 and data following the frame ID code, and the storage circuits 30 and 3
0a and a data storage area 31c for storing data following the frame ID code. In the third embodiment, the I / F 21 is a multiplex bus M
When the frame F is received from B and transmitted to the multiplex transmission control circuit 22, the multiplex transmission control circuit 22
Indicates that the frame ID code of the frame F is stored in the storage circuit 30a.
It is determined whether or not it is stored. If the frame ID code is stored, the multiplex transmission control circuit 22 stores the frame ID code in the storage circuit 30.
It is determined whether or not it is stored.

If the frame ID code is not stored, the multiplex transmission control circuit 22 stores the frame ID code and subsequent data in the storage circuit 31.
In the data storage area 31c of the
A flag is set in a flag area provided corresponding to the storage address of the D code. The frame ID of the frame F
When the code is stored in the storage circuit 30, data is stored in the same procedure as in the second embodiment.

In the second and third embodiments, when transmitting an urgent signal, for example, a signal necessary for controlling the engine, the multiplex transmission control circuit 22 interrupts the CPU 23 to transmit the urgent signal. It is also possible to give priority to the signal. Therefore, in the present embodiment, the multiplex transmission control circuit is provided with a storage circuit that constitutes a table of a bit string corresponding to each frame ID code of a frame, and the above-mentioned storage corresponding to the frame ID code indicating data required at each multiplex node. Since the flag of the circuit was set to a flag,
When each multiplex node receives data, it becomes possible for the multiplex transmission control circuit to determine whether or not the received data is data necessary for its own station. As a result, the CPU does not judge the necessity of the received data,
Occupation time required for receiving the data of the first embodiment can be reduced. Further, since the frame ID code is specified in units of bits, the amount of stored data can be reduced, and the storage capacity of the storage circuit can be reduced.

Also, contrary to the above embodiment, the storage circuit 30
It is also possible to adopt a configuration in which the received frame of the ID code stored in the storage device is not received or the received data is discarded and not transferred to the CPU 23, and the received frame of the ID code not stored is received and transferred to the CPU 23.

[0025]

As described above, according to the present invention, a plurality of multiplex nodes are distributed and connected to each other via a common multiplex transmission line, and the multiplex nodes are provided for each frame by the multiplex transmission control means. There line transmission of data, the
The frame is an identification code that identifies the contents of the data in the data area.
In the multiplex transmission method having a code, the multiplex transmission control means has a storage means for storing the type of the identification code in bit units, and when a frame is received from the multiplex transmission path, the received Frame identification code and previous
The identification code stored in the bit unit is compared to identify the reception / non-reception of the data of the received frame, so that the identification code of the frame can be stored without increasing the storage capacity of the storage means. As a result, the occupation time required for data reception can be shortened compared to the ID filtering method based on the frame ID code registration method in the related art, and data transmission can be performed reliably.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a schematic configuration of a multiplex node according to the present invention.

FIG. 2 is a configuration diagram showing a schematic configuration of a multiplex node according to a second embodiment of the present invention;

FIG. 3 is a configuration diagram illustrating a schematic configuration of a third embodiment of the multiplex node according to the present invention;

FIG. 4 is a configuration diagram showing a schematic configuration of an automobile multiplex transmission system using the CSMA / CD system.

FIG. 5 is a diagram illustrating a frame configuration of a frame transmitted by a multiplex transmission method.

FIG. 6 is a configuration diagram showing a schematic configuration of a conventional multiplex node.

FIG. 7 is a configuration diagram showing another schematic configuration of a conventional multiplex node.

[Explanation of symbols]

 Reference Signs List 21 interface circuit (I / F) 22 multiplex transmission control circuit 23 control circuit (CPU) 30 storage circuit 31 storage circuit 31a data storage area 31b flag area MB multiplex bus

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kei Inoue 2-6-1 Marunouchi, Chiyoda-ku, Tokyo Inside Furukawa Electric Co., Ltd. (72) Inventor Hiroaki Sakamoto 3-1 Shinchi, Fuchu-cho, Aki-gun, Hiroshima Matsu (72) Inventor Yoshikazu Shinnoki 3-1 Shinchi, Fuchu-cho, Aki-gun, Hiroshima Prefecture Mazda Corporation (72) Inventor Seiji Hirano 3-1 Shinchi, Fuchu-cho, Aki-gun, Hiroshima Mazda In-house (56) References JP-A-3-16343 (JP, A) JP-A-59-215150 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (2)

(57) [Claims] [Claim 1 further comprising a plurality of multi-node distributed interconnected via a common multiplex transmission line, have line transmission of data for each frame by multiplexing transmission control means and said multiple nodes with each other, the frame Of the data in the data area
In the multiplex transmission method having an identification code for identifying the contents, each of the multiplex transmission control means has a storage means for storing the type of the identification code in bit units, and when a frame is received from the multiplex transmission path, , Of the received frame
An identification code and an identification code stored in the bit unit
ID filtering scheme in multiplex transmission, characterized by comparing the received data with the received data. 2. A comprising a plurality of multi-node distributed interconnected via a common multiplex transmission line, have line transmission of data for each frame by multiplexing transmission control means and said multiple nodes with each other, the frame Of the data in the data area
In the multiplex transmission system having an identification code for identifying the content, each of the multiplex transmission control means includes : first storage means for storing the type of the identification code in bit units; and arbitrary bits in a bit sequence of the identification code. A second storage unit for designating reception / non-reception, and receiving a frame from the multiplex transmission path according to the identification code stored in the first storage unit. An ID filtering method in multiplex transmission, characterized by identifying data of a frame and identifying reception / non-reception of the received data according to the contents stored in the second storage means.