JP3108271B2 - Waveform control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform control circuit,
In particular, the present invention relates to a waveform control circuit suitable for wirelessly transmitting dial information (information in which staircase waves having different frequencies approximating a sine wave are combined one by one) from a telephone handset to a base unit.

[0002]

2. Description of the Related Art At present, cordless telephones used in homes, each of which is a combination of a parent device and a child device, are becoming mainstream. Here, the master unit is connected to the exchange side of the central office via a telephone line. When making an outside line call using the master unit, the ten keys (0 to 9) for transmitting the telephone number provided on the master unit itself are operated, and the DT corresponding to the ten key is operated.
It is only necessary to transmit the MF wave (a composite wave of two kinds of sine waves having different frequencies) to the exchange via the telephone line. Then, the exchange side decodes the DTMF wave and determines the telephone number transmitted from the master unit. Thus, the user of the master unit can talk with a desired destination.

On the other hand, the slave unit is not connected to the master unit via a signal line. Therefore, when making an outside-line call using the slave unit, the ten-key operation information of the slave unit must be once wirelessly transmitted to the master unit. Then, the master unit decodes the ten-key operation information of the slave unit, and thereafter, the DTMF wave is transmitted from the master unit to the exchange side in the same manner as the above operation, so that external line communication is possible.

[0006] When wirelessly transmitting ten-key operation information from a child device to a master device, the ten-key operation information is generally divided into 4-bit digital data. Specifically, the numeric keys “0” to “9” are digital data “0000”.
To “1001”. Further, "0" of digital data corresponds to a sine wave having a frequency f1, and "1" of digital data corresponds to a sine wave having a frequency f2 (= 2f1). Thus, the ten-key operation information is information in which sine waves of the frequency f1 or f2 are serially connected for four periods according to the type of the ten-key. For example, when the ten key “9” is operated, the sine wave of the frequency f2 and the frequency f
A sine wave in which a sine wave of 1, a sine wave of the frequency f1, and a sine wave of the frequency f2 are sequentially connected is wirelessly transmitted from the slave unit to the master unit.

FIG. 3 is a diagram showing a conventional waveform control circuit for generating the continuous sine wave. In FIG.
(1-1) to (1-16) are ones whose one ends are commonly connected.
There are six resistors. (2) is a clock generator for generating a clock signal CK obtained by subjecting the oscillation signal OSC to predetermined frequency division in accordance with an instruction from a microcomputer or the like. For example, the clock generator (2) is configured to cascade-connect a plurality of T flip-flops (not shown) and to switch the number of connection stages of the plurality of T flip-flops according to the instruction. . Therefore,
The clock signal (CK) having a different frequency can be generated from the clock generator (2). (3-1) to (3-16)
The preceding Q (output) terminal is a D flip-flop cascaded to the subsequent D (data) terminal, the R (reset) terminal is connected to the source of the reset signal RST,
The C (clock) terminal is connected to the output of the clock generator (2). Furthermore, the final stage D flip-flop (2-
The Q terminal 16) is connected to the D terminal of the first stage D flip-flop (2-1) via the inverter (4).
That is, the D flip-flops (3-1) to (3-16) are configured to circulate the shift data. The Q terminals of the D flip-flops (3-1) to (3-16) are connected to the resistors (1-1) to (1-16) via the inverters (5-1) to (5-16), respectively. Is connected to the other end. According to the above configuration, the resistances (1-1) to (1-1)
A sine wave can be output from the common connection point 6), and this sine wave is formed by approximating a staircase wave.

The operation of FIG. 3 will be described below with reference to the waveform diagram of FIG. FIG. 4 shows a staircase wave corresponding to a sine wave, and the change level of the staircase wave is fixed for convenience of explanation. First, at time t0, when the D flip-flops (3-1) to (3-16) are reset, the outputs of the inverters (5-1) to (5-16) all become high level. As shown in FIG. 4, the resistance (1-1)
The maximum voltage Vdd is generated at the common connection point of (1-16). Thereafter, at time t1, when the clock signal CK rises, the D flip-flops (3-1) to
The data of the Q terminal of (3-15) is applied to the D terminals of the subsequent D flip-flops (3-2) to (3-16), and the data of the Q terminal of the final stage D flip-flop (3-16). The data is fed back to the D terminal of the first-stage D flip-flop (3-1) via the inverter (4). Thus, except for the output of the inverter (5-1) being at a low level, the outputs of the remaining inverters (5-2) to (5-16) are all at a high level, and the resistances (1-1) to (1-) A voltage one step lower can be generated from the common connection point of 16). As described above, the D flip-flops (3-1) to (3-16) repeat the shift operation based on the rising edge of the clock signal CK 32 times, whereby the D flip-flops (3-1) to (3-1)
The circuit goes round until the 16-bit output data of 6) gives the staircase wave level at time t0, and a staircase wave for one cycle can be generated. The values of the resistors (1-1) to (1-16) are selected so that the staircase wave in FIG. 4 approximates a sine wave. In particular,
Resistance (1-1) (1-16), resistance (1-2) (1
−15), resistance (1-3) (1-14),.
The values of the resistors (1-8) and (1-9) are set equal.

Accordingly, the frequency of the clock signal CK obtained from the clock generator (2) is controlled by an instruction of a microcomputer or the like, and a serial waveform is generated by combining one cycle of staircase waves having different frequencies approximate to a sine wave. I was able to do it. As a result, the parent device recognized the ten-key operation information of the child device.

[0008]

Here, a staircase wave (hereinafter, referred to as a sine wave) having a frequency different from that of a sine wave is referred to as a sine wave.
In the case of serial generation by combining one cycle at a time, it is originally desirable to connect the sine waves at the same voltage level so that the master unit can reliably recognize the frequency of each staircase wave. For example, one cycle of each sine wave may be started from the midpoint voltage Vdd and ended at the midpoint voltage Vdd, and each sine wave may be connected at the midpoint voltage Vdd.

In general, a master unit takes in sine wave information transmitted from a slave unit into an inverter having a threshold voltage of Vdd / 2, and outputs a midpoint based on a change in output from a low level to a high level of the inverter. The voltage Vdd / 2 is detected, and the time from when the output of the inverter changes from low level to high level again is counted. The content of the count represents one cycle of the sine wave of the frequencies f1 and f2. Therefore, if one cycle of the sine wave of the frequency f1 or f2 is T1, T2 (> T1), respectively, T1 <
The contents of the count representing the time t satisfying the relationship of t <T2 are prepared in advance. Then, the actually counted contents are compared with the prepared contents. When the actual contents are smaller than the prepared contents, it is determined that the sine wave has the frequency f1. Is larger than the prepared count content, it is determined that the sine wave has the frequency f2.

However, the microcomputer for instructing the sine wave to change the frequency has no means for detecting what voltage level the sine wave is at a certain time. That is, the voltage for connecting the sine waves in one cycle unit is not necessarily determined as the midpoint voltage Vdd / 2. Thus, when the sine waves are connected at a voltage level other than the midpoint voltage Vdd / 2, even if the master unit measures the period of this sine wave based on the midpoint voltage Vdd / 2, the frequency f1 The time from the middle of the sine wave of (or f2) to the middle of the sine wave of the following frequency f1 (or f2) is counted, and therefore, one correct cycle of the sine wave of the frequency f1 or f2 is calculated. There was a problem that could not be counted. Therefore, there is a problem that the master unit cannot correctly detect the cycle of each sine wave, and cannot correctly transmit the ten-key operation information of the slave unit to the exchange.

Therefore, according to the present invention, the base unit can accurately measure the period of the sine wave at the voltage level for connecting the sine waves of a plurality of periods wirelessly transmitted from the slave unit of the telephone set to the base unit. It is an object of the present invention to provide a waveform control circuit capable of setting a level.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is characterized by clock generating means for generating a clock signal based on an oscillation signal; A plurality of flip-flops connected in series so that the output of the last stage is fed back to the input of the first stage, a shift register means for circulating data in synchronization with the clock signal, and one end connected to each output of the shift register means. Ladder resistance means for generating a sine wave voltage in accordance with a change in the content of the shift register means from a common connection point, and detecting a change in a predetermined output of the shift register means. An interrupt generating means for generating an interrupt signal for changing the frequency of the clock signal; and detecting the interrupt signal and generating a control signal for changing the frequency of the clock signal. In that with the control means.

[0013]

According to the present invention, among the outputs of the plurality of flip-flops constituting the shift register means, a single flip-flop output which changes at a position where each sine wave has a specific level is output to the interrupt generation means. Connecting. Thus, each time each sine wave reaches a specific level after one cycle, the interrupt generating means detects a change in the output of the flip-flop and generates an interrupt signal. A signal is detected to generate a control signal for varying the frequency of the clock signal. Therefore, the frequency of the clock signal applied to the shift register means is varied at a specific level of the sine wave. That is, the sine waves serially output are continuous waveforms connected at a specific level.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a waveform control circuit of the present invention. still,
FIG. 1 is provided on a chip constituting a microcomputer. It is assumed that the microcomputer is built in the slave unit of the telephone.

In FIG. 1, reference numeral (6) denotes a clock generator, which divides an oscillation signal OSC by a predetermined frequency and generates a clock signal for operating each component in the microcomputer. The clock generator (6)
Is configured such that a plurality of T flip-flops are cascaded and the number of connection stages of the T flip-flops can be switched according to an instruction from the CPU. (7) is C
It is a PU for controlling the operation of each component inside the microcomputer. Reference numeral (8) denotes an AND gate, to which an open / close control signal CTL1 output from the CPU (7) is applied to one input, and a clock signal CK output from the clock generator (6) is applied to the other input. .
That is, the AND gate (8) outputs the clock signal CK when the open / close control signal CTL1 is at the high level based on the instruction to output the sine wave waveform. (9) is 1
This is a shift register in which data input / output lines of six D flip-flops are cascaded, and the inverted output (* Q) of the last D flip-flop is connected to the data input (D) of the first D flip-flop. . The clock signal CK output from the AND gate (8) is applied to the C terminals of the 16 D flip-flops, and the reset signal RST is applied to the R terminals. That is, after the 16 D flip-flops are reset, the clock signal C
The data shift operation is performed in synchronization with the rise of K. (1
Reference numeral 0) denotes a ladder resistance network composed of 16 resistors. One end of each resistance is connected in common, and the other end is connected to each Q terminal of 16 D flip-flops.

FIG. 2 is a diagram showing details of the shift register (9) and the ladder resistor network (10) shown in FIG. Since FIG. 2 has the same configuration as FIG. 3, the same reference numerals are given and the description of the same portions is omitted. By the way, in the present embodiment, the data to be transmitted from the slave to the master
Each sine wave (numerical key operation information) for the cycle is the midpoint voltage V
It is assumed that dd / 2 is connected and connected continuously. In FIG. 4, the staircase wave becomes Vdd / 2 after reset when the D flip-flops (3-1) to (3-16) perform eight shift operations based on the clock signal CK. is there. That is, when the output of the D flip-flop (3-8) rises from a low level to a high level. Therefore,
In order to detect a rising change of the output Q8 of the D flip-flop (3-8), the output Q8 of the D flip-flop (3-8) is connected to an interrupt generation circuit described later.

Returning to FIG. 1, reference numeral 11 denotes an interrupt generation circuit which detects a rising change in the output of the D flip-flop (3-8), that is, each sine wave is shifted from the Vdd side to the midpoint voltage Vdd /.
2 is detected, and an interrupt signal for generating a sine wave to be connected next is generated. (1
Reference numeral 2) denotes a ROM, which has an area in which a main program for normal operation of the microcomputer is stored, and an area in which a subroutine program for jumping when a numeric keypad of the slave unit is operated is stored. ing. Reference numeral (13) denotes a RAM for writing and reading the result of the arithmetic processing of the CPU (7) and for writing 4-bit information corresponding to a ten-key operation of the slave unit in response to a program command of the ROM (12). It is.

Hereinafter, an example of the operation of FIG. 1 will be described. In other words, consider a case where an outside-line call is performed using a slave unit. In this case, as described in the section of the related art, it is necessary to serially transfer a sine wave for four cycles corresponding to the numeric keypad from the slave unit to the master unit. For example, when the ten key "6" is operated, the operation of the "6" is detected by the CPU (7), and the ROM (12) interrupts the processing of the main program and jumps to the subroutine program. And
According to the program instruction of the ROM (12), 4-bit data “0110” corresponding to “6” is transferred from the internal register of the CPU (7) to the RAM (1) via the data bus (14).
The data is written to the specific address of 3), the shift register (9) is reset, and the open / close control signal CTL1 goes high.

Next, according to the program command of the ROM (12), the 4
The least significant bit “0” of the bit data is taken into the CPU (7), and as a result, the clock signal C
K is the frequency corresponding to data "0" (for example, 200H
z), a clock control signal CTL2 is generated. As a result, the 200 Hz clock signal CK is applied to the C terminal of the shift register (9), and a step wave approximating the stair wave shown in FIG. 4 to a sine wave is output from the ladder resistor network (10). Even if an interrupt signal is generated at the first rising transition of the D flip-flop (3-8) at time t2, a program is designed so that the CPU (7) does not accept the interrupt signal. That is, a sine wave having a frequency of 200 Hz corresponding to the data “0” starts at time t2. Until the sine wave reaches time t3, R
OM (12) returns to the main program.

Next, at time t3, when the output of the D flip-flop (3-8) rises, the interrupt generation circuit (1)
An interrupt signal is generated from 1), and this interrupt signal
When detected in (7), the ROM (12) interrupts the main program processing and jumps again to the subroutine program. Then, in accordance with a program command of the ROM (12), the lower second bit "1" of the 4-bit data written at a specific address of the RAM (13) is changed to the CPU (7).
As a result, the clock (C) is output from the CPU (7).
K is the frequency corresponding to data “1” (for example, 400H
z), a clock control signal CTL2 is generated. As a result, the 400 Hz clock signal CK is applied to the C terminal of the shift register (9), and a sine wave having a frequency twice that of the sine wave from the time t3 to the time t2 from the time t3 is generated. The ROM (12) returns to the main program until the output of the D flip-flop (3-8) rises again.

Next, when the output of the D flip-flop (3-8) rises again, an interrupt signal is generated from the interrupt generation circuit (11), and this interrupt signal is detected by the CPU (7). R
The OM (12) interrupts the main program and jumps to the subroutine program again. Then, the ROM (1
According to the program instruction of 2), the lower third bit "1" of the 4-bit data written to the specific address of the RAM (13) is taken into the CPU (7).
A clock control signal CTL that sets the clock signal CK from PU (7) to a frequency of 400 Hz corresponding to data “1”
2 occurs continuously. As a result, the 400 Hz clock signal CK is applied to the C terminal of the shift register (9), and a sine wave having the same twice frequency as the immediately preceding sine wave is generated. The ROM (12) returns to the main program again until the output of the D flip-flop (3-8) rises again.

Finally, when the output of the D flip-flop (3-8) rises again, an interrupt signal is generated from the interrupt generating circuit (11), and this interrupt signal is detected by the CPU (7).
The ROM (12) interrupts the main program and jumps to the subroutine program again. And ROM
According to the program instruction of (12), the most significant bit “0” of the 4-bit data written at the specific address of the RAM (13) is taken into the CPU (7).
A clock control signal CT from the CPU (7) for changing the clock signal CK to a frequency of 200 Hz corresponding to data "0"
L2 occurs. As a result, the 200 Hz clock signal CK is applied to the C terminal of the shift register (9), and a sine wave having a frequency half the frequency of the immediately preceding sine wave is generated. As described above, the sine waves of the frequencies corresponding to “0” and “1” can be reliably connected at the level of the midpoint voltage Vdd / 2. Since the connection of the sine waves of the frequency corresponding to the 4-bit data is completed, the ROM (12) sets the open / close control signal CTL1 to low level and returns to the main program.

The 4-bit data "011"
The sine wave serially output for four cycles corresponding to "0" is taken into the master unit, and is based on the midpoint voltage Vdd / 2 in the same manner as the operation described in the section of the problem to be solved by the invention. Period determination is performed, and as a result, what numeric key is operated is reliably determined. As described above, when serial transmission of sine waves for four cycles is performed from the slave unit to the master unit, a voltage level for connecting the sine waves can be arbitrarily set in accordance with the specification of the cycle detection unit of the master unit. That is, the interrupt generation circuit (1) is provided on the microcomputer chip.
What is necessary is just to select an arbitrary output of the shift register (9) connected to 1) and perform mask wiring. In this embodiment,
Although the sine waves are connected at the midpoint voltage Vdd / 2 according to the specifications of the master unit, it goes without saying that the present invention is not limited to this.

The interrupt generation circuit (11) is configured to detect a rising change of the output of the D flip-flop (3-8). So that each sine wave of one cycle is
May be connected at the midpoint voltage Vdd / 2 when rising to the midpoint voltage Vdd / 2. Further, the interrupt generation circuit (11) may be configured to detect both a rising change and a falling change of the output of the D flip-flop (3-8) and generate an interrupt signal. The sine waves can be connected at the midpoint voltage Vdd / 2 every half cycle.

[0025]

According to the present invention, the base unit accurately measures the voltage level at which the sine waves of a plurality of cycles wirelessly transmitted from the slave unit of the telephone set to the master unit are connected to each other. Thus, there is obtained an advantage that the master unit can reliably determine the operation information of the slave unit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a waveform control circuit of the present invention.

FIG. 2 is a diagram showing a main part of FIG. 1;

FIG. 3 is a diagram showing a conventional waveform control circuit.

FIG. 4 is a waveform diagram showing a staircase wave generated in FIGS. 1 and 3;

[Explanation of symbols]

 (6) Clock generator (7) CPU (9) Shift register (10) Ladder resistance network (11) Interrupt generation circuit (12) ROM (13) RAM

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/12 H03B 28/00

Claims (3)

(57) [Claims] A clock generating means for generating a clock signal based on an oscillation signal; and a plurality of flip-flops connected in series so that an output of a final stage is fed back to an input of a first stage. Shift register means for circulating the data, one end of which is connected to each output of the shift register means, and the other end of which is connected in common. Ladder resistance means for generating an approximated staircase voltage; interrupt generation means for detecting a change in a predetermined output of the shift register means and generating an interrupt signal for varying the frequency of the clock signal; Control means for detecting the input signal and generating a control signal for varying the frequency of the clock signal. 2. The waveform control circuit according to claim 1, wherein said interrupt generating means detects a change in a predetermined output of said shift register means when said staircase voltage reaches a specific level. 3. The waveform control circuit according to claim 2, wherein the frequency of the staircase voltage can be changed at a specific level of the staircase voltage.