JP3104815B2 - Test design equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tester used for testing an IC (integrated circuit), and more particularly to a test design apparatus for preparing data necessary for preparing a tester control program.

[0002]

2. Description of the Related Art In testing an IC, it is necessary to grasp the functions of both the IC and the IC test apparatus. The signals required to test the IC include input signals, output signals,
There are three types of input / output signals.
C, and the output signal is a signal output from the IC to the peripheral device. The input / output signal is a signal in which an input signal and an output signal are alternately switched.

[0003] These signals take several states electrically. Now, there are two voltages E1 and E2, and E1> E2
Then, when the signal voltage> E1, the signal is in the high state,
When 1 <signal voltage <E2, the signal is in a high impedance state, and when signal voltage <E2, the signal is in a low state. An event that the signal changes from such a certain state to another state is an event. That. There are three types of events: an input event, an output event, and an input / output switching event. The input signal status change, the output signal status change, and the input / output signal alternate switching status change in the input / output signal, respectively. Say. A state in which a signal causes such a state change is called a signal state.

[0004] The operation of an IC is defined by the time between these events, which is called the operation specification of the IC. Further, the IC performs an operation of repeating a series of operations performed at a constant period called an operation cycle. Normal IC operation specifications are 1
Or, it is composed of more operation cycles.

[0005] In order to test whether or not an IC functions according to the operation specifications, an apparatus called a simulator and an apparatus called a tester are used. A simulator is a device that virtually implements the function of an IC on a computer. When an appropriate input signal is input to the simulator, an expected value of an output signal when the IC is normal can be obtained. As a result, a simulation result in which a signal operation for the IC is described by a time from an appropriate reference time to an event is obtained for each signal. Such an operation is called a simulation. This simulation is performed before manufacturing the IC, and its execution requires a long time.

On the other hand, an IC test apparatus called a tester is used for inspecting the manufactured IC. The tester
A signal is applied to the IC, and as a result, a signal output from the IC is observed, and the quality of the IC is determined by comparing the signal with an expected value set in advance. For this purpose, a waveform generator, a timing generator (hereinafter, referred to as TG), and an application pattern are used.

[0007] The application pattern, in combination with the waveform mode of the waveform generator, defines the signal operation during one test cycle described later. The TG defines its operation timing (the timing of occurrence of each event). The strobe state and the expected value pattern are used to observe the output signal. The expected value pattern is represented by H and L, indicating that the output signal must be in a high state and a low state, respectively. The strobe specifies the timing of observing the output signal, and the tester compares the electrical state (high, low, impedance state) of the output signal observed at the specified timing with an expected value pattern and, based on the comparison result, The quality of the IC is determined. The input / output switching TG is used for switching between the input state and the output state of the input / output signal. The input / output switching TG includes ON and OFF TGs, and defines the input state start timing and the input state end timing, respectively.

The above hardware, ie, a waveform generator,
The TG, the strobe, and the input / output switching TG are collectively called a tester resource, and the applied pattern and the expected value pattern are collectively called a test pattern.

Tester resources such as the TG, strobe, and input / output switching TG described above define the operation timing of signals. The reference of the timing is a pulse that is self-generated at a constant period inside the tester, and the position where the pulse is generated is represented by a symbol T0. The time from one symbol T0 to the next symbol T0 is the above-described test cycle, and the timing set value in the TG, strobe, and TG for input / output switching is determined by the symbol T0.
Is defined by the time since

[0010] The timing set values of the tester resources are put together in test cycle units to form a timing set, and each obtained different timing set is given a name. Changing the signal operation timing is performed by designating the name of a desired timing set in the test pattern.

[0011] The tester has a tester resource that can be allocated to all the signals used in the IC, and the tester resource number is smaller than the number of signals required for the IC. Some tester resources must be shared. The former is called a per-pin type tester, and the latter is called a shared resource type tester.

To test an IC using a tester,
The tester resources of the tester must be allocated to each signal of the IC, and a test pattern must be created. This work is called test design.

Conventionally, in a test design work, a test designer who is familiar with the specifications of testers that differ from one tester to another manually performs I / O operations in consideration of IC operation specifications and simulation results.
Tester resources are allocated to each signal of C, and a timing set is determined for each test cycle. As for the test pattern, an applied pattern and an expected value pattern are created based on the simulation result, and timing set information is added.

As a device for performing a test design, a device for performing a test design using a simulation result as input data is mainly used. Related to this type of device is a system called TDS of TSSI. This system is based on VLSI Systems Design July 1986, pp. 92-97 (VLSI SYSTEMS DESIGN).
July 1986, PP92-97), a simulation result is used as input data, a test cycle is determined in consideration of tester specifications, tester resources are allocated to each signal of the IC, and a test pattern is created. Is performed automatically. When testing an IC using a per-pin tester, the test designer does not have to run out of tester resources and cannot allocate tester resources to each signal.
A test design can be performed using the result of the simulation as input data without being conscious of the specifications of the tester.

[0015]

However, the above-described conventional test design apparatus has the following problems in test design of an IC using a tester.

(1) Since the specifications of the tester differ for each model of the tester, the test designer must be familiar with the specifications of all the testers used for testing the IC. Further, in a system that performs test design using simulation results as input data, if test design fails for any reason, it is necessary to execute a simulation that takes a long time to confirm the result of redoing the test design. In particular, when testing an IC using a shared resource type tester, there is a high possibility that the test design will fail due to insufficient tester resources.

(2) The test design includes an operation of allocating tester resources in consideration of an operation taken by an IC signal during a test, and an operation of converting a simulation result into a test pattern based on the result. You. Of these, tester resource distribution work differs in work content depending on whether the tester is a per-pin method or a shared resource method.

Since the per-pin type tester has tester resources that can be distributed to all signals of the IC, it is possible to mechanically perform tester resource distribution work. However, in the case of the shared resource type tester, since the tester resources are smaller than the number of signals of the IC, the tester resources must be shared among a plurality of signals. For this reason, the designer must be able to share the tester resource among a plurality of signals by repeating the operation of changing the operation timing of the signal and allocating the tester resource.

Therefore, in the above-described conventional test design, in order to create input data for tester resource allocation, a simulation must be performed while variously changing the signal operation timing to obtain a simulation result. There was a problem that confirmation took time.

A first object of the present invention is to enable a test designer to perform a test design without being conscious of the specifications of a tester, using input data of an operation specification of the IC created at the time of IC design. It is an object of the present invention to provide an improved test design device.

A second object of the present invention is to provide a test design apparatus capable of allocating tester resources in a short time and converting a simulation result into a test pattern.

[0022]

In order to achieve the above object, the present invention provides a tester specification database in which an event symbol representing an event as a signal change and a tester specification are described, and an operation is performed using the event symbol. First means for defining an operation specification of the IC under test as a change in signal for each cycle; second means for dividing the defined operation specification of the IC under test at a predetermined cycle; A third means for defining the observed position of the electrical state of the signal in the operation specification of the IC under test, and the event symbol and the observed position set by the first and third means. And a fifth means for designing a test of the IC under test by referring to the information on the specifications of the tester.

According to another aspect of the present invention, there is provided a means for determining a condition for identifying a plurality of operation cycles of an IC from each other, and identifying the operation cycle of the IC from a simulation result using the condition. Means and means for converting the identified simulation result into a test pattern with reference to the tester resource allocation result.

[0024]

The operator defines the operation specifications of the IC in operation cycle units by using a symbol representing a change in the state of a signal.
When the observation position of the signal is determined, the defined operation specification of the IC is divided into an appropriate test cycle, a reference time point T0 of the test cycle is set, and the set position to the tester resource in the operation specification of the IC is obtained. The tester resources are allocated in consideration of the tester specifications.

Further, conditions for identifying the operation cycles of the IC defined by the operator are obtained, and the operation cycles are identified from the simulation results using the conditions.
The identified simulation result is converted into a test pattern in consideration of the tester resource allocation result.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing an embodiment of a test design apparatus according to the present invention. 100 is a CPU (central processing unit), 101 is a keyboard, 102 is a binding device, 103 is a display device, and 104 is a tester. Specification database, 105 is an event symbol database, 106 is a waveform mode operation database, 107 is T
G distribution rule database, 108 is a tester resource database, 109 is a tester resource distribution processing unit, 11
0 is an operation specification definition unit, 111 is a T0 setting unit, 112 is an observation position definition unit, 113 is a tester resource setting position calculation unit, and 114 is a test design unit.

Referring to FIG. 1, a CPU 100 for controlling the entire device, a keyboard 101 and a pointing device 102 as input devices, a display device 103 as an output device, a tester specification database 104, and an operation of an IC are shown. It comprises a tester resource allocation processing unit 109 for defining a cycle and allocating tester resources.

Then, the tester specification database 104
Uses an event symbol database 105 in which symbols representing events used when inputting the operation specifications of the IC to this apparatus are arranged, and the symbol mode is used to indicate the operation that a tester used in the test can take in a waveform mode in one test cycle. And organized waveform mode operation database 106
And a TG distribution rule database 107 in which the relationship between the waveform modes described in the waveform mode operation database 106 and TGs (timing generators) that define the operation timings thereof, and the types of tester resources of the tester used in the test The tester resource distribution processing unit 109 defines an operation specification of an IC, and defines a set position of a symbol T0 serving as a time reference of the operation of the tester. A T0 setting unit 111, an observation position definition unit 112 that defines an observation position of an output signal and an input / output signal, an operation specification definition unit 110, a T0 setting unit 111,
The operation specifications of the IC defined by each of the observation position definition units 112,
A tester resource setting position calculation unit 113 that calculates a tester resource setting value based on the setting position of the symbol T0 and the observation position of the output signal, and a tester resource that can be allocated to each signal with reference to the tester specification database 104. And a test design unit 114 for determining

FIG. 2 shows a specific example of the event symbol database 105 in FIG. 1, which is an example of a symbol used to represent an event when defining the operation specifications of an IC in this embodiment. It is a list showing.

In the figure, such symbols are divided into a symbol representing a change in the state of a single signal indicated by a heading 200 and a symbol indicating a change in the state of a plurality of signals indicated by a heading 201. Further, it is divided into a symbol representing a change in the state of an input signal indicated by a heading 202, a symbol indicating a change in the state of an output signal indicated by a heading 203, and a symbol indicating a change in the state of an input / output signal indicated by a heading 204.

In the symbols representing the states of a single signal, symbols 205 and 223 indicate that the input signal and the output signal change from low to high, respectively, and symbols 206 and 224 indicate that the input signal and the output signal respectively change to high. From the low state to the low state.
Symbols 5 and 241 indicate that the input signal, output signal and input / output signal change from the high impedance state to high, respectively, and symbols 208, 226 and 242 indicate that the input signal, output signal and input / output signal change from the high impedance state, respectively. Symbol 209, indicating a low state change.
Symbols 227 and 243 indicate that the input signal, output signal and input / output signal change from high to high impedance state, respectively, and symbols 210, 228 and 244 indicate that the input signal, output signal and input / output signal change from low to high impedance, respectively. The state changes to the state.

The symbols representing the state changes of a plurality of signals are used when a plurality of signals are collectively represented as one signal.
Reference numerals 9 and 245 denote that there are a signal that changes from a high-impedance state to a high state and a signal that changes from a high-impedance state to a low state with respect to the input signal, the output signal, and the input / output signal. 2
Reference numeral 46 indicates that there are a signal that changes from a high state to a high impedance state and a signal that changes from a low state to a high impedance state with respect to the input signal, the output signal, and the input / output signal, and the symbols 213 and 231 respectively indicate
The symbols 214 and 232 indicate that the input signal and the output signal change from low to high and the signal changes from high to low, respectively. The symbols 215 and 233 indicate an input signal and an output signal, respectively, indicating a signal that changes state, a signal that changes state from high to low, a signal that remains high and does not change state, and a signal that remains low and does not change state. , A signal that changes state from low to high, a signal that changes state from high to low, and a signal that does not change state while remaining low. Symbols 216 and 234 indicate the input signal and the output signal, respectively, from low to high. Indicates a signal that changes state from high to low, a signal that changes state from high to low, and a signal that does not change state while remaining high. Symbols 217 and 235 indicate that the input signal and the output signal include a signal that changes state from low to high, a signal that remains low and does not change state, and a signal that remains high and does not change state. Indicates that the input signal and the output signal include a signal that changes state from high to low, a signal that remains low and does not change state, and a signal that remains high and does not change state. Symbols 219 and 237 indicate input signals and output signals, respectively. Symbols 220 and 238 indicate that the signal and the output signal change from low to high for the input signal and the output signal, respectively, indicating that there is a signal that changes from high to low and a signal that does not change state while remaining high. The symbols 221 and 239 indicate that there is a signal that remains high and a signal that does not change state while remaining high. Signal, the output signal indicates that there is a signal that does not change in state remains signals and row changes state from low to high,
Symbols 222 and 240 indicate that the input signal and the output signal include a signal that changes state from high to low and a signal that remains low and does not change state.

In this embodiment, the operation specifications of the IC are defined by using a total of 42 types of symbols.

FIG. 3 shows a specific example of the waveform mode operation database 106 shown in FIG. 1, and shows the operation of signals during one test cycle defined in each waveform mode. The names of waveform modes that can be set by the tester and the operation of signals during one test cycle defined by the waveform mode are represented using symbols.

In the figure, here, a vertical heading 30
As shown in FIG. 1, it is assumed that the waveform generator in the tester can take six types of waveform modes.
B, C, D, E, F, G. Further, as shown by the horizontal heading 300, it is assumed that there are eight types of signal operations in one test cycle defined by these waveform modes, and these are represented by symbols U302, H303, D304, L305,
UD306, DU307, UDU308, DUD309
And

Symbol U302 indicates that the signal changes state from low to high, symbol H303 indicates that the signal remains high for one test period, and symbol D304 indicates that the signal changes state from high to low. And the symbol L305 indicates that the signal remains low for one test period. Therefore, the symbol U
Symbols UD306, DU307, U, which are a combination of these symbols, so that D306 indicates that the signal changes state from low to high and then from high to low.
DU 308 and DUD 309 represent a combination of the above operations represented by individual symbols U and D.

The circles in FIG. 3 indicate the signal operations that the waveform mode can take during one test cycle. For example, the waveform mode A indicates the symbols U302 and H30.
3, signal operations indicated by D304 and L305 are possible.

FIG. 4 shows a specific example of the TG distribution rule database 107 in FIG. 1, and shows the possible signal operations in each waveform mode defined in the waveform mode operation database 106 shown in FIG. It indicates the type of TG that defines the operation timing.

In the same figure, the vertical heading 401 shows the waveform modes E, F, and G of the tester used for the test, and the horizontal heading 400 shows the type of TG of the tester.
1, TG2, and TG3, respectively. And FIG.
The waveform mode is associated with the TG for the signal taken by the event symbol shown by.

Since the input signals of the symbols H303 and L305 in FIG. 3 remain high or low during one test period, TG is not defined for them.

Therefore, referring to the waveform mode E, FIG. 3 shows that the waveform mode E is the symbol U30.
2, D304, UD306 and DU307, the waveform mode E of which is shown in FIG.
When the signal operation of the symbol D304 is performed, the specified TG is TG1, and when the signal operation of the symbol D304 is performed, the specified TG is TG1. When the signal operation of the symbol UD306 is performed, first, the TG defined by the signal operation of the symbol U is TG2, and the signal operation of the next symbol D is TG3. When the signal operation of the symbol DU307 is performed, first, the TG defined by the signal operation of the symbol D is TG2, and the signal operation of the next symbol U is TG3.

The same applies to the waveform modes F and G.
As is apparent from FIG. 4, different TGs can be defined when the waveform mode E takes the signal operation of the symbols U302 and D304 and when the waveform mode F takes the signal operation of the symbols UD306 and DU307.

FIG. 5 shows a specific example of the tester resource database 108 shown in FIG. 1, in which types and numbers of tester resources in the tester used for the test are summarized.

In this figure, here, the type of TG 50
0 is TG1, TG2, TG3, TG4, respectively, and the strobe 501 is the strobes 1, 2, 2,
3, 4, input / output switching TG (input state start) 502
Indicates that the input / output switching TGs 1, 2, 3, and 4 and the input / output switching TG (for ending the input state) 503 are input / output switching TGs 5, 6, 7, and 8, respectively.

Next, the operation of this embodiment will be described. FIG.
When the test design apparatus is started, the CPU
100 activates the operation specification definition unit 110 to define the operation cycle of the IC. That is, the operation specification definition unit 110
Displays a menu 600 of symbols of the event symbol database 105 shown in FIG. FIG. 6 shows an example of the display.

While watching the display, the operator firstly
Keyboard 101 or pointing device 10
2 are used to define signal names 601 and 602 (here, signals 1 and 2), and a symbol menu 600
, And input the operation specifications of the IC to be tested. Since the operation specifications of the IC define the operation of the signal based on the time between events, the operator selects an event symbol from the menu 600 and places it on the display device 103. Here, two event symbols are arranged in signal 1 and one event symbol is arranged in signal 2.
Thereafter, the time between the preceding event of signal 1 and the event of signal 2 is defined using keyboard 101 or pointing device 102. With this definition, the operation specification definition unit 110 opens a time relationship definition window 603 on the screen, and displays a defined time between these events as, for example, 30 nsec.

Although it is not necessary to describe the operation specifications of the IC in terms of the time relationship between the events, by inputting the same description format as the operation specifications of the IC, test design can be performed in the form of IC operation specifications that are unrelated to the tester specifications. , And common input data can be used when testing the same IC with different testers.

FIG. 7 shows an example of the operation specification of the IC defined by the operation specification definition section 110. Here, a thin line represents an input signal, and a thick line represents an output signal and an input / output signal.

When the operator has defined the operation specifications of the IC,
The operation specification definition unit 110 notifies the CPU 100 of the end of the process, and the CPU 100 then activates the T0 setting unit 111.

The activated T0 setting unit 111 divides the operation specification of the IC defined by the operation specification definition unit 110 at an appropriate test cycle, and divides the division position by the symbols T0800, 801 and 802 as shown in FIG. Express. In this example, the test cycle is 100 nsec, and the position of the symbol T0800 is defined by the time from the first event of the input signal surrounded by the frame 803. Therefore, in this case, for example, a time point 30 nsec before the first event 803 of the input signal is defined as the symbol T0800. Therefore, 100 ns from the time point of this symbol T0800.
The symbols T0801 and 802 are set at the time interval c.

When the symbol T0 has been defined, the T0 setting unit 111 notifies the CPU 100 of the end of the processing, and
Next, the observation position definition unit 112 is activated.

The activated observation position definition unit 112 displays the operation specifications of the IC defined by the operation specification definition unit 110 on the display device 103. In this state, the operator uses the keyboard 101 or the pointing device 102 to define a position for observing the electrical state of the output signal and the input / output signal. As a method of defining the observation position, there are a method of observing at the output event position, a method of defining the observation position by the time from the output event, and a method of defining by the time from the set position of the symbol T0.

FIG. 9 shows a display example when the observation position is defined by the time from the output event position and the time from the set position of the symbol T0. Observation position is symbol 90
2, 903 and 904. In this example, 20 ns from the first event surrounded by the frame 900 of the output signal
The observation position is a position where ec has elapsed and a position where 20 nsec has elapsed from the next event surrounded by the frame 901. Further, the position at which 80 nsec has elapsed from the first symbol T0 is set as the observation position of the input / output signal.

When the observation position is uniformly defined by the time from the position of the output event or uniformly by the time from the symbol T0, the operator instructs the observation position definition unit 112 to do so. The observation position definition unit 112 defines an observation position according to this instruction.

When the observation position is defined, the observation position definition unit 112 notifies the CPU 100 of the end of the process. CPU
100 is the tester resource setting position calculation unit 113
Start. The started tester resource setting position calculation unit 113 calculates the set value for the tester resource as follows.

The tester resource TG is used to generate an input event, and its setting position is the same as the setting position of the symbols 205 to 222 representing the input event in the event symbol database 105 shown in FIG. The strobe is used to define the timing for observing the output signal and the input / output signal, and the set position is determined by the observation position definition unit 1.
It is the same as the observation position defined in 12. The input / output switching TG is used to switch the input state and the output state of the input / output signal, and the setting position is the same as the setting position of the symbols 241 to 246 in FIG. In a test using a tester, the set values for these tester resources must be defined by the time from the symbol T0 at the tester operation reference time point due to the structure of the tester.

The tester resource setting position calculation unit 113
A tester resource setting position based on the IC operation specification defined by the operation specification defining unit 110, the T0 setting unit 111, and the observation position defining unit 112, the setting position of the symbol T0, and the observation position of the output signal and the input / output signal. Ask for. FIG. 10 shows an example of the obtained result of the tester resource setting position. In this example, from FIG. 9, the setting positions of the tester resources are 30 nsec from the first symbol T0 for the event symbols 1000 and 1001 of the input signal 1005, respectively.
70 nsec, and the event symbol 100
2,1003,1004, the next symbol T0
15 nsec, 30 nsec and 60 nsec. For the first observation position of the output signal, the first symbol T070 nsec, and for the next observation position,
The position is 45 nsec from the next symbol T0. For the observation position of the input / output signal, as in FIG. 9, the first symbol T0 is 80 nsec, and for the two event symbols, the next symbol T0 is 5 nsec. , 75
nsec.

When the calculation is completed, the operation specification definition unit 11
0, the T0 setting unit 111, the observation position definition unit 112, and the data of the operation specification of the IC shown in FIG.
14, the tester resource setting position calculation unit 113 notifies the CPU 100 that the calculation has been completed. CPU
Next, the test design unit 114 is activated.

The activated test design unit 114 refers to the tester specification database 104 and allocates tester resources to each signal as follows.

That is, first, the test design unit 114 calculates the operation specification definition unit 11 from the supplied operation specification data of the IC.
It interprets the operation of the input signal in the operation cycle defined by 0, determines a settable waveform mode, and refers to the tester resource database 108 to correspond to the setting position obtained by the tester resource setting position calculation unit 113. Distribute TG. If tester resources cannot be allocated to input signals due to lack of tester resources, the tester cannot test the IC. Therefore, the test design unit 114 first allocates the TG to the input signal, and if the allocation is not possible, stops the subsequent operation to prevent useless processing. Such an operation will be described below.

The input signal 1005 shown in FIG. 10 is composed of five symbols 1000 representing changes of the plurality of signals shown in FIG.
1001, 1002, 1003, and 1004, which are symbols representing changes in a plurality of signals shown in the index 201 in FIG. 2, respectively, and correspond to the symbols 218, 213, 214, 213, and 217, respectively. ing. The test design unit 114 decomposes these symbols into symbols representing a single signal change shown in the heading 200 of FIG. For a symbol representing a single signal change, a symbol ending in the high state is only a symbol starting in the high state, a symbol ending in the low state is only a symbol starting in the low state, and a symbol ending in the high impedance state is Only the symbols starting in the high impedance state can be adjacent to each other. The test design unit 114 determines an operation that a signal can take in each test cycle in consideration of the combination.

That is, in the case of the input signal 1005 shown in FIG.
There are at least a signal that remains high, a signal that changes from high to low, and a signal that remains low. In event 1001, at least a signal that changes from high to low and a signal that changes from low to high There is a signal to do.
From these and the combination of the above symbols, FIG.
In the first test cycle of, as shown in FIG.
Although the signal remains high at the event 1000 in FIG. 10, the signal changes from high to low at the event 1001, and the signal changes from high to low at the event 1000.
A signal changing from low to high at 1 and event 1000
In this case, there are three signals, that is, a signal that changes from low to high at the event 1001. The first of these three signals is represented by symbol D304 in FIG.
The third one is represented by symbol DU307 and the third one is represented by symbol U302. Therefore,
In the first test cycle of the input signal 1005, FIG.
In (a), three types of signal operations represented by symbols D, DU, and U shown in a frame 1100 can be taken.

Similarly, the input signal 100 shown in FIG.
In the next test cycle of 5, six operations represented by symbols DU, D, UDU, UD, DU, and U shown in a frame 1101 in FIG. 11 can be taken.

As described above, an operation that a signal can take in each test cycle is obtained. Next, the test design unit 114
Referring to the waveform mode operation database 106 shown in FIG. 3, a waveform mode in which the input signal can take the operation of all the symbols in the frame of FIG. 11 is selected for each test cycle.

That is, referring to FIG. 3, the test design unit 114 performs all three operations of symbols D, DU, and U for the first test cycle of the input signal 1005 shown in FIG. As the waveform mode, waveform modes E, F, and G are selected as shown in FIG.
In the next test cycle shown in, symbols DU, D, UD
As shown in FIG. 11D, the waveform modes F and G are selected as the waveform modes that take the six operations U, UD, DU, and U together. However, here, the waveform mode cannot be changed every test cycle, so that these two
As a waveform mode common to one test cycle, the test design unit 114 extracts the waveform modes F and G as candidates as shown in FIG.

Thus, the symbol 2 shown in FIG.
By inputting the operation specifications of the IC to the present embodiment using the reference numerals 05 to 246, the signal operation can be interpreted, and the waveform mode that can be set for the input signal is determined with reference to the tester specification database 104 (FIG. 1). be able to.

Next, the test design unit 114 refers to the TG distribution rule database 107 shown in FIG. 4 and distributes the TGs defining the operation timings of the extracted waveform modes F and G as follows. Determine if it is possible.

That is, as described above, a symbol representing a change in a plurality of signals is decomposed into a symbol representing a change in a single signal. As shown in FIGS.
The timing of the event at each symbol of
As shown by the dotted lines, 1200, 1201, 1202, 1
In the case of 203 and 1204, the same TG must be allocated to events occurring at the same timing.

Therefore, it is now assumed that the input signal 1005
Suppose that the waveform mode F is set among the selected waveform modes. Then, referring to the TG distribution rule database 107 shown in FIG. 4, these waveform modes are tentatively named F1, F2, F3,..., F8 in order from the top as shown in FIG. Top symbol D
FIG. 4 shows the waveform mode F4 shown in FIG.
The waveform mode F1 is changed to the waveform mode F
2 correspond to the timing 12 in FIG.
TG1 can be allocated to the event on 00, and TG2 can be allocated to the event on the timing 1201. Similarly, in FIG. 12B, the waveform mode F8 is set for the first symbol DU from the top, the waveform mode F4 is set for the second symbol D, and the third symbol UD
U, waveform mode F7 for the fourth symbol UD, waveform mode F1 for the fifth symbol DU, and waveform mode F1 for the fifth symbol DU.
When the waveform mode F2 corresponds to the sixth symbol U, the event on the timing 1202 is TG
1, TG2 can be allocated to the event also at the timing 1203, and TG3 can be allocated to the event also at the timing 1204.

On the other hand, when the waveform mode G is set, the timing 1 is obtained regardless of which waveform G shown in FIG. 4 is used for the symbols D, DU, and U shown in FIG.
At 201, the same TG cannot be allocated. That is, in this waveform mode G, for the symbol DU, as shown in FIG.
Although TG3 is allocated to the symbol U (timing 1201), it is clear from FIG. 4 that TG3 cannot be allocated to the symbols D and U shown in FIG. Only TG1 can be allocated to these symbols D and U. Therefore, TG3 cannot be distributed to all events at timing 1201, and as a result, in waveform mode G,
It turns out that G cannot be allocated.

From the above, the test design unit 114
For this input signal 1005, a waveform mode F is set as a waveform mode, and timings 1200 and 12 are set as TG.
02 and TG1 at timings 1201 and 1203
2 and TG3 at timing 1204, respectively.

The test design unit 114 executes the above processing for all the defined input signals, finds a waveform mode that can be set for each input signal, and allocates TGs.

When the distribution of the tester resources to the input signal is successful, the test design unit 114 next applies the one output signal and the input / output signal whose observation position is defined by the observation position One appropriate strobe is allocated from the strobes 501 shown in the tester resource database 108. Regarding the output signal and the input / output signal for which the observation position is not defined, it is considered that the observation is not necessary, and the strobe is not distributed. When the observation positions are defined for the signals equal to or more than the number of strobes shown in FIG. 5, the test design unit 114 allocates one strobe to a plurality of signals and observes those signals at the same timing. Take measures such as reducing the required number of strobes.

Next, the test design unit 114 responds to one input / output signal of the operation cycle defined by the operation specification definition unit 110 by using the tester resource database 1 shown in FIG.
08 TG for input / output switching (for starting input state) and TG for input / output switching
(For ending the input state) are distributed one by one. If the operation specifications of the IC define input / output signals equal to or greater than the input / output switching TG shown in FIG.
Distributes the same input / output switching TG to a plurality of input / output signals and switches the input state and output state of those input / output signals at the same timing to reduce the number of necessary input / output switching TGs. Take countermeasures.

When the distribution of the tester resources is completed for all the signals, the test design unit 114 allocates the tester resources to the respective signals and sets the tester resources to the respective tester resources calculated by the tester resource setting position calculator 113. The value is displayed on the display device 103. FIG. 13 shows an example of the display.

In the figure, here, signal header 1
300, tester resource heading 1 for these signals
301, a set value (TS1) corresponding to the first cycle of the operation specification of the IC for these tester resources, a heading 1302 of the timing set, and a set value (TS1) corresponding to the second cycle of the operation specification of the IC for these tester resources
2) and the timing set header 1303 are displayed in a list. The operator can create a control program for the tester and select a tester to be used for the test based on the test design results.

As described above, the test design unit 114 receives the operation specification data of the IC obtained by the operation specification definition unit 110, the T0 setting unit 111, the observation position definition unit 112, and the tester resource setting position calculation unit 113. Further, since the tester resources are distributed by inputting the data of the tester resource database 108 separately from this, when changing the tester used for the IC test, the data of the IC operation specification data is changed. No change is required, and only the tester resource database 108 as shown in FIG. 5 needs to be changed. Therefore, it is not necessary to repeat the above processing from the beginning as a result of changing the tester.

FIG. 14 is an overall configuration diagram showing another embodiment of the test design apparatus according to the present invention, wherein 115 is a test pattern conversion unit, 116 is an operation cycle identification condition extraction unit,
117 is an operation cycle identification unit, 118 is a test pattern conversion unit, 119 is a test pattern storage memory, 120
1 is a test pattern, 121 is a memory for storing simulation results, and 122 is a simulation result.
Are given the same reference numerals.

Referring to FIG. 14, in this embodiment, in addition to the configuration of the embodiment shown in FIG. 1, test pattern conversion section 115 comprising operation cycle identification condition extraction section 116, operation cycle identification section 117 and test pattern conversion section 118. When,
It has a test pattern storage memory 119 and a simulation result storage memory 121.

Simulation result storage memory 121
Indicates a separately obtained simulation result. The test pattern conversion unit 115 operates when the tester resource distribution processing unit 109 completes the distribution of tester resources for all operation cycles of the IC, and uses the processing results to store the simulation result storage memory 1.
A test pattern is formed from the simulation results stored in 21.

Here, the operation cycle identification condition extraction unit 116 in the test pattern conversion unit 115 extracts information for distinguishing the operation cycles of the IC defined by the operation specification definition unit 110 in the tester resource distribution processing unit 109 from each other. The operation cycle identification unit 117 identifies the operation cycle of the IC from the simulation result in the simulation result storage memory 121 based on the information, and the test pattern conversion unit 118 determines the identified simulation result and the tester resource distribution. The test pattern is compared with the tester resource distribution result by the processing unit 109, and a test pattern is formed from the simulation result with reference to the tester specification database 104. Test pattern 12 created
0 is stored in the test pattern storage memory 119.

In this embodiment, the event symbol database 105 shown in FIG. 2 is used. The waveform mode operation database 106 shown in FIG. 15 is used. Where 1,0, P, N
Represents the type of application pattern in the operation of the input signal that the waveform mode can take during one test cycle. Further, the TG distribution rule database 107 and the tester resource database 108 use those shown in FIGS. 4 and 5, respectively.

Next, the operation of this embodiment will be described. However, this operation partially overlaps with the previous embodiment,
In order to facilitate understanding, the overlapping part will be described.

When this test design apparatus is started, the CP
U100 activates the operation specification definition unit 110 to define the operation cycle of the IC. The operation specification definition unit 110 first displays a menu of symbols of the event symbol database 105 shown in FIG. 2 on the display 103, for example, as shown in FIG. While watching such a display, the operator first uses the keyboard 101 or the pointing device 102 to input the signal names 601 and 6.
02 is defined as, for example, signal 1 and signal 2, and a symbol is selected from the symbol menu 600 and arranged on the screen.
Here, as in the embodiment shown in FIG. 1, it is assumed that signal 1 has two events and signal 2 has one event.

Next, the operator uses the keyboard 101 or the pointing device 102 to define the time between the preceding event 604 of signal 1 and the event 605 of signal 2. With this definition, the operation specification definition unit 1
10 opens a time relation definition window 603 on the screen,
Here, the defined time between the events 604 and 605 is displayed as, for example, 30 nsec.

By repeating the above operation, the operator defines one operation cycle of the IC, and assigns a name 606 to this operation cycle, for example, operation cycle 1. In the case of an IC having a plurality of operation cycles, as described above, the time between events is defined for each operation cycle, and a name is assigned to each operation cycle. This result is shown in FIG.
As in the embodiment shown in FIG.

When the operator has defined the operation specifications of the IC,
The operation specification definition unit 110 is activated and instructs the operator to define the setting position of the symbol T0. As a result, if the operator defines the time relationship between an arbitrary event and the symbol T0, the operation specifications of the IC shown in FIG. 7 become as shown in FIG. 8, as in the embodiment shown in FIG. It is displayed on the display device 103. Next, the observation position definition unit 112 is activated to instruct the operator to define the observation position of the signal. Using the keyboard 101 or the pointing device 102, the operator defines an observation position for observing the electrical state of the output signal and the input / output signal in FIG. The method of defining the observation position is the same as in the embodiment shown in FIG. When the observation positions are defined in the same manner as in the embodiment shown in FIG. 1, the observation positions are symbols 902 and 90 as shown in FIG.
3 is displayed.

Of course, even in this case, when the observation position is defined uniformly by the time from the output event position or uniformly by the time from the symbol T0, the operator instructs the observation position definition unit 112 to instruct the observation position definition unit 112. , The observation position definition unit 112 defines the observation position according to the instruction.

When the operator finishes defining the observation position, the tester resource setting position calculation unit 113 starts up, and calculates the setting value for the tester resource, as in the embodiment shown in FIG.
The calculation result shown in FIG. 10 is obtained. In this case, the tester resource TG is used to generate an input event (change of an input signal), and the setting position is the same as the setting position of the symbols 205 to 222 representing the input event in the event symbol database 105 of FIG. The strobe is used to define the timing for observing the output signal and the input / output signal. The set position is the same as the observation position defined by the observation position definition unit 112. The input / output switching TG
Is used to switch between the input state and the output state of the input / output signal, and the setting position is the same as the setting position of the symbols 241 to 246 in FIG. 2 representing the input / output switching event. In the test using the tester, Needless to say, the set values for these tester resources must be defined by the time from the tester operation reference time T0 due to the structure of the tester.

When the calculation is completed, the tester resource setting position calculation unit 113 sends the obtained tester resource setting value to the test design unit 114. Therefore, the test design unit 11
4 starts and refers to the tester specification database 104,
As in the embodiment shown in FIG. 1, tester resources are allocated to each signal.

When the distribution of the tester resources is completed for all the operation cycles of the IC, the CPU 100
The operation cycle identification condition extraction unit 116 of the test pattern conversion unit 115 is activated.

The operation cycle identification condition extraction unit 116 obtains conditions for identifying the operation cycles of the IC defined by the tester resource distribution processing unit 109. Now, it is assumed that the tester resource allocation processing unit 109 defines two operation cycles 1 and 2 shown in FIGS. 17 and 18, respectively, and allocates tester resources to each of them.

In operation cycle 1 shown in FIG.
The tester resources shown in boxes 1404 and 1405 are allocated to the signal 1 and the signal 2, respectively. The signal 1 is the position of the symbol shown by the box 1406 in the first test cycle and the symbol 1407 in the second test cycle. Observed at each location,
A timing set indicated by a frame 1402 is set in the first test cycle, and a timing set indicated by 1403 is set in the second test cycle. Then, the name of this operation cycle of operation cycle 1 is displayed in a frame 1401.

In operation cycle 2 shown in FIG.
Similarly, signals 150 and 15 are assigned to signal 1 and signal 2, respectively.
The tester resources indicated by 05 are allocated, and signal 1 is
Observed at the positions of symbols indicated by reference numerals 06 and 1507, timing sets indicated by boxes 1502 and 1503 are set in the first and second test cycles, respectively, and the name of the operation cycle called operation cycle 2 is displayed in the box 1501. You.

However, the signal 2 shown in FIG. 17 and FIG.
It is assumed that the input signal is composed of two input signals, and these signals are referred to as signals 21 and 22.

The operation cycle identification condition extracting section 116 obtains the identification conditions for the two operation cycles 1 and 2. In operation cycle 1, it is assumed that signal 1 changes from low to high 100 nsec after the signal 1 changes from high to low, and in operation cycle 2, 10 nsec after signal 1 changes from high to low in operation cycle 2, The state changes from low to high. The operation cycle identification condition extraction unit 116 detects these signal operations as operation cycle identification conditions, detects these as identification conditions 1 and 2 respectively, notifies the operation cycle identification unit 117, and ends the process. Next, the CPU 100 operates the operation cycle identification unit 11.
7 is started.

The activated operation cycle identification section 117 identifies the operation cycle of the IC from the simulation result using the identification condition 1 and the identification condition 2.

FIG. 19 shows an example of the simulation result 122 stored in the simulation result storage memory 121 of FIG. In the simulation results, the signal operation of the IC is described as time elapses, and FIG. 19 shows a part thereof. Here, signal 2 is signal 2
Since the input signal is composed of two input signals 1 and 22, the signal operations of these signals 21 and 22 are also shown.
The operation of signal 1 in the simulation result changes from high to low, changes from low to high 100 nsec later, changes from high to low again, and changes from low to high 10 nsec later. ing.

The operation cycle identification unit 117 converts the simulation result into an operation enclosed by a frame 1701 as shown in FIG. 20 based on the identification conditions 1 and 2 obtained by the operation cycle identification condition extraction unit 116. It identifies the cycle 1 part and the operation cycle 2 part surrounded by the frame 1702, notifies the test pattern conversion unit 118 of the identification result, terminates the process, and notifies the CPU 100 of this. The CPU 100 then executes a test pattern conversion unit 118
Start.

The started test pattern conversion unit 118
The identification result of the operation cycle identification unit 117 is compared with the tester resource allocation results shown in FIGS. 17 and 18 to generate a test pattern. First, a method of generating a test pattern corresponding to the operation cycle 1 will be described. I do.

The portion surrounded by the frame 1701 in FIG.
This corresponds to operation cycle 1 shown in FIG. As shown in FIG. 21, the test pattern conversion section 118 first sets the symbol T0 at the set position 18
01 to 1803 are obtained and divided into each test cycle.

Next, a timing set is obtained for each test cycle set by the symbol T0. In the operation cycle 1 of FIG. 17, since the timing sets TS1 and TS2 are set for the first and second test cycles, respectively, the timings corresponding to the first and second test cycles of the simulation result of FIG. The sets are TS1 and TS2 shown in frames 1806 and 1807, respectively.

Next, observation positions 1406 and 1407 of the signal 1 defined in FIG. 17 are obtained. In the simulation result of FIG. 21, this observation position corresponds to 1804 and 1805. From the electrical state of the signal 1 at this observation position, the expected value pattern of the signal 1 is “L” in the first test cycle and “H” in the second test cycle.

Next, the test pattern conversion section 118 obtains an application pattern of the signal 2 from the signal operation of the signal 2 during one test cycle with reference to the waveform mode operation database 106 shown in FIG. In FIG. 17, the waveform mode A is set as the waveform mode for the signal 2, and the signal in which the mode A is set is changed from low to high in one test cycle according to the waveform mode operation database 106 shown in FIG. The applied pattern is “1” when the state changes or remains high and the state does not change, and the applied pattern when the state changes from high to low or remains low and the state does not change is “0”. .

Therefore, from the simulation results shown in FIG. 21, the signal 21 changes from high to low in the first test cycle, and remains in the low state in the second test cycle. Therefore, the application pattern of the signal 21 is “0” in the first test cycle and “0” in the second test cycle. Further, since the signal 22 remains high in both the first and second test cycles, the application pattern of the signal 22 is “1” in the first and second test cycles.

By the above processing, the expected value pattern, the application pattern, and the timing set of the portion corresponding to the operation cycle 1 are obtained. The result is shown in FIG. The test pattern conversion unit 118 performs the same processing on a portion corresponding to the operation cycle 2 shown by the frame 1702 in the simulation result shown in FIG. This result is shown in FIG.
Shown in

The test pattern obtained by the above processing is as shown in FIG. Test pattern converter 1
Reference numeral 18 adds, as a comment, the name of the operation cycle shown in the frames 2101 and 2102 to the test pattern when the operator needs it. Thereby, the operator can easily understand the test pattern.

The test pattern conversion section 118 repeats the above processing for all the simulation results to create these test patterns. When this creation operation is completed, the obtained test pattern is stored in the test pattern storage memory 119, and the CPU 100 is notified of the end of the process. The CPU 100 displays the end of the test design on the display 1
03, and the process is terminated.

[0109]

As described above, according to the present invention,
Test design is performed by automatically considering the specifications of a tester that uses the operation specifications of the IC created at the time of IC design as input data for the test, so that the test designer does not need to be familiar with the specifications of the tester. The execution and correction of the test design can be performed easily and in a short time as compared with the case where the test design is performed by using the simulation result that takes a long time to execute as input data.

According to the present invention, what defines the operation specifications of the IC in operation cycle units is used as input data, and tester resources are allocated with reference to a tester specification database in which tester specifications are described. Tester resources can be allocated in a shorter time than when a result of a time-consuming simulation is used as input data.

Further, according to the present invention, a simulation result can be automatically converted into a test pattern in IC operation cycle units based on the distribution result and the defined IC operation cycle.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of a test design apparatus according to the present invention.

FIG. 2 is an explanatory diagram showing an example of an event symbol database in FIG.

FIG. 3 is an explanatory diagram showing an example of a waveform mode operation database in FIG. 1;

FIG. 4 is an explanatory diagram showing an example of a TG distribution rule database in FIG.

FIG. 5 is an explanatory diagram showing an example of a tester resource database in FIG.

FIG. 6 is a diagram illustrating a display example of a display screen of a display device when the operation specification definition unit in FIG. 1 is activated.

FIG. 7 is an IC defined by an operation specification definition unit in FIG.
FIG. 7 is a diagram showing a display example of the operation specifications of FIG.

FIG. 8 is a diagram showing a display example of an operation specification of an IC in which a symbol T0 is set in the embodiment shown in FIG. 1;

9 is a diagram illustrating a display example of an IC operation specification in which a signal observation position is defined by an observation position definition unit in FIG. 1;

FIG. 10 is a diagram illustrating an example of a calculation result of a tester resource setting value calculated by a tester resource setting position calculation unit in FIG. 1;

FIG. 11 is an explanatory diagram of waveform mode selection by a test design unit in FIG. 1;

FIG. 12 is an explanatory diagram of distribution of timing generators by a test design unit in FIG. 1;

FIG. 13 is an explanatory diagram of a test design result according to the embodiment shown in FIG. 1;

FIG. 14 is an overall configuration diagram showing another embodiment of the test design apparatus according to the present invention.

FIG. 15 is an explanatory diagram illustrating an example of a waveform mode operation database in FIG. 14;

16 is a diagram illustrating a display example of a display screen of a display device when the operation specification definition unit in FIG. 14 is activated.

FIG. 17 is a diagram showing a test design result according to the embodiment shown in FIG. 14 described in an operation cycle of the IC.

18 is a diagram showing a test design result according to the embodiment shown in FIG. 14 described in another operation cycle of the IC.

19 is an explanatory diagram illustrating an example of a simulation result stored in a simulation result storage memory in FIG. 14;

20 is an explanatory diagram for identifying an operation cycle from the simulation result shown in FIG. 19 by the operation cycle identification unit 117 in FIG. 14;

21 is a diagram showing a signal observation position and a symbol T0 on the simulation result shown in FIG. 20;

FIG. 22 is a diagram showing an application pattern, an expected value pattern, and a timing set on the simulation result shown in FIG. 21;

FIG. 23 is a diagram showing an application pattern, an expected value pattern, and a timing set of the next operation cycle on the simulation result shown in FIG. 22;

24 is a diagram showing a test pattern created from the display data shown in FIG. 23 by the test pattern conversion unit in FIG.

[Explanation of symbols]

 Reference Signs List 100 Central processing unit 101 Keyboard 102 Pointing device 103 Display device 104 Tester specification database 105 Event symbol database 106 Waveform mode operation database 107 TG allocation rule database 108 Tester resource database 109 Tester resource allocation processing unit 110 Operation specification definition unit 111 T0 setting unit 112 Observation position definition unit 113 Tester resource setting position calculation unit 114 Test design unit 115 Test pattern conversion unit 116 Operation cycle identification condition extraction unit 117 Operation cycle identification unit 118 Test pattern conversion unit 119 Test pattern storage memory 120 Test pattern 121 Simulation result storage Memory required 205-246 Event symbol 302-309 Operation symbol 00 events symbol menu 606 operating cycle name of

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-72278 (JP, A) JP-A-4-276571 (JP, A) JP-A-4-230876 (JP, A) JP-A-1- 250874 (JP, A) JP-A-63-275971 (JP, A) JP-A-63-76022 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28 G06F 17 / 50 G06F 11/22

Claims (14)

(57) [Claims] 1. An event symbol database for event symbols representing events which are signal changes, and an IC
A waveform mode operation database indicating a relationship between a waveform mode and a signal operation of a tester used for inspection of the tester; a timing generator distribution rule database indicating a relationship between a waveform mode and a timing generator defining operation timing of the waveform mode; A first tester resource database indicating tester resources, the tester specification database describing tester specifications; and the event symbols are used to define an operation specification of the IC under test as a signal change for each operation cycle. Means, second means for dividing the defined operation specification of the IC under test at a predetermined cycle, and an observation position of an electrical state of a signal in the operation specification of the IC under test divided at the cycle Third means for defining the event symbol and the event symbol and the observation position set by the first and third means. A test means for determining a setting position of a tester resource, and a fifth means for performing a test design of the IC under test by referring to information on the specifications of the tester. Design equipment. 2. The event symbol according to claim 1, wherein, for each input signal, output signal, and input / output signal, an event symbol representing a change in a single signal and an event symbol representing a change in a plurality of signals. A test design device characterized by being divided. 3. The test design apparatus according to claim 1, wherein the waveform mode operation database is configured such that signal operations that the tester can take in the waveform mode are defined in a table format using the event symbols. . 4. The test design according to claim 1, wherein in the timing generator distribution rule database, a relationship between the waveform mode and the timing generator is defined in a table format using the event symbols. apparatus. 5. The test design apparatus according to claim 3, wherein the tester used for testing the IC under test can be changed by changing the table. 6. The apparatus according to claim 1, wherein the first means associates an operation that the signal can actually take with an operation represented by the symbol on a one-to-one basis, and A test design apparatus wherein an operation specification of a test IC is defined as a change in a signal. 7. The test according to claim 1, wherein the first means defines an operation specification of the IC based on the symbol and a time relationship between the symbol. Design equipment. 8. The method according to claim 1, wherein the third means sets the observation position in terms of time in an operation specification of the IC under test defined by the first means. A test design apparatus characterized by being defined by a position. 9. The method according to claim 8, wherein the reference time of the temporal position is a start time of a cycle including the observation position in the cycle set by the second means, or an event position. Test design equipment characterized by the following. 10. The apparatus according to claim 1, wherein said fourth means comprises a setting position of each of said tester resources and a period set by said second means including said setting position. A test design apparatus for determining a time from a start time. 11. The IC according to claim 1, wherein the fifth means is configured to determine the IC to be inspected defined by the first means based on information of the waveform mode operation database. A tester set in the tester resource database at a set position of the tester resource determined by the fourth means based on the information of the timing generator distribution rule database by selecting a waveform mode that can be set for the operation specification. A test design apparatus characterized by allocating resources. 12. The first storage device for storing a simulation result according to claim 1, 6, 7, 8, 9, 9, 10 or 11, and the second storage device for storing a created test pattern. A first processing unit that uses the fifth output data as input data and obtains a condition for identifying the operation cycles from each other; a second processing unit that identifies an operation cycle from the simulation result based on the identification condition A processing unit and the simulation result in which the operation cycle is identified,
A third processing unit that converts the test pattern into a test pattern with reference to a tester resource distribution result by the fourth unit;
A test design apparatus storing the obtained test pattern in the second storage device. 13. The waveform mode operation database according to claim 12, wherein a relationship between a signal operation and a test pattern that can be taken during one test cycle of the waveform mode in the tester is defined in a table format using the event symbols. A test design apparatus characterized by being performed. 14. The test design apparatus according to claim 12, wherein the third processing unit adds an operation cycle name as a comment to the obtained test pattern.