JP3102412B2 - High breakdown voltage thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-breakdown-voltage thin-film transistor, and more particularly, to fluctuations in a threshold voltage of an offset region and a main gate electrode even when a high voltage is applied to a drain region and a sub-gate electrode. It does not cause dielectric breakdown between the gate electrode and the sub-gate electrode, so it can be operated at a high drain voltage, and the sub-gate voltage can be controlled at a high voltage to prevent a decrease in the on-current in the offset region And a high-breakdown-voltage thin-film transistor.

[0002]

2. Description of the Related Art Conventionally, high breakdown voltage thin film transistors have been
For example, IEEE ELECTRONDEVICES L
ETTERS, vol. 11, No. 6, p. 244,
FIG. As shown in FIG. 1, it is used to enable operation even when a high drain voltage is applied.

A conventional high-breakdown-voltage thin-film transistor 91 as disclosed in Japanese Patent Laid-Open Publication No.
For example, as shown in FIG. 9, a base oxide film 9 is formed on an insulating or semi-insulating substrate such as a glass substrate or a semiconductor substrate 92.
In the semiconductor thin film 94 formed through the gate electrode 3, a source region 95 doped with impurities and an active layer 9 forming a channel are formed.
6, an offset region 97 not doped with an impurity or having a low impurity concentration and a drain region 98 doped with an impurity are sequentially formed and formed;
A main gate electrode 100 formed thereon with a first insulating film 99 interposed therebetween, and a second insulating film 1 formed on the offset region 97.
The sub-gate electrode 102 is formed at a position higher than the main gate electrode 100 with respect to the semiconductor thin film 94.

The high breakdown voltage thin film transistor 91 can achieve a high breakdown voltage of, for example, 400 volts without the sub-gate electrode 102 by providing the offset region 97 having a lower impurity concentration than the source region 95 and the drain region 98. Yes, but the offset area 97
Is required to be longer than the width of the depletion layer from the drain region 98. Therefore, when the sub-gate electrode 102 is not provided, the resistance of the offset region 97 increases, and the on-current decreases. Therefore, when the sub-gate electrode 102 is provided and a drain voltage is set to 100 V, for example, when a voltage of about 60 V is applied to the sub-gate electrode 102, an inversion layer is formed in the offset region 97, and the offset region becomes It is said that the resistance is reduced, and the peak of the electric field is formed at two points, for example, at the boundary between the active layer 96 and the offset region 97 and at the boundary between the offset region 97 and the drain region 98, and the breakdown voltage characteristics are also optimized. Have been done.

However, if the width of the sub-gate electrode 102 for forming the inversion layer is small, the on-current flowing through the offset region 97 decreases, so that the sub-gate electrode 102 is also expected to have a margin for misalignment in the lithography process. The main gate electrode 10 is about 1 μm.
In this case, since the shortest distance between the main gate electrode 100 and the sub-gate electrode 102 is equal to the thickness of the second insulating film 101, for example, about 700 nanometers, the on-current is reduced. When the voltage applied to the sub-gate electrode 102 is increased to increase the voltage, a high electric field is generated between the main gate electrode 100 and the sub-gate electrode 102, charges are injected into the second insulating film 101, and the offset region There is a problem that the threshold voltage of the transistor 97 fluctuates or dielectric breakdown occurs between the main gate electrode 100 and the sub-gate electrode 102.

FIGS. 7 and 8 of JP-A-57-149773 show two sub-gate electrodes 31 and 5 respectively.
1 is disclosed, the sub-gate electrodes 31 and 51 are disposed at the same height from the semiconductor thin film 22 and the sub-gate electrodes 31 and 51 are disposed at the same height.
Has a structure extending above the main gate electrode 6, so that the occurrence of dielectric breakdown between the main gate electrode 6 and the sub-gate electrode 31 cannot be prevented. Since it is connected to the same voltage supply sources 9 and 11 as the drain electrode 8, any voltage setting of the sub-gate electrodes 31 and 51 is impossible.
Therefore, it is impossible to harmonize the control of the electric field and the on-current, and it is necessary to provide an insulating gap between the sub-gate electrodes 31 and 51. However, there is a problem in that an area is formed.

[0007]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art and to reduce the threshold voltage of the offset region even when a high voltage is applied to the drain region and the sub-gate electrode. It does not cause fluctuation or dielectric breakdown between the main gate electrode and the sub-gate electrode. Therefore, it can operate even when a high drain voltage is applied. An object of the present invention is to provide a high-breakdown-voltage thin film transistor capable of preventing a decrease in on-current.

[0008]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration in order to achieve the above object.

That is, as a first aspect according to the present invention,
A source region, an active layer, a first offset region and a drain region arranged and formed in the semiconductor thin film;
A main gate electrode formed on the active layer via an insulating film, and a first sub-gate electrode formed on the first offset region via an insulating film; A high-breakdown-voltage thin-film transistor in which a first sub-gate electrode is disposed at a position higher than the main gate electrode; and a second offset formed between the active layer and the first offset region in the semiconductor thin film. Region, and a second sub-gate electrode formed on the second offset region via an insulating film, wherein the first sub-gate electrode and the second sub-gate electrode are respectively the main gate electrode, the source region, and the drain region. And the second sub-gate electrode is higher than the first sub-gate electrode with respect to the semiconductor thin film. It is a high-breakdown-voltage thin-film transistor arranged in a position.

According to a second aspect of the present invention, there is provided the high-breakdown-voltage thin-film transistor according to the first aspect, further comprising a third offset region formed between the first offset region and the drain region. A third sub-gate electrode formed on the third offset region via an insulating film, wherein the third sub-gate electrode is connected to a voltage supply source different from the main gate electrode, the source region, and the drain region. The high-breakdown-voltage thin film transistor is connected, and the third sub-gate electrode is arranged at a position higher than the first sub-gate electrode with respect to the semiconductor thin film.

According to a third aspect of the present invention, there is provided the high-breakdown-voltage thin-film transistor according to the second aspect described above, further comprising an array formed between the source region and the active layer from the side closer to the source region. A fourth offset region and a fifth offset region, a fourth sub-gate electrode formed on the fourth offset region via an insulating film,
A fifth sub-gate electrode formed on the offset region via an insulating film, and the fourth sub-gate electrode and the fifth
The sub-gate electrode is connected to a voltage source different from the main gate electrode, the source region and the drain region, respectively, and the fourth sub-gate electrode is positioned higher than the main gate electrode with respect to the semiconductor thin film. ,
The high-breakdown-voltage thin-film transistor is arranged such that the fifth sub-gate electrode is higher than the fourth sub-gate electrode.

According to a fourth aspect of the present invention, there is provided a high-breakdown-voltage thin-film transistor according to the third aspect, further comprising a sixth offset region formed between the source region and the fourth offset region. A sixth sub-gate electrode formed on the sixth offset region via an insulating film, wherein the sixth sub-gate electrode is connected to a voltage supply source different from the main gate electrode, the source region, and the drain region. A high-breakdown-voltage thin film transistor which is connected to the semiconductor thin film and has the sixth sub-gate electrode disposed at a position higher than the fourth sub-gate electrode.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The high-breakdown-voltage thin film transistor according to the present invention employs the above-described configuration, and is characterized in that a second offset region is interposed between an active layer and a first offset region. Therefore, the first sub-gate electrode formed on the first offset region is isolated from the main gate electrode, and the second sub-gate electrode on the second offset region is arranged at a position higher than the first sub-gate electrode. Since it is more isolated from the main gate electrode than the conventional sub-gate electrode, even if a high electric field is generated between the main gate electrode and the first sub-gate electrode or the second sub-gate electrode, the threshold voltage of the offset region This makes it difficult to cause fluctuations and dielectric breakdown, so that each sub-gate electrode can be controlled at a high voltage. Further, since the first sub-gate electrode and the second sub-gate electrode are connected to different voltage supply sources from the main gate electrode, the source region and the drain region, respectively, the first sub-gate electrode and the second sub-gate electrode are independently formed Voltage control is possible, so that the electric field and the on-current can be freely controlled. Therefore, even if the device is operated at a high drain voltage of, for example, 200 volts, dielectric breakdown between gate electrodes and fluctuation of the threshold voltage in the offset region are prevented, and the on-current is also reduced to, for example, 1
It can be suppressed to 0% or less.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a thin-film transistor according to the present invention. That is, FIG. 1 is a cross-sectional view showing the structure of one specific example of the high-breakdown-voltage thin film transistor 1 according to the first embodiment of the present invention. By forming the offset region 7, the source region 5, the active layer 6, the second offset region 7, the first offset region 8, and the drain region 9 are sequentially formed in the semiconductor thin film 4,
The insulating films 10, 12, 1 and 2 are formed on the second offset region 7.
4, a second sub-gate electrode 15 is formed,
The first sub-gate electrode 13 formed on the first offset region 8 via the insulating films 10 and 12 with respect to the semiconductor thin film 4 is formed on the active layer 6 via the insulating film 10. The second sub-gate electrode 15 is arranged at a position higher than the main gate electrode 11 and higher than the first sub-gate electrode 13 formed on the first offset region 8 via the insulating films 10 and 12. .

In the high-breakdown-voltage thin film transistor according to the present invention, from the viewpoint of preventing dielectric breakdown, the second sub-gate electrode 15 is, for example, as shown in FIG. It is preferable to be arranged more apart than one sub-gate electrode 13. In addition, the second sub-gate electrode 15 is located above the main gate electrode 11 and the first sub-gate electrode 11 so as not to generate an inversion layer blank area which causes a decrease in on-current, and in consideration of misalignment in a lithography process. Above the sub-gate electrode 13, for example, 1
It is preferable that the first sub-gate electrode 13 has a portion extending about 1 μm, for example, above the drain region 9.

Further, the second offset region used in the high breakdown voltage thin film transistor according to the present invention has a boundary between each of the active layer 6 and the first offset region 8 as shown in FIG. 1, for example. The width between the boundary surfaces is 200 volts, as is clear from the graph of the relationship between the width of the second offset region and the on-state current and the withstand voltage during the operation of the transistor shown in FIG. In order to achieve high withstand voltage and reduce the on-current within 10%,
The thickness is preferably 1 to 5 μm. In addition, it is preferable that the first offset region 8 and the drain region 9 are similarly provided so as to be in contact with each other.

The first sub-gate electrode 13 and the second
The sub-gate electrode 15 is connected to a voltage source (Vs) 16 of the source region 4 and a voltage source (Vs) of the main gate electrode 11, respectively.
g) 18 and voltage source (Vd) 17 for drain region 9
2 are connected to a voltage supply source (Vsga) 19 and a voltage supply source (Vsgb) 20 which are different from each other so that the voltage can be controlled independently. For example, as shown in FIG. ) Is 100 volts, the first sub-gate electrode 13 and the second sub-gate electrode 15
Is controlled at the same constant voltage, for example, 70 volts, in order to prevent congestion of wiring for supplying the voltage,
For example, as shown in FIG.
It is preferable that a wiring 22 for electrically connecting the electrodes 13 and 15 is formed in the insulating film 14 between the first sub-gate electrode 15 and the second sub-gate electrode 15.

Next, FIG. 3 is a sectional view showing the structure of one specific example of the high-breakdown-voltage thin-film transistor 31 according to the second embodiment of the present invention, in which the same elements as those in FIG.
In the figure, a third offset region 32 is provided between the first offset region 8 and the drain region 9 in addition to the specific example shown in FIG.
Is formed, the source region 5, the active layer 6, the second offset region 7, the first offset region 8, the third offset region 32, and the drain region 9 are sequentially formed in the semiconductor thin film 4. The third sub-gate electrode 33 is formed on the 3 offset region 32 via the insulating films 10, 12, and 14.
The sub-gate electrode 33 is arranged at a position higher than the first sub-gate electrode 13 formed on the first offset region 8 via the insulating films 10 and 12.

From the viewpoint of preventing dielectric breakdown, the third sub-gate electrode 33 is arranged at a greater distance from the drain region 9 than the first sub-gate electrode 13 as shown in FIG. 3, for example. Things are preferred. Further, the third sub-gate electrode 15 is located above the first sub-gate electrode 13 and the drain so as not to generate an inversion layer blank area which causes a decrease in on-current and taking into account misalignment in a lithography process. It is preferable to have, for example, portions each extending about 1 μm above the region 9.

Further, the third offset region used in the high breakdown voltage thin film transistor according to the present invention has a boundary between the first offset region 8 and the drain region 9 as shown in FIG. 3, for example. The width between each of the boundary surfaces is as high as 200 volts at the time of the transistor operation, and the reduction in the on-current is within 10%, as in the case of the second offset region 7. For this reason, the thickness is preferably 1 to 5 μm.

The third sub-gate electrode 33 is connected to a voltage source (Vs) 16 of the source region 4, a voltage source (Vg) 18 of the main gate electrode 11, and a voltage source (Vd) 17 of the drain region 9. Are different voltage sources (Vsg
c) It is connected to 34 so that the voltage can be independently controlled. Also, in the example of FIG. 3, as shown in FIG. 4, when the drain voltage (Vd) is 100 volts, for example, the first sub-gate electrode 13 and the second
Is controlled at the same constant voltage, for example, 70 volts, in order to prevent congestion of wiring for supplying the voltage,
For example, as shown in FIG.
It is preferable that a wiring 42 for electrically connecting the electrodes 13 and 15 is formed in the insulating film 14 between the first sub-gate electrode 15 and the second sub-gate electrode 15. Alternatively, instead of the wiring 42, a wiring for electrically connecting the first sub-gate electrode 13 and the third sub-gate electrode 33 may be formed, or both the wiring and the wiring 42 may be formed. Alternatively, a wiring for electrically connecting the second sub-gate electrode 15 and the third sub-gate electrode 33 may be further formed.

1 to 4 show an example in which an offset region and a sub-gate electrode are sequentially added between the active layer 6 and the drain region 9, but the high breakdown voltage thin film transistor according to the present invention is In some cases, the applied voltage between the region 9 and the source region 5 is inverted and used.
It is preferable to sequentially add offset regions and sub-gate electrodes symmetrically with respect to the main gate electrode 11 in the same manner as in the example of FIG. 1, and in FIG. 5, the same elements as those in FIG. 1 are represented by the same reference numerals. FIG. 9 is a cross-sectional view showing a structure of one specific example of a high-breakdown-voltage thin film transistor 51 according to a third embodiment of the present invention. In the drawing, in addition to the specific example shown in FIG. The fourth offset region 52 and the fifth offset region 53 are formed therebetween, so that the source region 5, the fourth offset region 52, and the fifth
The offset region 53, the active layer 6, the second offset region 7, the first offset region 8, the third offset region 32, and the drain region 9 are sequentially formed and the insulating films 10 and 12 are formed on the fourth offset region 52. And the fifth sub-gate electrode 55 on the fifth offset region 53 via the insulating films 10, 12 and 14.
The fourth sub-gate electrode 54 is positioned higher than the main gate electrode 11 formed on the active layer 6 via the insulating film 10 with respect to the semiconductor thin film 4. The fifth sub-gate electrode 55 is arranged at a position higher than the fourth sub-gate electrode 54.

From the viewpoint of preventing dielectric breakdown, the fifth sub-gate electrode 55 is connected to the fourth sub-gate electrode 54 with respect to the main gate electrode 11 as shown in FIG.
It is preferable that they are spaced apart from each other. Further, the fifth sub-gate electrode 55 is located above the fourth sub-gate electrode 54 and the main sub-electrode 54 so as not to generate an inversion layer blank area which causes a decrease in on-current, and in consideration of misalignment in a lithography process. It is preferable that each of the first and second sub-gate electrodes 54 has a portion extending above the gate electrode 11 by, for example, about 1 μm.
It is preferable to have a portion extended, for example, by about 1 μm above.

Further, the fifth offset region used in the high breakdown voltage thin film transistor according to the present invention has a boundary between the fourth offset region 52 and the active layer 6 as shown in FIG. 5, for example. The width between each of the boundary surfaces is as high as 200 volts at the time of the transistor operation, and the reduction in the on-current is within 10%, as in the case of the second offset region 7. For this reason, the thickness is preferably 1 to 5 μm. It is preferable that the fourth offset region 52 and the source region 5 are similarly provided so as to be in contact with each other.

Also, the fourth sub-gate electrode 54 and the fifth
The sub-gate electrode 55 is connected to a voltage source (Vs) 16 of the source region 4, a voltage source (Vg) 18 of the main gate electrode 11, and a voltage source (Vg) of the drain region 9, respectively.
d) It is connected to a voltage supply source (Vsgd) 56 and a voltage supply source (Vsge) 57 different from 17 so that the voltage can be controlled independently. Also, in the case of the example of FIG.
And the fourth sub-gate electrode 5 as in the example shown in FIG.
A wiring for electrically connecting the fourth and fifth sub-gate electrodes 55 may be formed.

FIG. 6 is a sectional view showing the structure of one specific example of a high-breakdown-voltage thin film transistor 61 according to a fourth embodiment of the present invention, in which the same elements as those in FIG.
In the figure, the third offset region 32 and the third sub-gate electrode 33 as shown in FIG. 3 are formed in the specific example shown in FIG. 5, and the source region 5 and the fourth offset region 52 The source region 5, the sixth offset region 62, the fourth offset region 52, the fifth offset region 53, the active layer 6, and the second offset region 7 are formed in the semiconductor thin film 4 by forming the sixth offset region 62 therebetween. , The first offset region 8, the third offset region 32, and the drain region 9 are sequentially formed and formed.
A sixth sub-gate electrode 63 is formed thereover via insulating films 10, 12, 14.
The sixth sub-gate electrode 63 is arranged at a position higher than the fourth sub-gate electrode 54 formed on the fourth offset region 52 via the insulating films 10 and 12.

From the viewpoint of preventing dielectric breakdown, the sixth sub-gate electrode 63 is arranged more distant from the source region 5 than the fourth sub-gate electrode 54, as shown in FIG. Things are preferred. The sixth sub-gate electrode 63 is located above the fourth sub-gate electrode 54 and the source so as not to generate an inversion layer blank area which causes a decrease in on-current, and taking account of misalignment in a lithography process. It is preferable to have, for example, portions each extending about 1 μm above the region 5.

Further, the sixth offset region used in the high breakdown voltage thin film transistor according to the present invention has a boundary between the fourth offset region 52 and the source region 5 as shown in FIG. 6, for example. The width between each of the boundary surfaces is as high as 200 volts at the time of the transistor operation, and the reduction in the on-current is within 10%, as in the case of the second offset region 7. For this reason, the thickness is preferably 1 to 5 μm.

The sixth sub-gate electrode 63 is connected to a voltage source (Vs) 16 of the source region 4, a voltage source (Vg) 18 of the main gate electrode 11, and a voltage source (Vd) 17 of the drain region 9. Are different voltage sources (Vsg
f) It is connected to 64 so that the voltage can be controlled independently. Also, in the case of the example of FIG.
Wiring for electrically connecting any two or three of the electrodes 4, 55, 63 may be formed.

In the examples shown in FIGS. 1 to 6, the semiconductor thin film 4 is formed on the glass substrate 2 with the base oxide film 3 interposed therebetween. Is not limited thereto, and may be any of an insulating or semi-insulating substrate, a silicon semiconductor substrate, and the like, and the base oxide film 3 may or may not be another insulating film.

In the semiconductor thin film 4, the source region 5 and the drain region 9 are n-type or p-type, respectively.
For example, the active layer 6 and each of the offset regions 7, 8, 32, 52, 53, and 62 have impurity impurities in the order of 10 ²¹ / cm ^3. Is not contained, or even if it is contained, 10 ¹⁵ /
Preferably, it is contained in an amount on the order of cm ³ or less.

Further, in the examples shown in FIGS. 1 to 6, insulating films 10, 12, 14 and electrodes 11,
13 and 15 are alternately stacked, so that each electrode 11, 1
Although the heights of the electrodes 3 and 15 are adjusted, the shapes and materials of these electrodes and the insulating film can be appropriately selected without departing from the essence of the present invention.

Next, a method of manufacturing the high breakdown voltage thin film transistor according to the present invention will be described. FIG. 7 shows a specific example of a method for manufacturing a high-breakdown-voltage thin film transistor according to the present invention.
FIG. 7A is a process explanatory diagram for explaining a production example of the high breakdown voltage thin film transistor shown in FIG. 1, for example. In FIG. A base oxide film 72 made of silicon oxide for preventing diffusion of impurities from the glass substrate 71 is formed. On the base oxide film 72, for example, 100 nm thick amorphous silicon is formed by low pressure CVD. Semiconductor thin film 73 is formed,
For example, a semiconductor thin film 73 made of polycrystalline silicon containing no impurity and having a desired pattern shape is formed by crystallization and patterning by an excimer laser beam. On the film 72, a film thickness of 1
A first insulating film 74 made of 00 nanometer silicon oxide is formed.

Next, as shown in FIG. 7B, the first insulating film 74 is formed, for example, by a low pressure CVD method and contains about 10 ²¹ / cm ^{3 of} phosphorus and has a thickness of 50 nm. A layered structure of a layer made of n-type polycrystalline silicon and a tungsten silicide layer having a thickness of 200 nm formed by, for example, a sputtering method is further patterned to form a main gate electrode 79. In the semiconductor thin film 73 below the electrode 79, an active layer 7 for forming a channel covered with the main gate electrode 73 is provided.
6, and a portion of the semiconductor thin film 73 is doped with, for example, an ion beam method using, for example, a phosphorus ion 81 by using a resist 80, so that phosphorus is added to about 10 ²¹ / cm 2.
A source region 75 and a drain region 78 containing ³ are formed.

Next, as shown in FIG. 7C, after the resist 80 is removed, the low voltage C is applied on the first insulating film 74 so as to cover the main gate electrode 80.
A 200 nm-thick silicon oxide second insulating film 82 is formed by the VD method, and a 200 nm-thick aluminum film is further formed on the second insulating film 82 by, for example, a sputtering method. Formed and patterned to form a first sub-gate electrode 85.
A first offset region 84 covered with the first sub-gate electrode is provided in a portion of the semiconductor thin film 73 below the sub-gate electrode 85, that is, in a portion adjacent to the drain region 78.
Is defined.

Next, as shown in FIG. 7D, a film thickness of 400 is formed on the second insulating film 82 by, for example, a plasma CVD method so as to cover the first sub-gate electrode 85.
Third insulating film 86 made of nanometer silicon nitride
Further, a 200-nm-thick aluminum film is formed on the third insulating film 86 by, for example, a sputtering method, and is patterned to form a second sub-gate electrode 87. A second offset region 83 covered with the second sub-gate electrode is defined in the semiconductor thin film 73 below the sub-gate electrode 87, that is, between the active layer 76 and the first offset region 84. The second sub-gate electrode 87 is connected to the first sub-gate electrode 8
It is preferable to form portions extending with a width of 1 μm or less above the main gate electrode 79 and above the main gate electrode 79, respectively, and the first sub-gate electrode 85 is 1 μm or less above the drain region 78. It is preferable to form a stretched portion with a width of. Further, the active layer 7
6, second offset area 83, first offset area 8
4. It is preferable that the drain regions are provided so as to be in contact with each other.

The other offset regions and sub-gate electrodes shown in FIGS. 2 to 6 can be formed by the same method as in the example shown in FIG.

[0038]

Since the high breakdown voltage thin film transistor according to the present invention employs the above-described technical configuration, in each of the above embodiments, any one of the source region, the main gate electrode, and the drain region is connected to the first to the first. 6 Even if a high electric field is generated between any of the sub-gate electrodes, fluctuations in the threshold voltage of the offset region and dielectric breakdown are unlikely to occur, so that each sub-gate electrode can be controlled at a high voltage. Become. Further, since the first to sixth sub-gate electrodes are connected to voltage supply sources different from the main gate electrode, the source region, and the drain region, respectively, voltage control can be performed independently of each other. Flexible control becomes possible. Therefore, even when operated at a high drain voltage of, for example, 200 volts, dielectric breakdown between gate electrodes,
A change in the threshold voltage in the offset region is prevented, and the on-current can be suppressed to, for example, 10% or less.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a specific example of a high breakdown voltage thin film transistor according to the present invention.

FIG. 2 is a cross-sectional view illustrating a specific example of a high breakdown voltage thin film transistor according to the present invention.

FIG. 3 is a cross-sectional view illustrating a specific example of a high breakdown voltage thin film transistor according to the present invention.

FIG. 4 is a cross-sectional view illustrating a specific example of a high breakdown voltage thin film transistor according to the present invention.

FIG. 5 is a cross-sectional view illustrating a specific example of a high breakdown voltage thin film transistor according to the present invention.

FIG. 6 is a cross-sectional view illustrating a specific example of a high breakdown voltage thin film transistor according to the present invention.

FIG. 7 is a cross-sectional view for explaining a step of a specific example of the method for manufacturing the high withstand voltage thin film transistor according to the present invention.
7A illustrates a state in which the semiconductor thin film 73 is formed, FIG. 7B illustrates a state in which the main gate electrode 79 and the like are formed, FIG. 7C illustrates a state in which the first sub-gate electrode 85 is formed, and FIG. The state where the second sub-gate electrode 87 is formed is shown.

FIG. 8 is a graph showing the relationship between the width of the second offset region 7 of the high breakdown voltage thin film transistor according to the present invention and the standardized on-current (A) and breakdown voltage (B).

FIG. 9 is a cross-sectional view illustrating a conventional high breakdown voltage thin film transistor.

[Explanation of symbols]

Reference Signs List 1, 21, 31, 41, 51, 61 High breakdown voltage thin film transistor 2 substrate 4 semiconductor thin film 5 source region 6 active layer 7 second offset region 8 first offset region 9 drain region 11 main gate electrode 13 first sub gate electrode 15 second Sub-gate electrode

Claims (22)

(57) [Claims] 1. A main gate electrode having a source region, an active layer, a first offset region, and a drain region arranged and formed in a semiconductor thin film, and a main gate electrode formed on the active layer with an insulating film interposed therebetween. A first sub-gate electrode formed on the first offset region via an insulating film;
A high-breakdown-voltage thin-film transistor in which the first sub-gate electrode is disposed higher than the main gate electrode with respect to the semiconductor thin film, and further includes the active layer and the first offset region in the semiconductor thin film. A second offset region formed between the second offset region and a second sub-gate electrode formed on the second offset region via an insulating film, wherein the first sub-gate electrode and the second sub-gate electrode are respectively connected to the main sub-gate electrode; The gate electrode, the source region, and the drain region are connected to a different voltage supply source, and the second sub-gate electrode is located higher than the first sub-gate electrode with respect to the semiconductor thin film. High-breakdown voltage thin film transistor. 2. The high-breakdown-voltage thin film transistor according to claim 1, wherein the second sub-gate electrode is arranged more distant from the main gate electrode than the first sub-gate electrode. 3. The width of the second offset area is 1 to 5
The high breakdown voltage thin film transistor according to claim 1, wherein the thickness is set to μm. 4. A wiring for electrically connecting the first sub-gate electrode and the second sub-gate electrode is formed in an insulating film between the first sub-gate electrode and the second sub-gate electrode. 4. The method according to claim 1, wherein
The high breakdown voltage thin film transistor according to any one of the above. 5. The high withstand voltage according to claim 1, wherein the second sub-gate electrode has portions extending above the main gate electrode and above the first sub-gate electrode, respectively. Thin film transistor. 6. The high breakdown voltage thin film transistor according to claim 1, wherein the first sub-gate electrode has a portion extending above the drain region. 7. A semiconductor device further comprising: a third offset region formed between the first offset region and the drain region; and a third sub-gate electrode formed on the third offset region via an insulating film. The third sub-gate electrode is connected to a voltage supply different from the main gate electrode, the source region and the drain region, and the third sub-gate electrode is connected to the first sub-gate electrode with respect to the semiconductor thin film. 7. The high breakdown voltage thin film transistor according to claim 1, wherein the high breakdown voltage thin film transistor is arranged at a position higher than the sub-gate electrode. 8. The high-breakdown-voltage thin film transistor according to claim 7, wherein the third sub-gate electrode is arranged farther from the drain region than the first sub-gate electrode. 9. The width of the third offset area is 1 to 5
The high breakdown voltage thin film transistor according to claim 7, wherein the thickness is set to μm. 10. A wiring for electrically connecting the first sub-gate electrode and the third sub-gate electrode is formed in an insulating film between the first sub-gate electrode and the third sub-gate electrode. The high breakdown voltage thin film transistor according to claim 7, wherein: 11. The high breakdown voltage thin film transistor according to claim 7, wherein said third sub-gate electrode has portions extending above said drain region and above said first sub-gate electrode, respectively. . 12. A fourth offset region and a fifth offset region sequentially formed from the side closer to the source region between the source region and the active layer, and an insulating film on the fourth offset region. And a fifth sub-gate electrode formed on the fifth offset region with an insulating film interposed therebetween, wherein the fourth sub-gate electrode and the fifth sub-gate electrode are respectively formed by the The fifth sub-gate electrode is connected to a voltage supply source different from the main gate electrode, the source region and the drain region, and the fourth sub-gate electrode is positioned higher than the main gate electrode with respect to the semiconductor thin film. 12. The high-breakdown-voltage thin film transistor according to claim 1, wherein the high-voltage thin film transistor is disposed at a position higher than the fourth sub-gate electrode. Lanista. 13. The high-breakdown-voltage thin film transistor according to claim 12, wherein the fifth sub-gate electrode is arranged farther from the main gate electrode than the fourth sub-gate electrode. 14. The fifth offset region has a width of 1 to 5 μm.
3. The high breakdown voltage thin film transistor according to claim 1. 15. A wiring for electrically connecting the fourth sub-gate electrode and the fifth sub-gate electrode is formed in an insulating film between the fourth sub-gate electrode and the fifth sub-gate electrode. The high breakdown voltage thin film transistor according to claim 12, wherein 16. The semiconductor device according to claim 1, wherein the fifth sub-gate electrode has portions extending above the main gate electrode and above the fourth sub-gate electrode, respectively.
16. The high breakdown voltage thin film transistor according to any one of 2 to 15. 17. The high breakdown voltage thin film transistor according to claim 12, wherein said fourth sub-gate electrode has a portion extending above said source region. 18. A semiconductor device comprising: a sixth offset region formed between the source region and the fourth offset region; and a sixth sub-gate electrode formed on the sixth offset region via an insulating film. The sixth sub-gate electrode is connected to a voltage supply different from the main gate electrode, the source region, and the drain region, and the sixth sub-gate electrode is connected to the fourth sub-gate electrode with respect to the semiconductor thin film. 17. The high breakdown voltage thin film transistor according to claim 1, wherein the thin film transistor is arranged at a position higher than the sub-gate electrode. 19. The high breakdown voltage thin film transistor according to claim 18, wherein said sixth sub-gate electrode is arranged at a distance from said source region than said fourth sub-gate electrode. 20. The width of the sixth offset region is set to 1 to 5 μm.
3. The high breakdown voltage thin film transistor according to claim 1. 21. A wiring for electrically connecting the fourth sub-gate electrode and the sixth sub-gate electrode is formed in an insulating film between the fourth sub-gate electrode and the sixth sub-gate electrode. 21. The high breakdown voltage thin film transistor according to claim 18, wherein 22. The semiconductor device according to claim 18, wherein said sixth sub-gate electrode has lower portions extending above said source region and above said fourth sub-gate electrode, respectively.
2. The high-breakdown-voltage thin film transistor according to claim 1.