JP3197526B2 - Decryption device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device for decoding channel-coded information, and is particularly suitable for use in a multimedia digital information communication system.

[0002]

2. Description of the Related Art In multimedia digital information communication, a transmitting side converts a plurality of pieces of multimedia information, for example, voice, video, text document, and computer data into bit data by an information source coder and then multiplexes the information. Synthesizes it into one bit string and transmits it. On the receiving side,
After the received bit string is divided into each piece of media information by the separator, the data is reproduced by information source decoding. In the case of wireless transmission such as mobile communication, a bit error occurs due to the transmission. Therefore, error correction by channel coding / decoding is introduced. At this time, in the multimedia communication, an allowable bit error rate and an allowable processing delay time for error correction differ depending on each medium. For example, audio and video can tolerate some bit errors, but in particular, in the case of two-way communication, the demand for delay time is strict. On the other hand, in the case of computer data, the requirement for bit errors is extremely severe, but the delay time is acceptable.

[0003] Therefore, in multimedia communication,
In channel coding on the transmission side, first, channel coding is performed for each medium before multiplexing, and channel coding is further performed on the multiplexed bit sequence. In the channel decoding on the receiving side, first, channel decoding is performed on the bit string before separation, and further, channel decoding is performed on each of the separated media. That is, the minimum necessary error correction is performed on the signal before separation, and the required error correction is performed on each of the separated media signals.

FIG. 7 is a diagram showing an example of the configuration of such a multimedia digital communication system, in which (a) shows the configuration on the transmitting side and (b) shows the configuration on the receiving side. In this example, the first information and the second information having different required communication qualities are multiplexed and transmitted. The first information is encoded by a first information source encoder S-Enc1 and converted into a corresponding bit sequence, and subjected to a first channel encoding in a first channel encoder C-Enc1. Is done. On the other hand, after the second information is source-coded by the second source encoder S-Enc2, the first information is sent by the second channel encoder C-Enc2.
A second channel coding is performed. Here, the channel coding by the first channel coder C-Enc1 and the channel coding by the second channel coder C-Enc2 correspond to requests for the corresponding first and second information, respectively. Selected so as to absorb the difference in communication quality. Encoded first information output from the first channel encoder C-Enc1, and encoded second information output from the second channel encoder C-Enc2 Are multiplexed in the multiplexer Mux, and
In the channel encoder C-Enc3, the second channel encoding is performed. The output of the third channel encoder C-Enc3 is modulated by a modulator (not shown) and transmitted to a transmission channel.

In FIG. 7 (b), a received signal demodulated by a demodulator (not shown) is input to a third channel decoder C-Dec3, where decoding corresponding to the second channel coding is performed. Is made. This decoded output is input to the separator DMux, and the channel decoded data string corresponding to the first information and the second
And a channel decoded data string corresponding to the information of
A decoded output corresponding to the first information is input to a first channel decoder C-Dec1 corresponding to channel coding by the first channel encoder C-Enc1 and decoded, and the first channel is decoded. The information source is decoded by the information source decoder S-Dec1, and the first information is reproduced. Also, the second output from the separator DMux
Is output from the second channel decoder C-De.
The information is decoded in c2 and the information is decoded in the second information source decoder S-Dec2 to reproduce the second information.

As described above, in the multimedia digital information communication, in order to cope with the fact that the communication quality required by the transmission information of each medium is different, communication channel coding on the media side before multiplexing and multiplexing are performed. The channel coding is performed twice, which is divided into the channel coding on the transmission side after the transmission. As an example of the former, H.223 Annex C of the International Standards Organization ITU-T is known. Regarding the latter, there have been many studies using wideband CDMA, and in recent years, there has been a study to introduce turbo coding / decoding as channel coding / decoding on the transmission path side (for example, Fujiwara, Suda, Adachi, "Turbo" Transmission characteristic of W-CDMA using code ", IEICE General Conference 1998, B-5-123).

[0007] Turbo encoding / decoding will be described with reference to FIG. FIG. 8A is a diagram showing the configuration on the transmission side. As shown in FIG. 8, on the transmission side, a first parity block is applied to an information block by a first channel encoder C-Enc1. Generate Further, a second parity block is generated by a second channel encoder C-Enc2 for the information block obtained by interleaving the information block with an interleaver Ilv1, and the information block is generated by the first block.
And the second parity block. Here, the first and second channel encoders
C-Enc1 and C-Enc2 use a cyclic systematic convolutional coding method.

On the receiving side shown in FIG. 8 (b), the received information block and the first parity block are decoded by a first channel decoder C-Dec1, and are interleaved by an interleaver Ilv2. The block and the second parity block are decoded by the second channel decoder C-Dec2. Here, as the first and second channel decoders C-Dec1 and C-Dec2, a soft-decision input and a soft-decision output for generating a real-valued decoded output signal with respect to a real-valued received input signal are provided. A decoder of the maximum likelihood decoding method is used. Furthermore, this decoder employs a method that can add an input likelihood that gives the reliability of the signal before decoding and can generate an output likelihood that gives the reliability of the signal after decoding. Then, at the time of decoding, the output likelihood generated by decoding by the first channel decoder C-Dec1 is output via the interleaver Ilv3 to the second channel decoder C-Deci.
In addition to the input likelihood of c2, the output likelihood generated by the decoding of the second channel decoder C-Dec2 is used as the deinterleaver DIlv1
, And as input likelihood in the decoding of the first channel decoder C-Dec1, these decoders C-Dec1 and C-Dec1
The decoding process in c2 is repeated. The decryption information is the first
Channel decoder C-Dec1 or deinterleaver DIlv
2 via the output of the second channel decoder C-Dec2.

This turbo encoding / decoding system is said to obtain characteristics close to the theoretical limit.
For example, it is described in detail in the following literature. (1) J. Hagenauer, E. Offer, and L. Papke, "Iterativ
e decoding of binaryblock and convolutional code
s ", IEEE Trans. Information Theory, vol.42, no.2, p
p.429-445, March 1996. (2) Nikkei Electronics, No.721 (1998.7.13), p.
p.163-177

[0010]

Generally, in channel coding / decoding, as the number of parity bits is increased, the error correction capability is improved, but there is a problem that the transmission efficiency is deteriorated. In the prior art shown in FIG. 7, the transmission-side channel decoding before the separation (third channel decoder C-Dec3) and the media-side channel decoding after the separation (first and second channels) are performed. , The channel decoders C-Dec1 and C-Dec2) are independently performed, and there is a problem that efficient error correction is not performed. In the above-described conventional multimedia multiplex communication system for multiplexing and transmitting a plurality of media, error correction on the receiving side includes channel decoding on the transmission line performed before separating the multiplexed received signal, and voice decoding. It consists of media channel decoding that is performed after separation into media information such as video, text documents, computer data, etc.Before and after separation, channel decoding is performed independently. There is a problem of bad.

Accordingly, an object of the present invention is to provide a decoding device capable of performing efficient error correction. It is another object of the present invention to provide a decoding device that can realize efficient error correction according to the error correction capability and the allowable delay amount required by each medium.

[0012]

In order to achieve the above object, a decoding device according to the present invention is a decoding device for decoding channel-coded information, in which a received signal is input and an input signal block is converted. A first communication path decoding unit having a function of inputting an input likelihood of a constituent signal and executing a decoding process; and a control unit included in an output signal block output from the first communication path decoding unit. Extracting means for extracting a signal arranged at a predetermined position to generate a separated signal block, and inputting the separated signal block and outputting the output likelihood of the signal constituting the output signal block to execute decoding processing And a second channel decoding unit having a function of performing the above operation. The output likelihood output from the second channel decoding unit is input as the input likelihood of the first channel decoding unit. What is being done . Further, the decoding process of the first channel decoding unit and the decoding process of the second channel decoding unit are repeatedly executed.

Further, the control signal includes a synchronization flag indicating a head position of the separation signal block.
Furthermore, the control signal includes a header indicating an arrangement position of a signal constituting the separation signal block in an output signal block of the first communication path decoding unit. Still further, the control signal is input as an input likelihood of the first channel decoding means. Furthermore, the separation means is adapted to generate the separation signal block from one or more continuous output signal blocks of the first communication path decoding means in which at least two synchronization flags are detected. Things.

According to such a decoding apparatus of the present invention, it is possible to associate the transmission path decoding on the transmission side before separation with the communication path decoding on the media side after separation, thereby performing efficient decoding. Becomes possible. Further, by performing iterative decoding, more efficient error correction can be performed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment of the Present Invention) FIGS. 1A and 1B are diagrams for explaining a first embodiment of the present invention. FIG. 2 shows the configuration of the receiving side. For ease of explanation, it is assumed that the information to be transmitted on the transmitting side includes first and second information signal sequences. Here, the information signal sequence is obtained by assigning a code word composed of a bit pattern combining "0" and "1" to information such as audio, video, characters, and computer programs by information source coding. This is the generated bit string.

On the transmitting side, first, the first information signal sequence is divided into an appropriate length (N1) by the first blocker Blk1, and a first information signal block is generated.
Is input to the channel coder C-Enc1 and subjected to a channel coding process to generate a first channel coded signal block.
Similarly, the second information signal sequence is input to the second blocker Blk2, divided into blocks of an appropriate length (N2), and a second information signal block is generated. The channel encoder C-Enc2 performs a channel encoding process to generate a second channel encoded signal block. Through these channel coding processes, error correction coding for improving transmission reception quality is performed. Here, a cyclic systematic convolutional encoder is used as the first and second channel encoders C-Enc1 and C-Enc2. The channel coded signal block generated by the coder has a configuration in which a parity signal block generated according to a coding rule determined by the coder is added after the input signal block. That is, when the coding rate of the first channel encoder C-Enc1 is 1 / R1,
The length of the first parity signal block is N1 (R1-1),
The length of the first channel coded output signal block is N1R1. Similarly, when the coding rate of the second channel encoder C-Enc2 is 1 / R2, the length of the second parity signal block is N2 (R2-1), and the second channel code is The length of the structured output signal block is N2R2. However, it is assumed that the information blocks each include a termination signal for convenience of decoding.

The first channel encoded output signal block and the second channel encoded output signal block are input to a multiplexer Mux. In the multiplexer Mux, the first information signal block, the first parity signal block, the second information signal block, and the second parity signal block are combined into one signal sequence according to a predetermined rule. To generate a multiplexed block.
FIG. 2 shows the data structure of the multiplex block. As shown in this figure, the multiplexed block is a payload (length Np) in which the multiplexed coded signal sequence is accommodated, and a header (length) indicating a rule of how the signal block is accommodated in the payload. Nh) and a synchronization flag (length Ns) indicating the start position of the multiplex block, and the length of the multiplex block is Nm = Ns + Nh + Np. The number of payload signals is Np = N1 + (R1-1) N1 + N2 + (R2-1) N2, but the first information signal block, the first parity signal block, the second information signal block, and the second parity The header indicates which signal of the signal block corresponds to which signal of the payload.

The multiplex block sequence composed of a plurality of multiplex blocks output from the multiplexer Mux is divided into an appropriate length (N3) by the third blocker Blk0.
The third channel encoder C-Enc0 performs a channel encoding process to generate a third channel encoded signal block. Here, when a cyclic organization convolutional encoder is selected as the third channel encoder, when the coding rate is 1 / R3, the length of the parity signal block is N3 (R3-1), The length of the third channel-coded output signal block is N3R3. However, the output block of the third channel encoder C-Enc0 includes a termination signal for convenience of decoding. Further, the input signal block of the third channel encoder C-Enc0 is obtained by cutting the output signal block sequence of the multiplexer Mux into an appropriate length N3. Even when N3 is larger than Nm, N3 May be smaller than Nm.

Hereinafter, in the third channel-coded block sequence, the length N3 of all the third channel-coded blocks is fixed, and the length Nm of the multiplex block is variable. The case where the maximum value is smaller than N3 will be described as an example. The third channel coded block sequence output from the third channel coder C-Enc0 is transmitted to a transmission path via a transmitter (not shown) including a modulator, an amplifier, an antenna, and the like. You.

The signal received through the transmission path is input to a third communication path decoder C-Dec0 via a receiver (not shown) including an antenna, an amplifier, a demodulator and the like.
Here, as the third channel decoder C-Dec0 and the first and second channel decoders C-Dec1 and C-Dec2 to be described later, a soft decision input and a soft decision output maximum likelihood decoder are used. Is used. This decoder inputs an input likelihood representing the reliability of each signal constituting the received input signal block together with a real-valued received input signal block, and outputs an output likelihood representing the reliability of each signal after decoding. Calculated and output, there is a relationship of decoded output = received input signal + input likelihood + output likelihood. This maximum likelihood decoding method, such as a likelihood calculation method, is described in detail in, for example, the aforementioned reference (1).

After transmission in the additive noise environment, the received signal has the following relationship: received signal = transmitted signal + noise. It is assumed that each signal constituting the transmission signal block is a signal in which data of "1" is assigned a signal value of "+1.0" and data of "0" is assigned a signal value of "-1.0". For example,
This is a case where a two-phase PSK method is adopted as a modulation method on the transmitting side. When the received signal value input to the soft-decision input, soft-decision output maximum likelihood decoder is “+0.4”,
When the noise value "-0.6" is added to the transmission signal value "+1.0",
A noise value “+1.4” may be added to the transmission signal value “−1.0.” The input likelihood input to the decoder C-Dec is a positive value,
For example, if "+0.6" is set, the channel is decoded with a bias that the transmission signal value is likely to be "+1". Conversely, if the input likelihood is a negative value, for example, "-0.4",
Communication channel decoding is performed with a bias that the transmission signal value is likely to be "-1". When the output likelihood output from the maximum likelihood decoder is a positive value, for example, “+0.
7 means that the decoded value may be "+1", and the larger the value is, the higher the reliability is. On the other hand, when the output likelihood is a negative value, for example, "-0.3" This means that the transmission signal value may be "-1", and the larger the absolute value, the higher the reliability.

When the value of the received signal is "+0.4" and the input likelihood is "+0.
When the output likelihood is “+0.7”, the decoded value output from the maximum likelihood decoder is “+1.7”, and the value of the received signal is “+1.7”.
0.4 ", the input likelihood is" -0.1 "and the output likelihood is" -0.2 ",
The decrypted value is "+0.1". When the decoded value is positive, a hard decision is made that the decoded data is "1", and when the decoded value is negative, the decoded data is "0". In both the former case and the latter case, the decoded data is "1". The former has a higher reliability of the decoded data, while the latter has a lower reliability of the decoded data, and the correct data is "0". It means that there is a possibility. In this embodiment, a channel decoding method based on the input likelihood and the output likelihood of the above document is introduced, and the likelihood calculation is based on the above document.

Now, the third channel decoder C-Dec0 is:
The received third channel coding block is subjected to a corresponding third channel decoding to perform error correction. That is, the output likelihood of each signal of each channel coding block is calculated, and its decoded value is obtained. Note that, as an initial condition, the input likelihood of each received signal forming the block is "
0 ". Next, the third channel decoded signal block output from the third channel decoder C-Dec0 is separated into each multiplex block in the third deblocking unit DBlk0, and each multiplex block is separated. The blocks are input to the separator DMux.

FIG. 3 shows the configuration of the third channel decoding block sequence output from the third channel decoder C-Dec0 and the multiplex blocks included therein. As shown in the figure, the third channel decoder C-Dec0 outputs the i-th and i-th channels.
The channel decoding blocks are sequentially output in the order of +1, i + 2, and so on. The third deblocker DBlk0
Represents two consecutive channel decoding blocks (i-th and i + 1
, Etc.), the synchronization flag is detected. The length N3 of all the third channel coding blocks is a fixed length, and
The length Nm of the multiplex block is variable and its maximum value is N3
As shown in the figure, from the i-th and (i + 1) -th third channel decoded signal blocks,
Two or more synchronization flags are detected. The third deblocker DBlk0 detects the synchronization flag to detect the start position of the multiplex block, and separates one or more multiplex blocks between the detected first and last synchronization flags into a demultiplexer DMlk0.
Output to ux.

The demultiplexer DMux detects the contents of the header of each multiplexed block, and detects at what position in the payload what kind of signal is accommodated. In the present embodiment, where the signals of the first and second channel-encoded signal blocks are accommodated is detected, and each signal block is separated. Then, it outputs the separated first channel coded signal block to a first channel decoder C-Dec1, and outputs the second channel coded signal block to a second channel decoder C-Dec2. Output to

Each of the first channel decoder C-Dec1 and the second channel decoder C-Dec2 performs a corresponding channel decoding process on a corresponding channel coded signal block. And a second channel-decoded signal block. At this time, for each information signal of the block, each received signal from the demultiplexer DMux is input, and as the input likelihood of each signal, a third signal in the third channel decoder C-Dec0 is input. The output likelihood of each information signal obtained by the channel decoding is input via the selector Sel.
On the other hand, the decoded output of the third channel decoding is input to each parity signal of the channel decoded signal block. Error correction is performed by this channel decoding process. That is, the output likelihood of each signal of the block is calculated to obtain a decoded value. At this stage, the first and second channel decoders C-De
c1, a first deblocker DB from the first and second channel decoded signal blocks output from C-Dec2, respectively.
The first and second information can be reproduced via lk1 and the second deblocker DBlk2.

In order to further improve the decoding performance, the following processing is performed. The output likelihood obtained by the first and second channel decoding in the first channel decoder C-Dec1 and the second channel decoder C-Dec2 is calculated by the third channel decoder C-Dec1.
As the input likelihood of the third channel decoding in Dec0, the third
Re-execute the communication path decoding. Then, based on the result of the third channel decoding, the first and second channel decoding are further executed. That is, the output likelihood obtained by the third channel decoding is used as the input likelihood of the first and second channel decoding, and the output likelihood obtained by the first and second channel decoding is The channel decoding process is repeated as the input likelihood of the third channel decoding, and the decoding performance is gradually improved. The same process is performed on the received (i + 1) th and (i + 2) th channel coding blocks.
Continues to the (i + 3) th.

As described above, in the present invention, since the iterative decoding is performed between the channel decoding on the transmission side before separation and the channel decoding on the media side after separation, efficient error correction is performed. Corrections can be made. Note that the number of repetitions for the first information block and the number of repetitions for the second information block may be the same or different. The number of iterations is
It can be set freely according to the decoding quality required for each information and the allowable processing delay time. Further, in the above, both the first and second information blocks are provided with channel coding / coding.
Although decryption is introduced, only one of them may be used if unnecessary.
Furthermore, the number of information blocks to be multiplexed is not limited to two,
It can be applied to any number of one or more information blocks.

(Second Embodiment of the Present Invention) Next, unlike the first embodiment, one of the two types of information blocks has stronger error protection than the other. Is required, and only one channel is subjected to two-time channel coding. Further, in an embodiment in which the length of a multiplex block may be longer or shorter than the length of a block divided after multiplexing, This will be described with reference to FIG.
4A shows the configuration on the transmitting side, and FIG. 4B shows the configuration on the receiving side.

First, on the transmitting side shown in FIG. 4 (a), as in the first embodiment shown in FIG. 1, two sources are used as information sources for generating information such as images, sounds, and computer data.
The information sources are assumed to be "0" and "1" by the corresponding source encoders S-Enc1 and S-Enc2.
Has been converted to a bit stream consisting of
The two types of information bit streams are divided into K1 bit and K2 bit blocks, respectively, by the corresponding blockers Blk1 and Blk2, and each of the information bitstreams is divided into information block 1 (In).
f1: K1 bit) and information block 2 (Inf2: K2 bit). Here, it is assumed that the information block 1 requires stronger error protection than the information block 2. Therefore, a communication path encoder 1 (C-Enc1) for error correction coding is installed for the information block 1, but unlike the first embodiment, the information block 2 is different from the first embodiment. On the other hand, the channel encoder 2 (C-Enc
2) Not installed. Here, the channel encoder 1 (CE
nc1) is defined as a systematic cyclic convolutional encoder with a coding rate of 1 / R1. At this time, the encoded output (C-Inf1) is composed of information block 1 (Inf1) and parity check block 1 (Chk1).
Are described separately.

Next, Inf1, Chk1 and Inf2 are arranged in one bit string, the order of bits is changed by an interleaver (Ilv1), and a synchronizing word (Sync) and a header (Head) are multiplexed by a multiplexer (Mux). To add multiple packets (M-Pac: M
Bit). FIG. 5A shows the relationship between the information blocks 1 and 2 and the multiplex packet M-Pac. As shown in this figure, the multiplex packet M-Pac is composed of information block 1 (I
nf1), a payload (Pyld: M3 bits) containing the parity check block Chk1 and the information block 2 (Inf2), and a header (Head) containing control information such as the type, length, and arrangement rules of the multiplexed information. : M2 bit) and a synchronization word (Sync: M1 bit) indicating the head of the packet. Here, the header itself is error-correction coded by a header channel coder (C-Enc-h) for error protection. That is, as shown in the lower part of FIG. 4A, the channel coding of the header is performed by adding a parity check block of the header to the header information block (Inf-h) and by the channel coding (C-Enc-h). Generates a header (Head) that has been subjected to error correction coding. The above-mentioned interleaver (Ilv1) has a role of increasing the tolerance against burst errors by spreading Inf1, Chk1 and Inf2 into Pyld.

Next, as can be seen from the frame structure shown in FIG. 5B, the multiplexed packet (M-pac) sequence generated by the multiplexer (Mux) is divided, and the bit order is changed by the interleaver (Ilv0). Sorting, information block 0 (Inf0:
K0 bit). Note that M-Pac may be shorter or longer than Inf0. As shown in FIG. 4A, the information block Inf0 is error-corrected coded Inf0 (C-Inf0) by a channel encoder 0 (C-Enc0) having a coding rate of 1 / R0. Is generated, and the information block C-Inf0 is input to a modulator (not shown) or the like. Channel encoder 0
By defining (C-Enc0) also as a systematic cyclic convolutional encoder, the coded output C-Inf0 is described separately for information block 0 (Inf0) and parity check block 0 (Chk0). I have.

On the other hand, on the receiving side in FIG. 4B, the received signal block C-Inf0 from the demodulator (not shown) is decoded by the channel decoder 0 (C-Dec0), and the decoded information block 0 is decoded.
Generate Then, after passing through a deinterleaver (DIlv0), this block sequence is input to a separator (DMux) to detect a synchronization word (Sync) and to detect a head of a block (M-Pac). Next, the header (Head) is error-corrected and decoded by the header channel decoder (C-Dec-h), and the header information (Inf-h) is extracted. The deinterleaver (DIlv1) performs a reverse operation of the operation in which the bit order is changed by the interleaver (Ilv1) on the transmission side, and plays a role of returning to the order before the change. DIlv1), after the payload (Pyld) to Inf according to the header information (Inf-h)
1. Separate Chk1 and Inf2. Then, Inf1 and Chk1 are input to the error correction decoder 1 (C-Dec1), and execute the error correction of Inf1. Finally, Inf1 and Inf2 are connected to source decoders 1 and 2 (S-Dec1, SD-Dec1) via deblockers DBlk1 and DBlk2.
ec2) is input and the information is reproduced.

As described above, in this embodiment, the second information Inf2 is subjected to one-time error correction by the error correction encoder C-Dec0, but the first information Inf2 is assumed to require strong error correction. The information Inf1 is subjected to two error corrections by the error correction encoders C-Dec0 and C-Dec1. Here, as described in the turbo decoding, two soft decision inputs / soft decision outputs (So
The likelihood (Likelihood) representing the reliability of information is supplied between decoders having the configuration of ft-in / Soft-out to improve the decoding quality. That is, the error correction encoder C-Dec1
Is fed back to the error correction encoder C-Dec0 as the input likelihood (L-in).

This will be described more specifically with reference to FIG. The first input block (1st input, (a) in the figure) of the received signal is composed of an information block (Inf0) and a parity check block (Chk0), which is used as a channel decoder (C-Dec0).
And the error-corrected decoded information block Inf0
(B) is obtained. Similarly, the information block (Inf0) and the parity check block (Chk0) of the second input block (2nd input, (c)) of the received signal are converted into a channel decoder (C-Dec).
0) and the error-corrected decoded information block Inf
0 (d) is obtained. After deinterleaving (DIlv0) each of these two Inf0 blocks, a sync word (Sync, abbreviated as S in the figure) is detected. At this time, Sync is detected in a state where the two DIlv0 output blocks are combined. I do. This is because if the blocks are separated and you try to detect one of the syncs, if the sync spans both blocks,
This is because nc cannot be detected.

In the case shown in the figure, since two Syncs are detected from Inf0 (b) generated from the first input block (a), the first M is interposed between the first Sync and the second Sync. It can be seen that one -Pac is completely included. That is, M-Pac is shorter than Inf0. The second Sync is the next MP
Although the beginning of ac is shown, it is understood that the second M-Pac is included only halfway since the third Sync is not detected. On the other hand, Inf0 generated from the second input block
Since Sync is not detected from this, it can be seen that this Inf0 contains only a part of Pyld.

Hereinafter, the first block generated from the first block will be described.
The process is executed for M-Pac (e). This M-Pac
(E) The Pyld part is deinterleaved (DIlv1), and according to the header (abbreviated as Head, H), information block 1 (Inf1, I
1), parity check block 1 (abbreviated as Chk1, C1), and information block 2 (abbreviated as Inf2, I2) are detected (f). The information block 2 is output as it is. on the other hand,
The information block 1 obtains Inf1 error-corrected and decoded by the channel decoder 1 (C-Dec1) (g), and this is output.
At this stage, the first output of Inf1 and Inf2 is obtained. Next, iterative decoding for improving output characteristics is performed.

The output likelihood (L1) of the information block 1 is extracted and fed back to the channel decoder C-Dec0.
L1 corresponds to the portion of Inf1 in the Pyld block, and the remaining likelihood has not been obtained. Therefore, 0 is inserted into the remaining portion (h), and interleaving (Ilv2) is performed. Further, the In
In addition to the first Sync and Head and the second Sync and Head detected from f0 (b), 0 is inserted into the next Pyld section (i), and after interleaving (Ilv3), the information is obtained. The input likelihood (L0) of block 0 (Inf0, (a)) is obtained (j). Note that the real-valued Sync and Head including the received noise
On the other hand, the correctly detected and reproduced Sync and Head are bit strings of + v and -v in which noise has been suppressed, and when adding this as likelihood, the larger the value of v, the higher the reliability. Assumed Sync and Head. Using this input likelihood L0,
The communication channel decoding 0 (C-Dec0) is executed again, and thereafter, the same operation as described above is performed, and the second output generation ends. The third and subsequent iterations are performed according to the desired output characteristics.

Next, the second input block (2nd input, (c)) of the received signal will be described. For the second block (c), the information block (Inf0) and the parity check block (Ch) have already been processed in the first block.
k0) is decoded by the channel decoder (C-Dec0) to obtain an error-corrected decoded information block Inf0 (d). Similarly, the third input block (3rd input,
(K)) The information block (Inf0) and the parity check block (Chk0) are decoded by the channel decoder (C-Dec0),
An information block Inf0 (l) subjected to error correction decoding is obtained. After each of these two Inf0 blocks (k, l) is deinterleaved (DIlv0), a synchronization word (abbreviated as Sync, S) is detected. Similarly, a state in which the two DIlv0 output blocks are combined To detect Sync.

As is known from the processing of the first block, no Sync is detected from the second block.
Part of Pyld is included. On the other hand, the third Sync is detected from the third block. This Sync and the first
During the second Sync detected in the processing of the second block
It can be seen that Pac exists. This is more M-Pac than Inf0
Is long. The third Sync indicates the beginning of the next M-Pac, but since the fourth Sync is not detected, the third M-Pac is not detected.
It turns out that Pac is included only halfway. Second
From the first Sync to the third Sync to form the second M-Pac
Generate (m) and deinterleave the Pyld part (DIlv)
Information block 1 (Inf1), parity check block 1
(Chk1), the information block 2 (Inf2) is detected (n).
The information block 2 is output as it is. On the other hand, the information block 1 obtains Inf1 that has been subjected to error correction decoding by the channel decoder 1 (C-Dec1), and this is output (o). At this stage, the first output of Inf1 and Inf2 is obtained. Next, iterative decoding for improving output characteristics is performed.

As in the processing of the first block, the output likelihood (L1) of information block 1 is extracted and fed back to C-Dec0, where L1 corresponds to the Inf1 part in the Pyld block. However, since the remaining likelihood has not been obtained, 0 is inserted into the remaining portion to perform (p) interleaving (Ilv2), and further, the detected first Sync and Head, and the second Sync and Head are detected. In addition, 0 is inserted into the next Pyld section (q), and after interleaving (Ilv3), the input likelihood (L0) of information block 0 (Inf0) is obtained (r). By using this, channel decoding 0 (C-Dec0) is executed, and thereafter, the same operation as described above is performed, and the second output generation ends. The third and subsequent iterations are performed according to the desired output characteristics. The same process is performed for the fourth and subsequent blocks.

As can be seen from the above, this embodiment is
The case where M-Pac is shorter or longer than Inf0 is also applied, and as shown in FIG. 6, when M-Pac is longer than Inf0, according to C-Dec1 after correction by C-Dec0 for continuous Inf0. Through processing, the output likelihood is obtained, the signal is fed back to the position of Inf1 in Inf0 as the input likelihood in consideration of the signal arrangement in Mux, and decoding / separation is repeated. As a result, Inf1 is selectively subjected to iterative decoding.

[0043]

As described above, according to the decoding apparatus of the present invention, the communication path decoding on the transmission side before separation and the communication path decoding on the media side after separation are decoded in association with each other. , Efficient decoding can be performed. Further, since iterative decoding is performed, more efficient error correction can be performed. Furthermore, efficient error correction can be realized according to the error correction capability and the allowable delay amount required for each medium.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a configuration of a multiplex block according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining a configuration of a channel decoding block according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration example of a second embodiment of the present invention.

FIG. 5 is a diagram for explaining communication channel encoding / decoding of a header and a frame configuration according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining a decoding method on the receiving side according to the second embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a conventional multimedia digital information communication system.

FIG. 8 is a diagram illustrating a turbo code.

[Explanation of symbols]

 Blk blocker C-Dec channel decoder C-Enc channel encoder DBlk deblocker DIlv deinterleaver DMux separator Ilv interleaver Mux multiplexer S-Dec information source decoder S-Enc information source code Chemist

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-336400 (JP, A) JP-A-11-191758 (JP, A) JP-A-11-330984 (JP, A) JP-A-11-191 298339 (JP, A) IEICE Technical Report Vol. 99, No. 200, C S99-71

Claims (6)

(57) [Claims] 1. A decoding device for decoding channel-coded information, having a function of receiving a received signal, inputting an input likelihood of a signal constituting an input signal block, and executing a decoding process. A first channel decoding unit, and extracting a signal arranged at a predetermined position based on a control signal included in an output signal block output from the first channel decoding unit to generate a separated signal block. A second communication path decoding unit having a function of receiving the separated signal block, outputting an output likelihood of a signal constituting the output signal block, and executing a decoding process; The output likelihood output from the channel decoding means of
A decoding device, wherein the input is input as an input likelihood of the first channel decoding means. 2. The decoding according to claim 1, wherein the decoding process of the first channel decoding unit and the decoding process of the second channel decoding unit are repeatedly executed. apparatus. 3. The decoding device according to claim 1, wherein the control signal includes a synchronization flag indicating a head position of the separated signal block. 4. The control signal according to claim 1, wherein the control signal includes a header indicating an arrangement position of a signal constituting the separation signal block in an output signal block of the first communication path decoding means. Decoding device. 5. The decoding apparatus according to claim 1, wherein said control signal is inputted as an input likelihood of said first channel decoding means. 6. The separation unit generates the separation signal block from one or more continuous output signal blocks of the first channel decoding unit in which at least two synchronization flags are detected. 4. The decoding device according to claim 3, wherein: