JP3196813B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TEG (Test Element) used for measuring various characteristics required for the development and design of a semiconductor memory or for checking a process at the time of production.
The present invention relates to a semiconductor memory having an ent group, and a method of inspecting a semiconductor memory for measuring electrical characteristics using the TEG.

[0002]

2. Description of the Related Art In many semiconductor devices such as VLSIs having a complicated circuit inside, a simple circuit for process check called a test element group (hereinafter referred to as TEG) is provided on the same wafer. Is provided.

The TEG is formed, for example, on a semiconductor chip different from a semiconductor device to be a product, and is used for a non-defective check test when separating a semiconductor chip on which a product circuit is formed from a wafer.

Further, in order to measure the influence of variations from the design dimensions of elements caused by manufacturing processes such as photolithography and etching, a TEG is formed as close as possible in the same semiconductor chip as a product, and the TEG and the product are formed. By using the same manufacturing method, it may be used to monitor the device performance of a product.

As such an example, there is a method of measuring the characteristics of a semiconductor memory in which a large number of memory cells are arranged in a lattice by using a TEG. In this case, the TEG is also a memory cell laid out in a lattice. Be composed.

When measuring using the TEG,
Aluminum terminals called pads are formed in TEG in advance,
The electrical characteristics are measured by applying a probe needle provided on the measuring device side to the pad.

Hereinafter, a conventional semiconductor memory having a TEG will be described with reference to FIGS.

FIG. 11 is a plan view showing the structure of a TEG used in a conventional semiconductor memory. FIG. 12 is a plan view showing a configuration example of a conventional semiconductor memory including a TEG.

In FIG. 11, in a TEG section 302 used for a conventional semiconductor memory, in order to accurately evaluate the characteristics of a memory cell of a product, a scale similar to that of the product (here, several K bits or more as an example) is provided. (A number of memory cells) is formed.

In the memory cell array 302, three word lines 305 and 3 for applying a voltage and measuring electric characteristics are applied to memory cells of 9 bits in the central portion 331 and the peripheral portion 332, respectively. The bit lines 304 are connected to each other, and TEG pads 307 for interfacing with a measuring device are provided at ends of the word lines 305 and the bit lines 304, respectively.

Here, three bit lines 304 (BL0 to BL0) connected to the memory cells of 9 bits in the central portion 331.
L2) are connected to the drain regions of the transistors of each memory cell, respectively, and are connected to three word lines 305 (WL
0 to WL2) are respectively connected to the gate electrodes of the transistors.

On the other hand, memory cells for 9 bits provided in the peripheral portion 332 also have three bit lines 304 (BL3-B).
L5) and three word lines 305 (WL3 to WL5)
Are connected to the transistors in the same manner as the central portion 331.

A source line 309 is connected to the source region of the transistor of each memory cell, and a terminal T
An EG pad 307 is formed.

Further, a wiring 310 for setting the substrate potential at a fixed potential is formed outside the memory cell array 302, and a substrate potential fixing pad 311 is formed at an end thereof. Here, a cell plate electrode (not shown) connected to a capacitor (not shown) connected to the source region of each transistor is connected to the wiring 310.

The TEG section 302 is arranged as close as possible to a semiconductor memory circuit 402 as a product in a semiconductor chip 401 as shown in FIG. 12, so that variations in element dimensions caused by processes such as photolithography and etching are different from those of the product. Manufactured by the same manufacturing process as the product so as to be equivalent.

By doing so, the characteristics of the memory cells formed in the TEG section 302 reflect the characteristics of the memory cells of the product, and the characteristics of the memory cell of the product are measured by measuring the characteristics of the TEG section 302. Characteristic can be obtained.

In addition, when the electrical characteristics of the memory cells of the central portion 331 and the peripheral portion 332 of the memory cell array 302 of the TEG portion 302 are measured, the manufacturing process conditions (for example, processing shape,
It is also possible to measure a difference in electrical characteristics resulting from a difference in processing dimension.

[0018]

However, in a semiconductor memory having the conventional TEG as described above,
In order to reflect the characteristics of the memory cells in the G section to the characteristics of the memory cells in the product, a memory cell of the same size as the product is formed in the TEG section and placed on the same semiconductor chip or in a position adjacent to the product on the same wafer I needed to.

In such a case, since a memory cell array of the same size as the product is formed in the TEG portion, the required chip area is almost doubled, and the number of product chips that can be taken out from one wafer is reduced when the TEG portion is not mounted. It will be about half as compared. Therefore, there is a problem that the manufacturing cost per chip is doubled.

On the other hand, as a method of suppressing an increase in chip area and not reducing the number of chips of products that can be taken out from one wafer, the size of the memory cell array in the TEG section is reduced and the chip is arranged at the end of the semiconductor chip as shown in FIG. There is a way to do that.

However, in this method, the number of memory cells in the TEG section is reduced. For example, when the product is a memory cell array of a megabit class, the processing and forming conditions for the product and the TEG section are different. The characteristics of the cells will not reflect the characteristics of the memory cells of the product.

This is because TE is mounted on the same semiconductor chip as the product.
Even when the G portion is arranged, a difference occurs in the etching rate of reactive ion etching (RIE) due to a difference in density of the element pattern (generally, this phenomenon is called a micro-loading effect), and a difference in electrical characteristics. Is caused.

FIG. 14 shows the relationship between the etching rate and the size of the memory cell array.

The graph shown in FIG. 14 shows a gate electrode composed of a composite film of tungsten silicide (WSi) and polycrystalline silicon, and shows the etching characteristics when this gate electrode is formed. Reactive ion etching (RIE) characteristics when helium (He) gas is used as carrier gas and sulfur hexafluoride (SF6) gas and hydrogen bromide (HBr) gas are used as etching gas under the condition of 250 (mTorr). Is shown.

As shown in FIG. 14, the etching rate tends to decrease as the size of the memory cell array increases. For example, when the size of a memory cell of a product is 64 Mbits, the memory cells in the TEG section are equal to or more than Megabits. Otherwise, the difference between the etching rate and the product becomes large, and the difference between the processed shape and the processed dimension cannot be ignored.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has been made in consideration of various characteristics of a memory cell of a semiconductor memory to be a product without increasing a chip area of the semiconductor memory. TE accurately reflected
It is an object to provide a semiconductor memory having G.

Further, there is provided a semiconductor memory inspection method for measuring various characteristics of a memory cell by using the semiconductor memory TEG.

[0028]

In order to achieve the above object, a semiconductor memory according to the present invention comprises a plurality of word lines and a plurality of bits.
Line is arranged vertically and horizontally, and the corresponding word line, bit line and
And multiple memory cells connected to the source wiring respectively
Semiconductor memory having a memory cell array comprising
And a product is attached to any one of the plurality of bit lines.
Predetermined electrical characteristics are measured instead of memory cells
Only the TEG section is connected. At this time,
Being arranged at a predetermined position in the memory cell array,
Simultaneous with the same manufacturing method as the transistor included in the memory cell
Memory cell for a TEG comprising a transistor formed in a semiconductor device
And the gate of the transistor of the TEG memory cell
Connected at the same time and used when evaluating the characteristics of the TEG memory cell.
And TEG word line having a pad that is, for the TEG
Only connected to the drain of the memory cell transistor,
Pad used when evaluating characteristics of the TEG memory cell
And TEG bit line having a of the TEG for memory cells
Connected only to the source of the transistor,
TEG with pad used for recell characterization
Source wiring.

Also, a plurality of word lines and a plurality of bit lines are
The word lines, bit lines, and source lines
Consists of multiple memory cells connected to
A semiconductor memory having a memory cell array, said
In the memory cell array, instead of the product memory cells
The TEG part where the predetermined electrical characteristics are measured
And the TEG portion is provided below the line running in the word line direction.
Part electrode wiring, between the source wiring and the lower electrode wiring.
Consisting of connected capacitors ,
Being arranged at a predetermined position in the memory cell array,
Same as the data retention capacitor of the memory cell
Consisting of capacitors formed simultaneously by the fabrication method
Of the capacitor evaluation cell,
Only one of the electrodes is connected,
A lower electrode wiring with a pad used at the time of the property evaluation,
Only the other electrode of the capacitor of the capacitor evaluation cell
And used when evaluating the characteristics of the capacitor evaluation cell.
TEG source wiring having a pad to be
May be. Further, the predetermined position is the memory cell.
The memory cell array.
It may be the periphery of b.

Since the semiconductor memory provided with the TEG configured as described above is formed by the same manufacturing method in the same region as the memory cell in which the TEG is a product, the TEG having the same characteristics as the product can be obtained. it can.

Therefore, since the TEG can be constituted by a small number of memory cells, the area occupied by the TEG can be reduced, and an increase in the chip area due to the provision of the TEG is prevented.

[0032]

Next, the present invention will be described with reference to the drawings.

The TEG for the semiconductor memory shown in each of the following embodiments is a 64-Mbit DRAM (Dynamic DRAM).
(Random access memory).

The TEG mounted on the DRAM needs to be able to measure the following various characteristics.

(1) Sub-threshold characteristics of a memory cell transistor (2) Drain current-drain voltage characteristics of a memory cell transistor (3) Isolation characteristics between memory cells (4) Capacitance characteristics of a data holding capacitor ( CV characteristics) and leak current characteristics of the capacitive insulating film The TEG of the present invention is configured to measure the above-mentioned characteristics (1) to (4), and further accurately measures the electrical characteristics of the memory cells of the product. It is a reflection.

First Embodiment First, as a first embodiment of a semiconductor memory having a TEG according to the present invention, a case where the transistor characteristics of a memory cell are measured by the TEG will be described.

FIG. 1 is a plan view showing the structure of a first embodiment of a semiconductor memory having a TEG according to the present invention.

In FIG. 1, a semiconductor chip 1 as a product
Above, four circuit blocks (memory cell arrays) each composed of a plurality of memory cells are formed, and a TEG unit 3 is formed in a desired region in the memory cell array 2 as needed. The TEG unit 3 is formed in at least one memory cell array 2 depending on the measurement content.

Of the four memory cell arrays 2, the memory cell array 2 shown in the lower left of FIG.
In the case where M is composed of four memory cell arrays 2, one memory cell array 2 is composed of 16 Mbit memory cells), a TEG unit 3 is formed at the center thereof, and the TEG unit 3 has one bit. Of memory cells.

One bit line 4 is connected to the drain region of the transistor of the memory cell, and T
An EG drain electrode pad 6 is formed. Also,
One word line 5 is connected to the gate electrode, and a TEG gate electrode pad 8 is formed at an end thereof.

On the other hand, the memory cell array 2 shown in the lower right of FIG. 1 has a TEG portion 3 formed in the peripheral portion thereof, and is composed of memory cells of one bit like the central portion. In addition, one bit line 4 is connected to the drain region of the transistor of the memory cell in the same manner as the TEG portion 3 formed at the center, and a TEG drain electrode pad 6 is formed at the end. One word line 5 is connected to the gate electrode, and a TEG gate electrode pad 8 is formed at an end of the word line 5.

Further, a source wiring 9 is connected to a source region of the transistor, and a TEG source electrode pad 7 is formed at an end thereof.

A wiring 10 for setting the substrate potential of the semiconductor chip 1 to a fixed potential is formed in a region outside the memory cell array 2, and a substrate potential fixing pad 11 is formed at an end thereof.

[0044] Here, TEG portion 3 described above, since being built into the region of the memory cell array 2 of a product, are produced simultaneously by the same manufacturing process as the memory cell array 2 as a product.

For this reason, for example, a difference in etching rate caused by a difference in pattern density when etching a gate electrode (a micro-electrode of reactive ion etching).
The loading effect) is eliminated, and the difference in processing dimensions of the gate electrode between the memory cell as a product and the memory cell in the TEG section 3 is eliminated.

Therefore, since the memory cells of the TEG section 3 have the same characteristics as the memory cells of the product, the transistor characteristics of the memory cells of the product can be improved even if the TEG section 3 is composed of only one bit of the memory cells. It will reflect exactly.

Therefore, the TEG unit 3 capable of measuring the transistor characteristics of the memory cell without increasing the chip area of the semiconductor memory can be provided.

Next, the configuration of the TEG unit 3 of this embodiment will be described in detail with reference to FIGS.

FIGS. 2 to 4 show the case where the TEG unit 3 is located at the center of the memory cell array 2.
The configuration is the same when the TEG unit 3 is located in the peripheral portion of the memory cell array 2, and the description thereof is omitted.

FIG. 2 is a circuit diagram showing an equivalent circuit of the TEG unit shown in FIG. FIG. 3 is an enlarged plan view showing the structure of the TEG portion shown in FIG. 1, and FIG.
It is sectional drawing which shows the structure seen from the side surface of the EG part.

In FIG. 2, the TEG unit 3 includes a transistor characteristic evaluation cell 12 for measuring transistor characteristics of a memory cell, and a non-operating cell 13 formed in the same column.

The word line 5 is connected to the gate G of the transistor of the transistor characteristic evaluation cell 12, and a TEG gate electrode pad 8 is formed at an end thereof. A bit line 4 is connected to the drain D of the transistor, and a TEG drain electrode pad 6 is formed at an end thereof. The source S of the transistor has a T at its end.
Source wiring 9 on which source electrode pad 7 for EG is formed,
One end of a capacitor 14 for holding data (holding voltage) is connected. The other end of the capacitor 14 is commonly connected to each transistor in the memory cell array 2 by a cell plate electrode (not shown), and the cell plate electrode is connected to the TEG upper electrode pad 29 to be connected to the TEG.
The same voltage as that of the G source electrode 7 is applied.

In FIG. 3, a transistor characteristic evaluation cell 12 is composed of a source region 15 made of an N-type semiconductor and serving as a source S of the transistor, a drain region 16 made of an N-type semiconductor and serving as a drain D of the transistor, A gate electrode 17 serving as a gate G; a bit line contact 18 connecting the bit line 4 to the drain region 16;
And a node contact 19 connecting the source line 9 and the source region 15.

The bit line 4 is connected to the TEG drain electrode pad 6, and the same word line 5 as the product memory cell is connected to the TEG gate electrode pad 8.

The source line 9 is connected to the source region 15 via a node contact 19.
Is formed with a TEG source electrode pad 7.

Note that this transistor characteristic evaluation cell 1
The memory cell (non-operating cell 13) on the same column as 2 is not used as a memory cell because the drain and source of the transistor are not connected to the bit line 4 and the source line 9, respectively.

In FIG. 4, a gate electrode 17 and a word line 5 (not shown) connected thereto are formed on a silicon substrate 20 made of a P-type semiconductor via a field oxide film 21 or a gate oxide film 22. A source region 15 and a drain region 16 are formed near the upper surface of the silicon substrate 20 with the gate electrode 17 interposed therebetween.

The first interlayer insulating film 23 is formed on the silicon substrate 20, and the bit lines 4 are formed on the first interlayer insulating film 23. This first interlayer insulating film 23
An opening reaching the drain region 16 is formed, and the drain region 16 formed near the upper surface of the silicon substrate 20 is connected to the bit line 4 by the bit line contact 18 through the opening.

A second interlayer insulating film 24 is formed on bit line 4, and source wiring 9 is formed on second interlayer insulating film 24. An opening reaching the source region 15 is formed in the second interlayer insulating film 24, and the source wiring 9 formed on the second interlayer insulating film 24 and the vicinity of the upper surface of the silicon substrate 20 are formed by the opening. Source region 15 is connected with node contact 19.

Further, the capacitor insulating film 25 is formed on the source line 9.
A cell plate electrode 26 is formed through the source line 9, the capacitor insulating film 25, and the cell plate electrode 2.
6 constitutes a capacitor 14.

Next, a procedure for measuring the transistor characteristics of a memory cell using the TEG unit 3 as described above will be described by taking as an example the case of measuring the sub-threshold characteristics of a transistor.

First, 0 V is applied to the TEG source electrode pad 7 shown in FIG.
, A positive voltage in the range of 0.1 to 5 V, for example, a voltage of about 3 V is applied.

In this state, the TEG gate electrode pad 8
Then, for example, a voltage from -1 V to +3 V is applied in 0.01 V steps, and a current flowing from the TEG drain electrode pad 6 at this time is measured by an ammeter.

Thus, the sub-threshold characteristic of the transistor can be measured.

(Second Embodiment) Next, as a second embodiment of a semiconductor memory having a TEG according to the present invention, a case where the TEG is used to evaluate the capacitor characteristics of a memory cell will be described.

FIG. 5 is a plan view showing the structure of a second embodiment of the semiconductor memory having the TEG of the present invention.

In FIG. 5, a semiconductor chip 1 as a product
01, four circuit blocks (memory cell arrays) each composed of a plurality of memory cells are formed.
A TEG section 103 is formed in a desired region in the memory cell array 102 as needed. This TE
The G section 103 is formed in at least one memory cell array 102 according to the measurement content.

Of the four memory cell arrays 102, a TEG section 103 is formed at the center in the memory cell array 102 shown at the lower left of FIG. 5, and one column (number of rows) shown in FIG. Capacitors 114 (not shown) are respectively formed in memory cell regions of (10 K bits).

One end of the capacitor 114 is connected to the lower electrode wiring 127, and a TEG lower electrode pad 128 is formed at the end.

The other ends of the capacitors 114 are commonly connected by a cell plate electrode described later, and the cell plate electrode is connected to the TEG upper electrode pad 129.

On the other hand, the memory cell array 102 shown at the lower right of FIG.
Capacitors 114 are formed in the TEG unit 103 in the region of one column of memory cells shown in FIG.
These capacitors 114 are formed by TE
As in the case of the G portion 103, one end thereof is connected to the lower electrode wiring 127, and the other end is commonly connected to a cell plate electrode described later.

Here, in order to accurately measure the capacitor characteristic (CV characteristic), the total capacitance of the capacitor 114 needs to be about several tens pF. Since the capacitance value of the capacitor 114 per memory cell is 20 fF to 30 fF, in the present embodiment, in order to obtain the capacitance value required for the above measurement, a capacitor of several K bits (one vertical column shown in FIG. 5) is used. 114 is formed in the TEG portion 103.

Since the above-described TEG section 103 is incorporated in the area of the memory cell array 102 of the product, it is manufactured at the same time by the same manufacturing process as the memory cell array 102 of the product.

Therefore, similarly to the first embodiment, TEG
Since the capacitor 114 of the portion 103 is formed with the same characteristics as the capacitor of the memory cell as a product, the capacitor 114 accurately reflects the capacitor characteristics of the memory cell of the product.

Therefore, it is possible to provide the TEG unit 103 capable of measuring the capacitor characteristics of the memory cell without increasing the chip area of the semiconductor memory.

Next, the configuration of the TEG unit 103 of this embodiment will be described in detail with reference to FIGS.

Although FIGS. 6 to 8 illustrate the case where the TEG unit 103 is located at the center of the memory cell array 102, the TEG unit 1 is located at the periphery of the memory cell array 102.
Since the configuration is the same when forming No. 03, the description thereof is omitted.

FIG. 6 is a circuit diagram showing an equivalent circuit of the TEG unit shown in FIG. FIG. 7 is an enlarged plan view showing the structure of the TEG portion shown in FIG. 5, and FIG.
It is sectional drawing which shows the structure seen from the side surface of the EG part.

In FIG. 6, the TEG section 103 is composed of a capacitor evaluation cell 112 for measuring a capacitor characteristic of a memory cell, and the capacitor evaluation cell 112 has a number of capacitors 11 corresponding to an 8-bit memory cell.
4.

One end (capacity storage electrode described later) of the capacitor 114 is connected to the lower electrode wiring 127, and a TEG lower electrode pad 128 is formed at the end. The other ends of the capacitors 114 are commonly connected to a cell plate electrode described later, and the cell plate electrode is connected to the TEG upper electrode pad 129.

In FIG. 7, the cell 11 for capacitor evaluation
Reference numeral 2 denotes a capacitance storage electrode 130 serving as one electrode of the capacitor 114, a cell plate electrode 126 serving as the other electrode of the capacitor 114, a lower electrode wiring 127, and a node contact 119 connecting the lower electrode wiring 127 and the capacitance storage electrode 130. It is composed of

Referring to FIG. 8, a lower electrode wiring 127 is formed on a silicon substrate 120 made of a P-type semiconductor via a field oxide film 121, and a first interlayer insulating film 123 is formed on lower electrode wiring 127. Have been. A bit line 104 used in a memory cell as a product is formed on the first interlayer insulating film 123, and a second interlayer insulating film 124 is formed on the bit line 104. On the second interlayer insulating film 124, a capacitance storage electrode 130 to be one electrode of the capacitor 114 is formed. An opening reaching the lower electrode wiring 127 is formed in the second interlayer insulating film 124, and the capacitor storage electrode 130 and the lower electrode wiring 127 are connected by the node contact 119 through this opening.

A cell plate electrode 126 serving as the other electrode of the capacitor 114 is formed on the capacitor storage electrode 130 via a capacitor insulating film 125 , and the capacitor storage electrode 130, the capacitor insulating film 125 , and the cell plate electrode
The capacitor 114 is constituted by 126 . In addition,
The cell plate electrode 126 is connected to the TEG upper electrode pad 129 shown in FIG.

Next, a procedure for measuring the capacitor characteristics of the memory cell using the TEG unit 103 of this embodiment will be described.
The case where the leak current characteristic of the capacitor insulating film is measured will be described as an example.

First, 0 V is applied to the lower electrode pad 128 for TEG shown in FIG.

In this state, the upper electrode pad 129 for TEG is used.
A positive or negative voltage in the range of 0 V to 3 V is applied in steps of 0.1 V. At this time, the TEG upper electrode pad 1
The current flowing from 29 is measured with an ammeter.

Thus, it is possible to measure the leakage current characteristics of the capacitor insulating film of the capacitor.

(Third Embodiment) Next, as a third embodiment of a semiconductor memory having a TEG according to the present invention, a case where the isolation characteristic between memory cells is evaluated using the TEG will be described.

FIG. 9 is a plan view showing the configuration of a third embodiment of a semiconductor memory having a TEG according to the present invention.

In FIG. 9, a semiconductor chip 2 as a product
01, four circuit blocks (memory cell arrays) each composed of a plurality of memory cells are formed.
A TEG portion 203 is formed in a desired region in the memory cell array 202 as needed. The TEG section 203 is formed in at least one memory cell array 202 depending on the measurement content.

Of the four memory cell arrays 202, a TEG section 203 is formed in the center of the memory cell array 202 shown at the lower left of FIG.
It is composed of memory cells for bits. A bit line 204 is connected to each drain region of the transistor of the memory cell, and a TEG drain electrode pad 206 is formed at an end thereof. A word line 205 is connected to each of the gate electrodes, and a TEG gate electrode pad 208 is formed at an end of the word line 205.

[0092] On the other hand, the memory cell array 202 shown in the bottom right of Figure 9, TEG portion 203 is formed on the periphery,
It is composed of 2-bit memory cells. The transistors of these memory cells have bit lines 20 in the drain region in the same manner as the TEG section 203 formed in the center.
4 are connected to each other, and the word lines 205 are connected to the gate electrodes.

Further, source lines 209 are connected to the source regions of the transistors, respectively, and TEGs are connected to the ends thereof.
Source electrode pad 207 is formed.

A wiring 210 for setting the substrate potential of the semiconductor chip 201 to a fixed potential is formed in a region outside the memory cell array 202, and a substrate potential fixing pad 211 is formed at an end thereof.

Here, the above-described TEG section 203 is incorporated in the area of the memory cell array 202 of the product, and is manufactured at the same time by the same manufacturing process as the memory cell array 202 as the product.

Therefore, as in the first embodiment, since the memory cells of the TEG section 203 are formed with the same characteristics as the memory cells of the product, the isolation characteristics between the memory cells of the TEG section 203 are reduced. Accurately reflects the isolation characteristics of

Therefore, it is possible to provide a TEG unit capable of measuring the isolation characteristics without increasing the chip area of the semiconductor memory.

Next, the configuration of the TEG unit 203 of this embodiment will be described in detail with reference to FIG.

Although FIG. 10 shows the case where the TEG portion is located at the center of the memory cell array, the configuration is the same when the TEG portion is located at the peripheral portion of the memory cell array. Omitted. The cross-sectional view of the memory cell array is the same as that shown in FIG. 4 of the first embodiment, and a description thereof will not be repeated.

FIG. 10 is an enlarged plan view showing the structure of the TEG portion shown in FIG.

In FIG. 10, an element isolation characteristic evaluation cell 212 composed of two-bit memory cells is formed of an N-type semiconductor and has a source region 215 serving as a source of a transistor.
A drain region 216 made of an N-type semiconductor and serving as a drain of the transistor; a gate electrode 217 serving as a gate of the transistor; a bit line contact 218 connecting the bit line 204 and the drain region 216;
09 and a node contact 219 connected to the source region 215.

The bit line 204 is connected to the TEG drain electrode pad 206, and the TEG gate electrode pad 2
08 is connected to the same word line 205 as the product memory cell.

The source region 215 of the transistor of the element isolation characteristic evaluation cell 212 has a TEG at its end.
Source line 20 on which source electrode pad 207 is formed
9, and one end of a capacitor (not shown) for holding data (holding voltage). The other end of the capacitor is commonly connected to each transistor in the memory cell array 202 by a cell plate electrode (not shown),
The cell plate electrode is the upper electrode pad 229 for TEG (Fig.
9) and connected to the source electrode pad 207 for TEG.
And the same voltage is applied.

Next, a procedure for measuring the isolation characteristics between memory cells using the above-described TEG unit 203 will be described.

First, two TEG gate electrode pads 2
For example, a voltage of 3 V is applied to the memory cell 08, and 0 V is applied to each of the TEG drain electrode pad 206 and the TEG source electrode pad 207 connected to one of the memory cells.

In such a state, a positive voltage is applied to the TEG drain electrode pad 206 and the TEG source electrode pad 207 connected to the other memory cell in a range of 0 to 15 V in 0.1 V steps. To TE
By measuring the current flowing from the G drain electrode pad 206 with an ammeter, the element isolation characteristics between memory cells can be measured.

In this case, the isolation characteristic between the bit line contact 218 of one memory cell and the node contact 219 of the other memory cell and the isolation characteristic between the two node contacts 219 can be measured simultaneously.

As another measurement method, two TEGs are used.
0 V is applied to each of the gate electrode pads 208 for TEG, and 0 V is applied to the source electrode pad 207 for TEG connected to one of the memory cells.

In this state, a positive voltage is applied to the TEG source electrode pad 207 connected to the other memory cell in the range of 0 to 15 V in 0.1 V steps.
By measuring the current flowing from the G drain electrode pad 206 with an ammeter, the element isolation characteristics between memory cells can be measured.

In this case, only the isolation characteristic of the leak path between the two node contacts 219 shown in FIG. 10 can be measured, and the data excluding the values of the other leak paths (between the bit contacts and the node contacts) is obtained. Obtainable.

[0111]

Since the present invention is configured as described above, the following effects can be obtained.

The TEG is simultaneously formed in the same area as the product memory array in the area where the product memory array is formed, and has interface means for independently measuring predetermined electrical characteristics. As a result, a TEG having the same characteristics as the product memory cell can be obtained.

Therefore, the TEG can be configured with a minimum necessary memory cell array, and an increase in chip area, which has been a problem in the conventional semiconductor memory TEG, can be suppressed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a first embodiment of a semiconductor memory provided with a TEG of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of a TEG unit shown in FIG.

FIG. 3 is an enlarged plan view showing a structure of a TEG unit shown in FIG.

FIG. 4 is a cross-sectional view showing a structure viewed from a side surface of the TEG section shown in FIG.

FIG. 5 is a plan view showing a configuration of a second embodiment of the semiconductor memory including the TEG of the present invention.

FIG. 6 is a circuit diagram showing an equivalent circuit of the TEG unit shown in FIG.

FIG. 7 is an enlarged plan view showing a structure of a TEG unit shown in FIG.

FIG. 8 is a cross-sectional view showing a structure as viewed from a side surface of the TEG section shown in FIG.

FIG. 9 is a plan view showing a configuration of a third embodiment of the semiconductor memory including the TEG of the present invention.

FIG. 10 is an enlarged plan view showing a structure of a TEG unit shown in FIG.

FIG. 11 is a plan view showing a configuration of a TEG used for a conventional semiconductor memory.

FIG. 12 is a plan view illustrating a configuration example of a conventional semiconductor memory including a TEG.

FIG. 13 is a plan view showing another configuration example of a conventional semiconductor memory having a TEG.

FIG. 14 is a graph showing a relationship between an etching rate and a size of a memory cell array.

[Explanation of symbols]

 1, 101, 201 Semiconductor chip 2, 102, 202 Memory cell array 3, 103, 203 TEG section 4, 104, 204 Bit line 5, 205 Word line 6, 206 Drain electrode pad for TEG 7, 207 Source electrode pad for TEG 8 , 208 TEG gate electrode pad 9, 209 Source wiring 10, 210 Wiring 11, 211 Substrate potential fixing pad 12 Transistor characteristic evaluation cell 13 Non-operating cell 14, 114 Capacitor 15, 215 Source region 16, 216 Drain region 17, 217 Gate electrode 18, 218 Bit line contact 19, 119, 219 Node contact 20, 120 Silicon substrate 21, 121 Field oxide film 22 Gate oxide film 23, 123 First interlayer insulating film 24, 124 Second interlayer insulating film 25 125 capacitor insulating film 26, 126 cell plate electrode 29,129,229 TEG upper electrode pad 112 lower electrode pad cell 127 lower electrode wiring 128 TEG capacitor rated 130 storage capacitor electrode 212 isolation characteristic evaluation cell

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/10 681C (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/108 G01R 31/28 H01L 21 / 66 H01L 21/8242

Claims (6)

(57) [Claims] A plurality of word lines and a plurality of bit lines are vertically and horizontally.
And the corresponding word line, bit line and source
Note consisting of multiple memory cells connected to the lines
A semiconductor memory having a recell array, wherein one of the plurality of bit lines is a product.
Where predetermined electrical characteristics are measured instead of memory cells
A semiconductor memory to which only the G section is connected. (2) At a predetermined position in the memory cell array.
The same as the transistor provided in the memory cell
TE comprising transistors formed simultaneously by a manufacturing method
A G memory cell; Connects only to the gate of the transistor of the TEG memory cell.
And used when evaluating the characteristics of the TEG memory cell.
TEG word line with pad Only at the drain of the transistor of the TEG memory cell
Connected when used for evaluating the characteristics of the TEG memory cell.
A TEG bit line having a pad to be Connects only to the source of the transistor of the TEG memory cell.
And used when evaluating the characteristics of the TEG memory cell.
TEG source wiring with pad 2. The semiconductor memory according to claim 1, comprising: 3. A plurality of word lines and a plurality of bit lines are arranged vertically and horizontally.
And the corresponding word line, bit line and source
Note consisting of multiple memory cells connected to the lines
A semiconductor memory having a recell array , wherein a memory cell as a product is provided in the memory cell array.
The TEG part where the predetermined electrical characteristics are measured is the word line direction
And the TEG section includes a lower electrode wiring running in the word line direction, and a capacitor connected between the source wiring and the lower electrode wiring.
Semiconductor memory consisting of Pashita. (4) At a predetermined position in the memory cell array.
And a data holding cap provided for the memory cell.
Capacitor formed at the same time with the same manufacturing method as Pasita
A capacitor evaluation cell comprising: Only one electrode of the capacitor of the capacitor evaluation cell
Connected to the Used when evaluating the characteristics of the evaluation cell
A lower electrode wiring having a pad that can be Only the other electrode of the capacitor of the capacitor evaluation cell
And used when evaluating the characteristics of the capacitor evaluation cell.
Source wiring for TEG having a pad to be
The semiconductor memory according to claim 3. (5) The predetermined position is: 5. The memory cell array according to claim 2, wherein said memory cell array is located at a central portion.
The semiconductor memory according to any one of the preceding claims. 6. The predetermined position is: 5. A memory device according to claim 2, wherein said memory cell array is a peripheral portion of said memory cell array.
The semiconductor memory according to any one of the preceding claims.