JP3196858B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an ultra-fine and high-speed semiconductor device, and more particularly to a method for manufacturing a vertical silicon pillar suitable for use in a semiconductor device in which vertical field-effect transistors are highly integrated. About.

[0002]

2. Description of the Related Art In a MOS (metal oxide semiconductor) type integrated circuit which is currently in practical use, a planar MOS electric field in which an electric conduction path (hereinafter abbreviated as a channel) is formed parallel (horizontally) to the surface of a semiconductor substrate. Effect transistor (hereinafter MOS)
FET) is used as a main element. 2. Description of the Related Art Conventionally, in order to improve the operation speed and the degree of integration of an integrated circuit, the size of each element has been reduced to reduce the area occupied on a semiconductor substrate. The above planar type MOSFE
In order to reduce the area occupied by T, it is necessary to reduce the channel length and the channel width. However, if the current size is to be further reduced, there will be many problems such as a short channel effect, deterioration due to hot carriers, and a reduction in current driving capability. That is,
It has almost reached the limit to reduce the occupied area by reducing the element size by the conventional scaling rule.

On the other hand, SOI (Silicon on I)
In a MOSFET formed on a substrate or the like, by completely depleting a semiconductor thin film portion,
It has been found that element characteristics such as operation speed can be improved, and research on such a fully depleted device has recently been conducted. In addition, research is underway to improve the drain current controllability by using a two-gate MOSFET having two gate electrodes sandwiching a channel region. Various methods have been tried to realize a device having a small occupied area, a fully depleted device, and a two-gate device as described above.

As one of the above methods, a vertical MOSFET having a channel perpendicular to the surface of a silicon substrate
Is formed. That is, the above vertical MOSFE
At T, the channel length is reduced or the channel width is reduced by forming the channel cross-section perpendicular to the silicon substrate surface while maintaining the direction of the current flowing through the channel substantially parallel to the substrate. Occupied area can be reduced. Further, in the above vertical MOSFET, a gate electrode can be easily formed around a channel region formed in a vertical direction. Therefore, by making the vertical substrate portion on which the channel region is formed into a sufficiently thin columnar (or wall) shape, the columnar substrate portion can be completely depleted. Further, in the vertical MOSFET, by forming gate electrodes along two opposing side walls of the substrate portion formed in a columnar shape, a two-gate fully-depleted vertical MOSFET can be easily realized. By using a vertical MOSFET having a vertically formed channel as a main element, a fine and high-speed semiconductor device can be manufactured.

Conventionally, SOI fully depleted vertical MOSFET
2 to 4 (Japanese Patent Application No. 3-217031). A method of manufacturing a conventional SOI fully-depleted vertical MOSFET will be described below with reference to FIGS. First, as shown in FIG. 2A, a pattern 12 of SiO2 is formed on the surface of a P-type silicon substrate 11 by ordinary photolithography and RIE. Next, as shown in FIG. 2B, the Si3 N4 film 13 is formed.
Is formed to a thickness of 100 nm.

Thereafter, as shown in FIG. 2C, the entire surface is etched by the RIE method to
Are formed on both side surfaces of the substrate. The thickness of the side wall 13a formed in this case in the horizontal direction (hereinafter, simply referred to as the thickness of the side wall 13a) is 50 nm.
It can be controlled by the thickness of the 3N4 film 13. Next, the substrate is immersed in a hydrofluoric acid solution to selectively remove only the SiO2 pattern 12 as shown in FIG. Thereafter, as shown in FIG. 2E, the P-type silicon substrate 11 is etched to a depth of 300 nm by RIE as an etching mask for the side wall 13a to form a silicon pillar 11a. As described above, the film formation technology and the sidewall formation technology
Since the side wall 13a serving as an etching mask is formed, the thickness of the silicon pillar 11a is not affected by restrictions on microfabrication.

Next, as shown in FIG.
After the formation of the Si3 N4 film 22 with a thickness of 3 mm, the entire surface is etched back by RIE to form the side walls 22a of Si3 N4 as shown in FIG. Next, FIG.
As shown in (h), thermal oxidation is performed to form an oxide film 23, and the silicon pillar 11a is insulated from the P-type silicon substrate 11 by the oxide film 23. Thereafter, as shown in FIG. 3I, the side walls 22a and 13a are removed with a phosphoric acid solution to leave the silicon pillars 11a. Next, as shown in FIG. 3 (j), after forming a gate oxide film 31 on the surface of the silicon pillar 11a, as shown in FIG. 3 (k), a gate electrode 32 is formed of a material such as polysilicon. . Then, using the gate electrode 32 formed as a mask, the silicon pillar 11a is formed.
Is implanted with arsenic (As) ions. Thus, source / drain regions are formed in portions of the silicon pillar 11a that are not covered by the gate electrode 32. FIG. 4 shows a completed example. According to this conventional example, the channel length can be controlled with high accuracy, and the thickness of the silicon pillar 11a can be set thin irrespective of the limit of fine processing, so that a fully depleted MOS semiconductor device can be manufactured.

[0008]

However, the above M
In the method for manufacturing the OSFET, the silicon pillar 11
The formation of a is performed using the Si3N4 film formed on the side wall as a mask, as shown in FIG. At this time, the cross-sectional shape of the Si3 N4 film serving as a mask is
The shape is not a rectangle but asymmetrical with curvature (see (d) of FIG. 2). It is very difficult to obtain a vertically high silicon pillar with a mask material of such a shape. In other words, with the current microfabrication technology, it is difficult to obtain vertical and good silicon pillars with the above mask shape, and the ultrafine S
There is a problem that the OI fully depleted MOSFET is difficult to manufacture. Therefore, an object of the present invention is to form a vertical silicon pillar having a good shape and to form the above-mentioned ultrafine SOI fully depleted MO.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which can easily manufacture an SFET.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film over an entire surface of a semiconductor substrate of a predetermined conductivity type, and a step of selecting a thin film material different from the insulating film. Forming a thin film with the thin film material over the entire pattern, forming a second insulating film over the entire surface, and forming a second insulating film over the entire surface by a sidewall technique. Forming a sidewall by removing the second insulating film while leaving only a peripheral portion;
A step of etching the thin film material using the sidewall formation as a mask, a step of etching the first insulating film using the thin film material remaining immediately below the sidewall formation in the etching as a mask, and a step of etching the first insulating film. The step of forming a semiconductor pillar on the semiconductor substrate by etching the semiconductor substrate using the first insulating film as a mask.

[0010]

According to the present invention, the first substrate is placed on the semiconductor substrate 11.
An insulating film 40 is formed, a selective pattern 41 is formed thereon with a thin film material, a thin film 42 is formed on the entire surface with the same thin film material, and a second insulating film 43 is formed on the entire surface. Thereafter, the second insulating film 43 is removed by a sidewall technique while leaving only the peripheral portion of the selective pattern 41 to form a sidewall 44.

The thickness of the side wall 44 in the horizontal direction is controlled by the thickness of the selective pattern 41 and the thickness of the second insulating film 43. Next, using the side wall 44 as a mask, the thin film 4
2 and the selective pattern 41 are etched. Next, using the remaining thin film 42 as a mask, the side wall 44 and the first insulating film 40 are etched. Next, the semiconductor substrate 11 is etched using the remaining first insulating film 40 as a mask to obtain a silicon pillar 11a. In this manner, fine silicon pillars can be obtained by the sidewall formation by the sidewall technique without being limited by the fine processing accuracy of selective pattern formation such as photolithography.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. First, as shown in FIG. 1A, a thermal oxide film (hereinafter abbreviated as SiO2 film) 40 is formed on the entire surface of a P-type silicon substrate 11 to a thickness of 300 nm. Thereafter, a polysilicon (polycrystalline silicon) pattern 41 is formed by ordinary photolithography and RIE. Then, as shown in FIG. 1B, a polysilicon film 42 and a SiO2 film 43, which are the same as the polysilicon pattern 41, are sequentially formed in a thickness of 30 nm and 300 nm, respectively.

Next, as shown in FIG. 1C, the entire surface is etched by RIE to form sidewalls 44 of SiO2 on both sides of the polysilicon pattern 41. In this case, the thickness of the side wall 44 in the horizontal direction can be controlled by the thickness of the polysilicon pattern 41 and the thickness of the SiO2 film 43. Next, the polysilicon pattern is etched as shown in FIG.
And the polysilicon 42 is removed. Then, FIG. 1E shows that SiO2 40 and polysilicon 42 were formed as masks for Si pillar etching by SiO2 etching. Then, the two-layer pattern (SiO
FIG. 1 shows that the P-type silicon substrate 11 was etched to a depth of 500 nm by the RIE method with the use of 240, polysilicon 42) as a mask to form a silicon pillar 11a.
(F).

Thereafter, as shown in FIG. 1 (g), the side wall 4 made of a silicon nitride (Si3 N4) film is formed.
5 is formed and oxidized to form an SOI.
(The SiO2 at this time is 46). Then, the source / drain / gate is formed conventionally. As is clear from the above, the silicon pillar is etched not by using the side wall produced by the sidewall as a mask but by the SiO 2 having a substantially vertical shape as a mask. Vertical silicon pillars can be obtained.

[0015]

As described above, according to the present invention, it is possible to obtain an ultra-fine and excellent vertical silicon pillar exceeding the fine processing of photolithography, and to form an ultra-fine SOI fully depleted MOSFET by using this. Thus, there is an effect that a high-speed semiconductor device having an ultra-high density of integration can be manufactured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of an SOI fully depleted MOSFET according to an embodiment of a method of manufacturing a semiconductor device of the present invention.

FIG. 2 shows a conventional SOI fully depleted MOSFET.
It is explanatory drawing of the manufacturing process which concerns on the manufacturing method of FIG.

FIG. 3 is an explanatory view of a conventional manufacturing process following FIG. 2;

FIG. 4 is an explanatory diagram of a completed example of the SOI fully depleted MOSFET.

[Explanation of symbols]

 11 P-type silicon substrate 11a Silicon pillar 13a, 22a, 44 Side wall 23 Insulating film (oxide film)

Continuation of the front page (56) References JP-A-2-263473 (JP, A) JP-A-5-198817 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29 / 78 H01L 29/786 H01L 21/336 H01L 21/762 H01L 21/8242 H01L 27/108

Claims (1)

(57) [Claims] A first conductive type semiconductor substrate on the entire surface of the semiconductor substrate;
Forming a selective pattern using a thin film material different from the insulating film; forming a thin film using the thin film material over the pattern; Forming a side wall by removing the second insulating film while leaving only the peripheral portion of the selective pattern portion by a sidewall technology; and forming the thin film using the side wall forming product as a mask. A step of etching a material; a step of etching the first insulating film using the thin film material remaining immediately below the sidewall formation in the etching as a mask; and a semiconductor substrate using the first insulating film remaining in the etching step as a mask. Forming a semiconductor pillar on the semiconductor substrate, including a step of etching the semiconductor substrate.