JP3196409B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit (hereinafter, referred to as a PLL circuit), and more particularly to a PLL circuit used in a mobile communication device such as an automobile telephone or a cordless telephone to perform phase synchronization.

[0002]

2. Description of the Related Art In recent years, mobile communication devices such as automobile telephones and cordless telephones have become widespread.
Circuits are an important part of these communication devices.

FIG. 4 is a block diagram showing a conventional PLL circuit. In FIG. 4, an input signal 5 is provided to a phase comparator 1, and the phase comparator 1 compares the input signal 5 with an output signal 6 of a voltage controlled oscillator (VCO) 4 to detect a phase error, and An error signal is provided to the charge pump circuit 2. The charge pump circuit 2 supplies a current corresponding to the phase error signal to the loop filter 3, and the loop filter 3 removes unnecessary frequency components such as input noise and phase jitter and supplies the same to the voltage controlled oscillator 4. Voltage controlled oscillator 4
Oscillates a signal having a frequency corresponding to the output of the loop filter 3 and outputs the signal as an output signal 6, and the phase comparator 1
Feedback to

[0004] The operation of the PLL circuit shown in FIG. 4 will be described in more detail. The input signal 5 and a part of the output signal 6 of the voltage controlled oscillator 4 oscillating at the free-running frequency are phase-shifted by the phase comparator 1. The signals are compared and a phase error signal is output. This phase error signal is converted into a current by the charge pump circuit 2 and applied to the loop filter 3, where noise and phase jitter components superimposed on the input signal 5 are removed and applied to the control input of the voltage controlled oscillator 4. Since the output signal 6 of the voltage controlled oscillator 4 is given to the phase comparator 1, this circuit forms a loop, and is locked when the phases of the input signal 5 and the output signal 6 match. The bandwidth of the loop filter 3 is determined by a balance between the amount of residual noise during tracking in the locked state and the response speed.

By the way, when noise is superimposed on an input signal or phase jitter is superimposed on a PLL circuit, a loop follows these disturbances, and thus frequency noise is generated. To reduce this, it is necessary to narrow the bandwidth of the loop filter, but this has the disadvantage of slowing the transient response and lengthening the time required for phase locking of the loop.

In order to avoid such a drawback, FIG.
A method as shown in FIGS. 6 and 7 has been proposed.

FIG. 5 has been proposed in Japanese Patent Application Laid-Open No. 61-87427. In the PLL circuit shown in FIG.
A wide-band loop filter 7 and a narrow-band loop filter 8 are provided in place of the loop filter 3, and these can be switched by switch circuits 9 and 10. And
At the time of channel switching, a high-speed response is realized by using the wide band filter 7, and at the time of locking, low noise is realized by switching to a narrow band filter.

[0008] The example shown in FIG.
No. 19, in which one loop filter 3 is used, and a resistor 3 included in the loop filter 3 is used.
1, a switch circuit 32 is connected to both ends of the switch circuit 3.
By switching 2, the time constant of the loop filter 3 is switched to realize high-speed lock and low noise.

The example shown in FIG. 7 is disclosed in Japanese Patent Laid-Open No. 62-9252.
No. 1, the charge pump current of the charge pump circuit 2 is increased at the time of channel switching to realize a high-speed response, and at the time of lock, the charge pump current is set to a normal level to realize low noise. is there.

[0010]

However, in the example shown in FIG. 5, when the band is brought close to the lock by the wide-band loop filter 7 and then switched to the narrow-band loop filter 8, the narrow-band loop filter immediately before the switching is switched. 8, the voltage is pushed back to near the output voltage of 8, and then a lock occurs due to the response of the narrow band loop filter 8, and there is a disadvantage that there is almost no advantage of using the wide band filter 7. Further, in FIG. 6, since the capacitor is charged through the resistor, there is a disadvantage that a significant improvement in the channel switching speed cannot be expected. The example shown in FIG. 7 also has a drawback that, as in the case of the resistance switching system, a significant improvement in the channel switching speed cannot be expected.

Therefore, a main object of the present invention is to provide a PLL circuit capable of realizing a high-speed response by quickly charging a capacitor constituting a loop filter to a voltage equal to a voltage in a locked state. To provide.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an output signal of a phase comparator for detecting a phase error between an input signal and an output signal of a voltage controlled oscillator. in the connected PLL circuit so as to input to the voltage controlled oscillator via a filter,
The loop filter includes at least two capacitors,
Separate for each of at least two capacitors
That charge and discharge the corresponding capacitor quickly.
Charge pump and separately provided when switching the oscillation frequency
Switching means for switching the charge pump .

[0013]

In the PLL circuit according to the present invention, a charge pump circuit is connected to each of the capacitors constituting the loop filter in addition to the normal charge pump circuit connected to the loop filter, and the charge pump is switched when the channel is switched. By means, the capacitor is charged at a high speed to realize a high-speed response. Further, by adjusting the charging current to each capacitor in accordance with the capacitance of the capacitor, the rising of the voltage of each capacitor can be made uniform, which is the most effective.

[0014]

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, a phase comparator 1, a charge pump circuit 2, and a voltage controlled oscillator 4 are configured in the same manner as in FIG. 4, but in addition to the charge pump circuit 2, two charge pump circuits 21, 22 and a charge pump switchover are performed. Means 50 are provided. The error signal from the phase comparator 1 is input to the charge pump circuit 2, the error signal from the phase comparator 1 and the external control signal 40 are input to the charge pump switching means 50, and the output of the charge pump switching means 50 is The signals are input to the charge pump circuits 21 and 22. The loop filter 30 includes resistors 33, 34, 35 and capacitors 36, 37. Resistors 33 and 34
Is connected in series between the output terminal of the charge pump circuit 2 and the input terminal of the voltage controlled oscillator 4, a capacitor 36 is connected between the input terminal of the voltage controlled oscillator 4 and the ground, and connected to the input terminal of the voltage controlled oscillator 4. The output of the charge pump circuit 21 is connected. Further, a series circuit of a resistor 35 and a capacitor 37 is connected between a connection point between the resistors 33 and 34 and the ground, and an output of the charge pump circuit 22 is connected to a connection point between the resistor 35 and the capacitor 37.

The operation of the embodiment shown in FIG. 1 will be described. Similar to the description of FIG. 4, the locked state is established when the phase of the output signal 6 of the voltage controlled oscillator 4 matches the phase of the input signal 5. . In the locked state, the potential difference between both ends of each of the capacitors 36 and 37 in the loop filter 30 becomes a constant voltage determined by the set frequency. In general,
This constant voltage corresponds to the voltage controlled oscillator 4 corresponding to the set frequency.
Input voltage. In the first embodiment of the present invention,
The charge pumps 21 and 22 are turned on by the charge pump switching means via the external control signal 40, and the capacitors 36 and 37 are quickly charged until the voltage reaches a constant voltage determined by the set frequency, thereby enabling high-speed lock. After locking, the charge pump circuits 21 and 22 connected to the capacitors 36 and 37 are turned off, and are in a normal lock state (low noise lock state).

FIG. 2 is a specific block diagram showing a main part of the first embodiment of the present invention. In FIG. 2, charge pump circuits 2, 21, and 22 are respectively composed of transistors 23
And 24, 25 and 26, and 27 and 28. One output of phase comparator 1 is provided to the base of transistor 23, and the other output is provided to the base of transistor 24. Further, in order to switch whether or not each output of the phase comparator 1 is supplied to the charge pump circuits 21 and 22, the inverter 11, the OR gate 12, and the
A switching circuit including D gate 13 is provided. The external control signal 40 is supplied to one input terminal of the AND gate 13, inverted by the inverter 11 and supplied to one input terminal of the OR gate 12. One output of the phase comparator 1 is applied to the other input terminal of the OR gate 12, and AND
The other input of the gate 13 is supplied with the other output of the phase comparator 1. The output of the OR gate 12 is a transistor 25
And 27, and the output of AND gate 13 is applied to the bases of transistors 26 and 28.

FIGS. 8 and 9 are waveform diagrams of respective parts of FIG. 2, and FIG. 10 is a diagram showing the response characteristics of the first embodiment of the present invention and the conventional example in comparison.

Next, a specific operation of the first embodiment of the present invention will be described with reference to FIGS. 1, 2, and 8 to 10. First, a change in the direction of increasing the input voltage of the voltage controlled oscillator 4 has a waveform as shown in FIG. That is, at the time of channel switching, the external control signal 4 shown in FIG.
When “0” becomes “H” level for a certain period as shown in FIG. 8A, the AND gate 13 is opened. Further, the external control signal 40 is inverted by the inverter 11, and the external control signal 40 shown in FIG.
, The OR gate 12 is opened. Therefore, each output signal of the phase comparator 1 shown in FIGS.
The signals are gated by the ND gate 13 and applied to the transistors 25, 26, 27, 28 of the charge pump circuits 21, 22 as signals shown in FIGS. 8 (e) and 8 (f), and these transistors 25 to 28 are turned on. Alternatively, the charge pump circuits 21 and 22 are turned off to be in the operating state. At this time, according to the output signal of the phase comparator 1, the charge pump circuit 21 rapidly charges the capacitor 36 as shown in FIG.
Charge 7 quickly.

Thereafter, when the external control signal 40 becomes "L" level, the OR gate 12 and the AND gate 13 are closed, and the transistors 25, 26, 27, 28 of the charge pump circuits 21, 22 are turned off. Then, the outputs of the charge pump circuits 21 and 22 are in a high impedance state, and a low noise mode is set in which only the charge pump circuit 2 operates.

Similarly, the operation of each part in the direction of decreasing the input voltage of the voltage controlled oscillator 4 has a waveform as shown in FIG. As described above, the charge pump circuit 21 is directly connected to the capacitor 36, and the charge pump circuit 22 is connected to the capacitor 37.
As shown in (a), a remarkably high-speed response can be realized as compared with the conventional method of charging through a resistor (FIG. 10B).

When the charging speed of the capacitors 36 and 37 varies, the charge pump current is affected by the slowest charging speed, and the charge pump current is controlled according to the capacitance of the capacitors 36 and 37 to suppress the variation of the charging speed. Being able to set it will be more effective.

FIG. 3 shows a PLL according to a second embodiment of the present invention.
FIG. 2 is a block diagram of a circuit in which the same elements as those in FIG. 1 are denoted by the same reference numerals.

In the second embodiment, in the loop circuit comprising the phase comparator 1, the charge pump circuit 2, the loop filter 30, and the voltage controlled oscillator 4 shown in FIG. A frequency divider 50 is provided between the input side and the input side.

When the output signal 6 from the voltage controlled oscillator 4 is input to the frequency divider 60, the frequency of the output signal 6 changes according to the set frequency division ratio. The output signal 61 of the frequency divider 60 is input from the input side of the phase comparator 1 and the input signal 5
After that, the same operation as in the first embodiment is performed. Therefore, the operation waveform is the same as that of the first embodiment, and is as shown in FIGS. When the frequency divider 60 is used, the oscillation frequency can be set in a wider range as compared with the first embodiment shown in FIG. 1, and is suitable for setting a higher frequency.

[0025]

As described above, according to the present invention, at least two charge pump circuits are provided, and the capacitor of the loop filter is rapidly charged by one of the charge pump circuits in the high-speed mode. High-speed response can be realized, and a sufficient noise suppression effect can be obtained after locking.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a first embodiment of the present invention.

FIG. 2 is a specific block diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a schematic block diagram of a second embodiment of the present invention.

FIG. 4 is a schematic block diagram of a conventional basic PLL circuit.

FIG. 5 is a block diagram showing a conventional PLL circuit configured to switch between a wide band loop filter and a narrow band loop filter.

FIG. 6 is a block diagram of a conventional PLL circuit in which a time constant of a loop filter is switched.

FIG. 7 is a block diagram of a conventional PLL circuit that controls a charge pump current supplied to a charge pump circuit.

8 is a waveform chart of each part in FIG. 2, and particularly shows an operation in a direction of increasing the input voltage of the voltage controlled oscillator.

FIG. 9 is a waveform diagram of each part in FIG. 2, showing a case where the voltage-controlled oscillator operates in a direction to reduce the input voltage.

FIG. 10 shows first and second embodiments of the present invention and a conventional P
FIG. 3 is a diagram illustrating a response characteristic of an LL circuit in comparison.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2, 21, 22 charge pump circuit 4 voltage controlled oscillator 11 inverter 12 OR gate 13 AND gate 23-28 transistor 30 loop filter 33, 34, 35 resistor 36, 37 capacitor 50 charge pump switching means 60 frequency divider

Claims (1)

(57) [Claims] An output signal of a phase comparator for detecting a phase error between an input signal and an output signal of a voltage controlled oscillator is connected to the voltage controlled oscillator via a charge pump and a loop filter. In a PLL circuit, the loop filter includes at least two capacitors.
See, for each of said at least two capacitors
Separately provided to rapidly charge and discharge the corresponding capacitor
That a charge pump, characterized by comprising a switching means for switching the charge pump which is individually provided at the time of switching the oscillation frequency P
LL circuit.