JP3185229B2 - Pulse signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal processing circuit, and more particularly, to a pulse signal processing circuit suitable for use in a circuit for outputting a delayed pulse signal obtained by finely delaying an input pulse signal by several picoseconds.

[0002]

2. Description of the Related Art For example, a process of delaying an input pulse signal by a very small time unit such as several picoseconds is performed, and a delayed pulse signal is output while maintaining the duty of the input pulse signal waveform. A known pulse signal generating circuit is known.

FIG. 3 is a block diagram of a conventional pulse signal generation circuit, and FIG. 4 is a circuit diagram for slicing a ramp waveform signal output from a ramp waveform generator used in the pulse signal generation circuit. FIG. 5 is a circuit diagram of a pulse signal processing circuit for controlling the timing of generating a pulse signal by adjusting the threshold level, and FIG. 5 is a waveform diagram for explaining the operation of each unit in FIG.
As is clear from FIG. 3, this pulse signal generation circuit
An input pulse signal (A) input through the buffer amplifier 20 and an input pulse signal (B) obtained by inverting the input pulse signal (A) are input to the first and second comparators 2.
1 and 22 respectively. These comparators 2
1, 22 are the input pulse signals (A) and (B)
Is sliced at the level of the pulse generation voltage (C), and the processing pulse signals (D) and (E) are generated at a predetermined timing.

[0004] These processing pulse signals (D) and (E) are supplied to first and second ramp waveform generators 23 and 2.
4 given. First and second ramp waveform generators 2
3 and 24 generate ramp waveform signals (F) and (G) as shown in FIG. 5 based on the given processing pulse signals (D) and (E), which are provided in the next stage. To the non-inverting input terminals of the third and fourth comparators 25 and 26, respectively.

On the other hand, third and fourth comparators 2
The reference voltage Vref is applied to the inverting input terminals 5 and 26, so that the threshold levels shown in FIG. 5H are set. The threshold level (H) is made variable, and by varying the level at which the ramp waveform signals (F) and (G) are sliced, the delayed pulse signal (I) output from each of the comparators 25 and 26 is changed. ) And (J) are controlled.

[0006]

The pulse signal processing circuit comprising the first ramp waveform generator 23 and the third comparator 25 in FIG. 3 is configured as shown in the circuit diagram of FIG. The pulse signal processing circuit including the ramp waveform generator 24 and the fourth comparator 26 has the same configuration.) That is, the first ramp waveform generator 23 includes the transistors Q1, Q2, the capacitor C, the constant current source I, and the like. Further, a differential connection circuit formed by the transistors Q4 and Q5, Q6, a resistor R connected to the collector of the transistor Q5, and a transistor Q8 for output and a base for supplying a reference voltage Vref to the bases of the transistors Q6. Transistor Q7
Thus, the third comparator 25 is formed.

In the pulse signal processing circuit configured as described above, as shown in the waveform diagram of FIG.
As the threshold level (H) set in the comparators 25 and 26 approaches the high level of the ramp waveforms (F) and (G), the falling edge of the delay pulse signal (J) and the delay pulse signal (I) Overlaps with the rising edge of Similarly, the falling edge of the delayed pulse signal (I) and the rising edge of the delayed pulse signal (J) overlap.

Therefore, when these delayed pulse signals (I) and (J) are applied to the set input terminal S and the reset input terminal R of the RS flip-flop 27, respectively, the set input terminal S and the reset input terminal R
, Respectively, will be input. As described above, it is not preferable that both the inputs of the RS flip-flop 27 become “H”. In such a case, the set timing and the reset timing may be shifted. Therefore, in this case, there is a disadvantage that the delayed pulse signal (K) cannot be output with a proper delay. In the above description, the case of a positive logic circuit has been described. However, the same problem occurs in the case of a negative logic circuit in which all polarities are inverted.
The present invention has been made in view of the above problems, and has disclosed a rising (or rising ) pair of delayed pulse signals formed by slicing a ramp waveform signal output from a ramp waveform generator at a predetermined level.
It is an object to provide a margin between a falling edge and a falling edge (or a rising edge) .

[0009]

A pulse signal processing circuit according to the present invention gradually changes a rising edge or a falling edge of an input first pulse signal and outputs the resulting signal as a first ramp waveform signal. A first ramp waveform generator, and a second ramp waveform generator that inverts the first pulse signal.
Rising edge or falling edge of the pulse signal
The second ramp waveform signal
A second ramp waveform generator for outputting as No., the first
1, the first output from the second ramp waveform generator,
Slicing the second ramp waveform signal at a threshold level
As a result, when the first and second pulse signals are generated,
Also, by changing the threshold level,
The timing at which the first and second pulse signals are generated is controlled, and the first and second pulse signals are slightly delayed .
1, a pulse signal generating circuit for generating a second delayed pulse signal, said first, a change gradient of the rising or falling edge of the second delay pulse signal, the falling of both the delay pulse signal
Rising (or falling) and falling (or falling)
And a change gradient correction circuit that changes steeply so as to have a margin between the change gradient and the rise .

[0010]

The operation is output from the first and second ramp waveform generators.
Generated by slicing the first and second ramp waveform signals
First, first, second to the second pulse signal is slightly delayed
By changing the change gradient of the rise or fall of the delay pulse signals steeply, falling in the first, second delay pulse signal outputted from the pulse signal processing circuit
Rising (or falling) and falling (or falling)
A margin can be provided between the first and second delay pulse signals to prevent the inconvenience that both of the first and second delay pulse signals have the same logic level.

[0011]

FIG. 1 is a main part circuit diagram showing an embodiment of a pulse signal processing circuit according to the present invention. As apparent from FIG. 1, the pulse signal processing circuit of the present embodiment includes a ramp waveform generator 1, a pulse signal generation circuit 2, a change gradient correction circuit 3, and the like.

As is apparent from FIG. 1, the pulse signal processing circuit of this embodiment has the following configuration of the pulse signal processing circuit portion of the pulse signal generation circuit shown in FIG. 3, that is, the circuit portion of FIG. It was done. That is, the ramp waveform generator 1 is constituted by the transistors Q1, Q2, the capacitor C, the constant current source I, etc., and is connected to a differential connection circuit formed by the transistors Q4, Q5, Q6, and the collector of the transistor Q5. The pulse signal generating circuit 2 includes the resistor R, the output transistor Q8, the transistor Q7 for supplying the reference voltage Vref to the base of the transistor Q6, and the like.

The structures of the ramp waveform generator 1 and the pulse signal generation circuit 2 are the same as those of the conventional pulse signal processing circuit shown in FIG. 4, and in the case of the present embodiment, the pulse signal thus configured In the processing circuit, a change gradient correction circuit for sharply changing the falling gradient of the output pulse signal waveform is added.

The change gradient correction circuit 3 connects the collector of the transistor Q2 forming the ramp waveform generator 1 and the collector of the transistor Q5 forming the pulse signal generation circuit 2 as shown in FIG. This is configured by connecting a diode Q3 to the collector of the transistor Q2.

In the pulse signal processing circuit according to the present embodiment, when the base voltage of the transistor Q1 becomes "L" and then the base voltage of the transistor Q5 becomes lower than the base voltage of the transistor Q6, The collector voltage of the transistor Q5 becomes "H". In addition,
In this series of operations, since the transistor Q2 is off, no collector current flows through the transistor Q2. In this case, when the deflection width of the base voltage of the transistor Q1 and [Delta] V, if the change potential of the emitter of the transistor Q2 is only [Delta] V, the transistor Q2 is turned on at that time.

In this state, when the base voltage of the transistor Q1 becomes "H", its output becomes "L". However, the emitter of the transistor Q2 becomes "H" while charging the capacitor C. A transient current flows through the collector of the transistor Q2. Since the transient current flows through the load resistor R, the change gradient of the falling edge of the output waveform (arrow portion in the waveform diagram of FIG. 2) becomes steep. As shown in the waveform diagram of FIG. 2 , the change gradient at this time is between the falling edge of the delayed pulse signal (J) and the rising edge of the delayed pulse signal (I) and the falling edge of the delayed pulse signal (I). And the rising edge of the delayed pulse signal (J) has a steep enough margin.

If such a pulse signal processing circuit is used for both the set S side and the reset R side of the RS flip-flop 27 as shown in FIG. 3, a ramp waveform signal (as shown in FIG. 2) Even if the threshold level (H) for slicing F) and (G) becomes high, the fall time of the logic level of the signals (I) and (J) input to the set S side and the reset R side becomes very long. Can be shorter
You. Therefore, between the two pulse signals (I) and (J) , that is, as is clear from the waveform diagram of FIG.
The falling of the pulse signal (J) and the falling of the pulse signal (I)
Between the rising edge and the falling edge of the pulse signal (I).
Since a margin can be provided between the rising edge of the pulse signal (J) and the logical level of these pulse signals (I) and (J) output from the signal processing circuit, both of them do not become "H" level. Can be

Therefore, the pulse signal (I),
If (J) is supplied, the above - mentioned RS flip-flop 2
7, both the set S side and the reset R side are "H".
, And the RS flip-flop 27 can be operated at high speed.
Although the above description has been given of the case of the positive logic circuit,
When a negative logic circuit is formed by inverting all the polarities, the same operation can be performed, and the same operation and effect as those described in the above embodiment can be obtained.

In the case of the present embodiment, the RS flip-flop 27 is driven at the rising edge, so that the falling gradient of the delay pulse signals (I) and (J) is set to be steep. Was. However, when the falling edges of the delayed pulse signals (I) and (J) are used, the rising gradient of the delayed pulse signals (I) and (J) may be made steep. The pulse signal processing circuit according to the embodiment can be used not only as a circuit for driving the RS flip-flop, but also for various pulse driving circuits requiring high-speed operation.

[0020]

According to the present invention as described above, first, a first output from each of the second <br/> ramp waveform generator, generated by slicing a second <br/> ramp waveform signal The rising or falling change gradient of the first and second delayed pulse signals is changed to the rising (or falling) of both delayed pulse signals.
Merge) between falling (or rising)
Since so as to sharpen the degree to have a down, both delay
It is possible to prevent the inconvenience that the logic levels of both pulse signals become the same logic level, and it is possible to increase the speed of circuits using pulse signals that are delayed for a short time with high accuracy using a ramp waveform generator. At the same time, various logic circuits such as flip-flops can be favorably driven at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a main part of an embodiment of a pulse signal processing circuit of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a configuration diagram of a pulse signal generation circuit showing an example of a state in which the pulse signal processing circuit of the present embodiment is used.

FIG. 4 is a circuit diagram showing a conventional example of a pulse signal processing circuit used in the pulse signal generation circuit of FIG. 3;

FIG. 5 is a waveform chart for explaining the operation of each part of the circuits of FIGS. 3 and 4;

6 is a waveform diagram showing a waveform of an output pulse signal of a pulse signal processing circuit when a threshold level of a comparator in FIG. 3 approaches a maximum level of a ramp waveform signal.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 ramp waveform generator 2 pulse signal generation circuit 3 change gradient correction circuit 4 connection wiring (A) input pulse signal (B) inverted input pulse signal (F) ramp waveform signal (G) ramp waveform signal (I) delayed pulse signal (J) Delay pulse signal

Claims (1)

(57) [Claims] A first ramp waveform generator that gradually changes a rising edge or a falling edge of an input first pulse signal and outputs the first ramp signal as a first ramp waveform signal; , A second pulse signal obtained by inverting the first pulse signal.
Change the rising or falling edge gradient
Slowly changing and outputting as a second ramp waveform signal
That a second ramp waveform generator, the output from the first, the second ramp waveform generator
Sliding the first and second ramp waveform signals at the threshold level
To generate first and second pulse signals.
And by changing the threshold level
A pulse signal generation circuit for controlling the timing of generating the first and second pulse signals and generating first and second delayed pulse signals slightly delayed from the first and second pulse signals; The rising or falling change gradient of the first and second delayed pulse signals is determined by the rising and falling edges of both delayed pulse signals.
Or between falling and falling or rising
And a change gradient correction circuit that changes steeply so as to provide a margin to the pulse signal processing circuit.