JP3182335B2 - Current cell type DA converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current cell type DA converter, and more particularly, to a current cell type DA converter capable of eliminating a variation in output current characteristics having a slope and improving its linearity.

[0002]

2. Description of the Related Art A DA converter (digital-to-analog converter) is a device for converting a digital signal into an analog signal. At present, similarly to an AD converter (analog-to-digital converter), a digital audio device,
It is widely used in video equipment, communication equipment, measurement fields, control fields, and the like.

[0003] In particular, the current cell type DA converter is characterized by a very high conversion speed because an analog value is represented by a current, and is frequently used in fields such as image signal processing. Generally, image signals are RGB (Red, Green, Blue)
, And corresponding to these signals, the DA
Converters are also often used in three channels (3ch), and many are converted into macrocells as 3ch-DA converters.

FIG. 9 shows an example of a conventional current cell type DA converter. The current cell type DA converter 30 includes a decoder 12 for decoding a digital signal and outputting a decoded signal, and a current cell block 14 in which a number of current cells 32 corresponding to the resolution of an analog signal are arranged in a matrix. Have been. The resolution of an analog signal is determined by the number of bits of a digital signal, and is represented by LSB (Least Significant Bit). For example, when an n-bit digital signal is converted to an analog signal, the resolution of the analog signal is 2 ⁿ LSB
Becomes

FIG. 10A shows an example of a conventional current cell. The current cell 32a includes three P-type MOS transistors (hereinafter, referred to as PMOS) 18, 20,
22. Here, the source terminal of the PMOS 18 is connected to the power supply, and the drain terminal thereof is connected to the PMOS2.
0 and 22 are connected to the source terminal, and a constant voltage is applied to the gate terminal to become a constant current source operating in a saturation region. Also,
The drain end of the PMOS 20 is connected to the ground, and the gate end is connected to the decode signal line 24. The drain end of the PMOS 22 is connected to an output signal line (IOU).
T) 28, and the gate end thereof is connected to the inverted decode signal line 26.

In the current cell 32a, the PMOS2
0 and the PMOS 22 operate as switches, and the constant current flows to the output when the decode signal is at a high level and flows to the ground when the decode signal is at a low level. Note that the current cell 3 in the illustrated example is
In 2a, a constant voltage is supplied instead of connecting the inverted decode signal line 26 to the gate end of the PMOS 22. In this case, there is an advantage that switching noise can be reduced.

FIG. 10B shows another example of a conventional current cell. This current cell 32b is connected to the series-connected 2
And two PMOSs 18 and 20. Here, the source terminal of the PMOS 20 is connected to the power supply, and the gate terminal thereof is connected to the decode signal line 24. Also,
The source terminal of the PMOS 18 is connected to the output signal line 28,
A constant voltage is applied to a gate end of the gate, and the gate is a constant current source that operates in a saturation region.

In the current cell 32b, a constant current is not always supplied unlike the current cell 32a, but a current is output to the output signal line 28 only when the current cell 32b is turned on. Therefore, the current cell 32b has an advantage that the inverted decode signal line 26 and the PMOS 22 are not required as compared with the current cell 32a. In the illustrated current cell 32b, the positions of the PMOSs 18 and 20 are interchanged. FIG. 10 (a)
The current cells 32a and 32b shown in FIGS. 10B and 10B, respectively, are composed of PMOS. However, the current cell of the present invention is not limited to these, and is shown in FIGS. 10C and 10D, for example. Current cells 32c and 32
As shown in d, N-type MOS transistor (NMOS) 1
9, 21, and 23.

In the current cell type DA converter 30, all the current cells 32 (32a, 32b, 32c,
32d) is connected to the output signal line 28 in parallel. Next, the operation of the current cell type DA converter 30 will be described.

In this current cell type DA converter 30, when an n-bit digital signal is input to the decoder 12, it is decoded by the decoder 12 (2 ⁿ −
1) A decoded signal is output. Note that, among these decoded signals, the same number of decoded signals as the digital signal value (digital code) are activated.
For example, 3 where the digital code is 100 (binary number)
When a bit digital signal is input, 7 (= 2 ³ -1) decoded signals obtained by decoding the digital signal are output, and among the 7 decoded signals, 4 decoded signals are in an active state. Becomes

Subsequently, these decode signals are input to the current cell block 14. When an active state, that is, a high-level decode signal is input to the current cell 32a shown in FIG. 10A, the PMOSs 20 and 22 are turned off and on, respectively. Therefore, the PMOS
The constant current I (for 1 LSB) of the PMOS 18 flows through the output signal line 28 through the NMOS 22.

On the other hand, the inactive state of the current cell 32,
That is, when a low-level decode signal is input, P
MOSs 20 and 22 are turned on and off, respectively. Therefore, the constant current I of the PMOS 18 is
Flows through 0 to the ground side.

As described above, in the current cell block 14, only the current cell 32 corresponding to the decode signal in the active state is turned on, and the total current output from all the current cells 32 turned on is the output signal line. 28. Although not shown, this current is converted to a predetermined voltage level by a terminating resistor and output as an analog signal having a voltage level corresponding to the input digital code.

The current cell type DA converter 30 outputs a predetermined current, that is, a current of 1 LSB to the output signal line 28 every time one current cell 32 is turned on, so that the input digital signal is output. It outputs an analog signal having a voltage level corresponding to the signal.
Therefore, using the same current cell 32 so that the same amount of current is output from each current cell 32,
That is, it goes without saying that the output current characteristics of each current cell 32 are made exactly the same.
Further attention must be paid to the arrangement and the wiring between the current cells 32.

However, in a semiconductor device, non-uniformity occurs due to a concentration distribution in a diffusion process accompanied by a heat treatment in a manufacturing process, an error in a processed shape caused by a lens distortion of an exposure device, and the like. Further, in some cases, for example, a semiconductor chip may be invisiblely warped due to stress at the time of plastic encapsulation and may have distortion. Generally, MOS products are liable to cause performance variations of internal transistors due to the influence of stress strain. In a relatively small chip, it is common to arrange a transistor requiring relative accuracy at the center of each side, avoiding the corners, and the ideal part is the center.

When an analog section and a digital section are mixedly mounted on a large semiconductor chip, it is necessary to provide a predetermined space between the analog section and the digital section in order to avoid mutual noise interference. However, when the analog section is arranged at the center of the semiconductor chip, the space between the analog section and the digital section needs to be provided all around the analog section, which causes a problem that the layout area increases.

For this reason, in a semiconductor chip in which an analog section and a digital section are mixedly mounted, as shown in FIG. 11, the analog section 42 is arranged at a corner of the semiconductor chip 40, and the analog section 42 and the digital section 44 are connected to each other. Are provided so as not to receive the interference of the noise 70.
By arranging the analog section 42 at the end of the semiconductor chip 40, more preferably at the corner of the semiconductor chip 40, the analog section 42 and the digital section 44
There is an advantage that the layout area required for the space between the two can be reduced and the analog signal can be wired to the output pad 46 with the shortest distance.

However, the above-mentioned stress concentrates in this portion. The stress increases as the size of the semiconductor chip increases. Therefore, when an analog part and a digital part are mixedly mounted on a plastic-sealed MOS product, the influence of stress cannot be avoided. Further, a temperature distribution due to heat generated by the semiconductor chip itself during operation causes variations in operation characteristics at an element level.

For this reason, depending on the positions where the current cell blocks 14 are arranged and the positions (order) where the respective current cells 32 are arranged, for example, an inclined shape, a mountain shape, a valley shape, or these shapes are formed between the current cells 32. There is a problem that the output current characteristics of the combined shapes vary, and as a result, the amounts of current output from the respective current cells 32 differ. Of these, variations between the exposure step and the diffusion step are generally evaluated in advance to determine the size of the constant current transistor serving as a current cell. That is, the gate length is selected to be large so as to absorb the above-mentioned variation to some extent.

For example, when the current cell block is arranged at the end of the semiconductor chip, if the output current characteristics between the current cells arranged in a line vary, the variation will always be inclined. For example, as shown in FIG. 12, seven current cells 1 in which current cell blocks are arranged in a row are provided.
2, 3, 4, 5, 6, and 7, and assuming that the output current characteristic of the current cell 4 disposed at the center thereof is ± 0, the current cell 1 arranged at one end side , 2
And 3 have a positive output current characteristic in an inclined manner, and the positive output current characteristic is maximized in the endmost current cell 1. On the other hand, the current cells 5, 6, and 7 arranged on the other end side have negative output current characteristics in an inclined manner, and the negative output current characteristics become maximum in the current cell 7 at the end.

Hereinafter, this problem will be described more specifically by taking as an example a case where a 3-bit digital signal is converted into an analog signal having a resolution of 8 LSB. In order to convert a 3-bit digital signal into an analog signal having a resolution of 8 LSB, that is, to obtain an analog output signal having a voltage level of 0 to 7, seven current cells 1, 2, 3, and 4, 5, 6, and 7 are required, and the description will be made on the assumption that there is a slope-like variation between these current cells 1 to 7.

FIGS. 13A, 13B and 13C show the order in which the current cells are sequentially turned on from one end to the other end (or from the other end to one end). A schematic diagram showing the order in which the current cells are turned on alternately from the center to both ends (or from the end to the center); and a schematic diagram showing the order in which the current cells are turned on randomly. is there. The method shown in FIG.
This is a method disclosed in a digital-analog converter according to Japanese Patent Laid-Open No. 1-123223.

FIGS. 14 (a), (b) and (c)
13 is an output current characteristic diagram when the current cells are turned on in the order shown in FIGS. 13 (a), (b) and (c), respectively. In FIGS. 14A, 14B and 14C, the current cells that have been turned on are marked with a circle. In all the cases of FIGS. 14A, 14B and 14C, when the digital code is 0, all the current cells 1 to 7 are off, and the sum of the output current characteristics is of course ± 0. is there.

First, as shown in FIGS. 13 (a) and 14 (a), digital codes 1, 2, 3, 4, 5, 6
And at time 7, current cells 7, 6, 5, 4, respectively
When 3, 2, and 1 are turned on, the current cell 7 is turned on at the time of digital code 1, so that the sum of the output current characteristics becomes -3. The sum of the output current characteristics at 5, 6, and 7 is -5, -6, -6, -5, -3, and ±, respectively.
It becomes 0.

As described above, when the current cells 1 to 7 are turned on in order from one end to the other end, the sum of the output current characteristics becomes ± 0 when the digital code 7 is used. It turns out that it is biased to the minus side. Also,
Although not shown, when the current cells 1 to 7 are turned on in order from the other end to the one end, the total output current characteristics are:
The value is ± 0 at the time of the digital code 7, but it is biased to the plus side at other times.

Next, as shown in FIGS. 13 (b) and 14 (b), the digital codes 1, 2, 3, 4, 5, 6
And at time 7, current cells 4, 3, 5, 2, respectively
When the digital code 6, 1, and 7 are turned on, the current cell 4 is turned on at the time of the digital code 1, so that the sum of the output current characteristics becomes ± 0. The sum of the output current characteristics at 5, 6, and 7 is +1, ± 0, +2, ± 0, +3, and ±, respectively.
It becomes 0.

As described above, when the current cells 1 to 7 are alternately turned on from the center to both ends, the sum of the output current characteristics is ± 0 at the digital codes 1, 3, 5, and 7.
However, it can be seen that the digital codes 2, 4 and 6 are biased to the plus side. Although not shown, when the current cells 1 to 7 are alternately turned on from the end to the center, the sum of the output current characteristics becomes ± 0 when the digital codes are 2, 4, 6, and 7. Are shifted to the plus side or the minus side at the time of the digital codes 1, 3 and 5.

Next, as shown in FIGS. 13 (c) and 14 (c), the digital codes 1, 2, 3, 4, 5, 6
And at time 7, current cells 2, 6, 1, 5, respectively
When 4, 7, and 3 are turned on, the current cell 2 is turned on at the time of digital code 1, so that the sum of the output current characteristics becomes +2, and similarly, the digital codes 2, 3, 4, 5 , 6 and 7 are ± 0, +3, +2, +2, −1 and ±, respectively.
It becomes 0.

As described above, when the current cells 1 to 7 are turned on at random, the sum of the output current characteristics becomes ± 0 at the time of the digital codes 2 and 7; It turns out that it is biased to the minus side.

Therefore, when the output current characteristics of the current cells 1 to 7 vary, the output linearity of the output current characteristics of the current cell type DA converter depends on the order in which the current cells 1 to 7 are turned on. However, there is a problem that the accuracy is deteriorated.

Next, in order to solve this problem, a D / A converter disclosed in Japanese Unexamined Patent Publication No. Hei 4-262622 has been described with reference to FIGS. 9 and 10 (a) to 10 (d). The description will be made in comparison with the converter 30.

The D / A converter disclosed in this publication includes a current converter corresponding to the above-described current cell block 14 and switching means corresponding to the decoder 12. Here, the current converter is composed of a plurality of (i × n) control elements corresponding to the current cells 32. These control elements are divided into n blocks, where i is one block. I have. Also, these control elements are
Those having current values at positions vertically symmetrical with respect to the average current of the variation of the entire output current characteristic are selected for each block and connected in common to form i outputs. Also,
The switching means controls the connection between the i outputs and the output terminals according to the digital amount.

According to this D / A converter, the conventional n
Double control elements are provided and divided into n blocks, and a control element having a current value at a vertically symmetric position with respect to the average current of the variation of the entire output current characteristic is selected for each block,
By connecting these in common to obtain i outputs, i
Since the sum of the output current amounts of the outputs is equalized at each output, it is possible to eliminate the error of each output of the current conversion unit due to the variation of the current amount with respect to the position of the control element and improve the linearity. I have.

However, this D / A converter is
As compared with the case where a DA converter having the same resolution is configured by the conventional technology, the number of control elements is n times as large as that of the conventional case. Even if the size of each control element is reduced in order to form a control element n times as large as the conventional one, the layout area does not become the same, so that the layout area naturally increases. Further, when the number of control elements is n times, wiring between control elements becomes complicated. Therefore, not only the layout becomes difficult, but also the speed is reduced due to the wiring resistance and the parasitic capacitance, and the output current characteristic is changed.

Next, a DA converter having a plurality of channels and formed into a macro cell will be described. For example, the output current characteristics of the 3ch-DA converter used for image signal processing and the like have the above-described variation in the output current characteristics between the current cells in the DA converter of each channel, as well as the individual channels. The output current characteristics also have a skewed variation between the D / A converters.

For example, the 3ch-DA converter shown in FIG. 15 has a D-channel having the output current characteristic shown in FIG.
The A converter is arranged in the order of R, G, and B colors from the left side in the figure to form a macrocell. In the figure,
The variation of the output current characteristic between the D / A converters of the individual channels is displayed for each current cell. Similarly, the variation of the output current characteristics between the current cells of the D / A converter of the individual channel is indicated in parentheses for each current cell. It is displayed inside.

In this 3ch-DA converter, assuming that the output current characteristic of the G color D / A converter located at the center is ± 0, for example, the R / D
The color D / A converter has a positive output current characteristic with respect to the G color D / A converter. Conversely, the B color D / A converter arranged on the right side has a negative output current characteristic with respect to the G color D / A converter. It has a current characteristic, or has the opposite output current characteristic.

The total output current characteristics of the R, G, and B DA converters are +7, ± 0, and -7 at the full scale voltage, respectively, and the variation in the output current characteristics is maximized. As described above, in a DA converter that has a plurality of channels and is made into a macro cell, the output current characteristics also vary among the DA converters of the individual channels. However, there is a problem that the screen is displayed with a little reddish color.

[0039]

SUMMARY OF THE INVENTION An object of the present invention is to provide a single-channel or multi-channel system by controlling the order in which each current cell is turned on and off, in view of the problems of the prior art. In either case, the current cell type D that can eliminate the slope-like variation of the output current characteristic and improve its linearity
An A-converter is provided.

[0040]

[0041]

[0042]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
Further, the present invention is a multi-channel current cell type D / A converter arranged at an end of a semiconductor chip and outputting, for each channel, an analog signal having a resolution corresponding to the number of bits of an input digital signal. A decoder for decoding the digital signal and outputting a decoded signal for each channel, and a current cell having a required driving capacity and a required number of cells in a column for the plurality of channels according to the resolution of the analog signal of each channel. And a current cell block which is arranged symmetrically with respect to a current cell arranged at the center thereof, wherein each current cell of each channel is controlled by the decode signal of each channel. , The one of the current cells is one of the current cells arranged in the row. Centrally located, the remaining current cells being symmetrically arranged with respect to the centrally located current cell, and for each of the remaining channels, for each channel, with respect to the centrally located current cell. And two current cells having half the driving capability are symmetrically arranged as a pair, and the remaining current cells have the same driving capability as the current cell arranged at the center, and the current cells arranged at the center are arranged. Cells and a pair of current cells arranged in the center of each channel symmetrically with respect to each of the plurality of channels, for each channel of the plurality of channels, the center of the current cells arranged in the row. An arranged current cell or the pair of centrally arranged current cells are turned on when the digital signal is odd, and turned off when the digital signal is even; With the current cell arranged in the center and the pair of current cells arranged in the center as the centers, the symmetrical positions on both sides outside the centrally arranged current cell or the pair of current cells arranged in the center. A current cell type DA converter is provided, wherein the arranged current cell pairs are simultaneously turned on or off for each current cell pair arranged at the symmetric position according to the digital signal.

Here, the pair of current cells arranged at the center are preferably arranged at positions symmetrical with respect to the current cells arranged at the center for each channel, and are arranged at the center. Each of the pair of current cells is preferably a current cell having the same cell width and half the cell height as the current cell arranged in the center.

Each of the pair of current cells disposed at the center is formed by halving the size of these transistors without changing the number of transistors constituting the current cell disposed at the center. Preferably, each of the pair of centrally located current cells comprises a plurality of current cell pieces, and the plurality of current cell pieces are line-symmetric with respect to the centrally located current cell. It is preferable to be arranged at a suitable position.

Preferably, the pair of current cells disposed at the center are disposed at points symmetrical with respect to the center of the current cell disposed at the center for each channel. The current cell having the same cell height and twice the cell width as the current cell of the pair of current cells disposed at the center is the same as the current cell of the pair of current cells arranged at the symmetric position. It is preferred that

Further, each of the pair of current cells arranged at the center is composed of a plurality of current cell pieces, and these plurality of current cell pieces are pointed with respect to the center of the current cell arranged at the center. Preferably, the current cells are arranged at symmetric positions, and the current cell includes a constant current source for driving a predetermined current, and first and second output terminals for switching the predetermined current driven by the constant current source to an output terminal or ground. It is preferable that the control terminals of the first and second switch elements are exclusively controlled in accordance with the value of the digital signal.

Further, the current cell type DA converter preferably further comprises a latch for holding a signal inputted to a control terminal of the first and second switch elements. At least two adjusting current cells for adjusting the amount of current driven by the cells
It is preferable to have one.

The centrally located current cell and the pair of centrally located current cells of each channel are directly controlled by one bit of the digital signal of the corresponding channel as the decode signal, A current cell pair arranged at symmetrical positions on both outer sides of the centrally arranged current cell or the pair of centrally arranged current cells, by a decode signal output from the decoder,
Preferably, control is simultaneously performed for each current cell pair located at each symmetric position.

[0049]

[0050]

[0051]

The current cell type DA converter according to the present invention, as one functional block used in a relatively large semiconductor chip, is provided at an end (peripheral portion) of the semiconductor chip, more preferably at a corner of the semiconductor chip. Is to be placed. Therefore, when the current cell type DA converter of the present invention has a variation in the output current characteristic, the output current characteristic necessarily has a variation in the sloped output current characteristic. When the present invention is applied to a multi-channel D / A converter, each current cell of the D / A converter of each channel is
The current cells are arranged at symmetrical positions on both sides of the current cell arranged at the center.

In the current cell type DA converter according to the present invention, the current cell arranged at the center among the current cells arranged in a line is controlled to be turned on when the digital signal is an odd number. Is turned off at the time of. With the current cell located at the center as a center, the current cell pairs located at symmetrical positions on both sides of the current cell located at the center are controlled to be in an on state or an off state according to the value of the digital signal. Is done.

That is, since the current cell type DA converter of the present invention necessarily has an inclined output current characteristic variation, the output current of the current cell arranged at the center among the current cells arranged in a line If the characteristics are ± 0, the current cells arranged at symmetrical positions on both sides thereof have output current characteristics equal to the plus side and the minus side, respectively. For this reason, by simultaneously controlling the current cell pairs arranged at the symmetrical positions to the ON state or the OFF state, these current cell pairs cancel each other's output current characteristics, and always keep the output current characteristics ± 0. be able to.

Therefore, according to the current cell type D / A converter of the present invention, the current cell type D / A converter is arranged at the end of the semiconductor chip regardless of the case of a single-channel or multi-channel D / A converter. By controlling the ON state and the OFF state of each current cell so as to offset the slope-like variation of the output current characteristics, the output current characteristics can always be made ± 0,
The linearity of the output current characteristics can be improved, and the accuracy can be improved. In addition, even if a constant current transistor having a small L length is used, the circuit can be compensated for the same accuracy as that of the conventional method.

[0055]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a current cell type DA converter according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a block diagram of a current cell type DA converter according to an embodiment of the present invention. This current cell type DA
The converter 10 has a decoder 12 for decoding a digital signal and outputting a decoded signal, and a current cell block 14 in which current cells of a number corresponding to the resolution of the analog signal are arranged in a line. A digital signal of a predetermined number of bits is input to the decoder 12, and a decode signal output from the decoder 12 is a current cell block 1
4, an analog signal having a resolution corresponding to the number of bits of the digital signal is output from the current cell block 14.

Here, for example, when the n-bit digital signal is composed of upper na bits and lower nb bits, the decoder 12 outputs the upper (n) bits of the upper na bits.
a-1) upper bit decoder 12a which decodes bits and outputs (2 ^na-1 -1) upper decoded signals
Similarly, for example, the upper (nb−
1) a lower bit decoder 12b which decodes bits and outputs (2 ^nb-1 -1) lower decoded signals.

The current cell block 14 is, for example, 2
^In the middle of the (2 ^na -1) upper bit current cells 16a, or more precisely, the upper bit current cell blocks 14a arranged in a line, capable of driving ^nb LSB of current. The one upper bit current cell 16a to be arranged and the symmetrical positions on both sides thereof (2 ^{na -1)}
-1) an upper bit current cell block 14a having upper bit current cell pairs 16a, 16a;
The (2 ^nb -1) lower-bit current cells 16b capable of driving the current of the LSB are similarly arranged at the center of the lower-bit current cell blocks 14b arranged in a line. It is divided into one lower bit current cell 16b and a lower bit current cell block 14b having (2 ^nb-1 -1) lower bit current cell pairs 16b, 16b arranged symmetrically on both sides thereof. Have been.

Here, (2)^na-1-1) Top decoding of books
The signal is (2^na-1-1) current cell pairs 1 for upper bits
6a and 16a are controlled on a one-to-one basis.
(2 ^nb-1-1) lower decoding signals are (2)^nb-1−
1) One pair of current cells 16b, 16b for lower bits
1 is controlled. Also, the current cell for the upper bit
One of the blocks located at the center of the block 14a
The high-order bit current cell 16a is
In the upper na bits, not decoded by 2a
Directly controlled by the remaining lower one bit,
In the center of the bit current cell block 14b,
The one lower-order bit current cell 16b is connected to the lower bit.
Not decoded by the decoding decoder 12b,
directly controlled by the remaining lower 1 bit of the nb bits
It is.

For example, the current cell type DA converter 1
0 indicates that the 8-bit digital signal has a resolution of 256 LSB.
, The upper three bits of the upper four bits of the digital signal are input to the upper bit decoder 12a, and the upper three bits of the lower four bits are converted.
The bits are input to the lower bit decoder 12b, and the upper bit decoder 12a outputs seven higher decode signals, and similarly, the lower bit decoder 12b outputs seven lower decode signals.

The upper bit current cell block 14
“a” is arranged at the center of fifteen upper-bit current cells 16a capable of driving a current of 16 LSB, more precisely, in the upper-bit current cell block 14a arranged in a line. One upper-bit current cell 16a and seven upper-bit current cell pairs 16a, 16a arranged at symmetrical positions on both sides of the current cell 16a. Similarly, the lower-bit current cell block 14b includes 1LS
Fifteen lower bit current cells 16b capable of driving a current of B, more precisely one of the lower bit current cell blocks 14b arranged in a line, are disposed at the center of the current cell block 14b. It has a lower bit current cell 16b and seven lower bit current cell pairs 16b, 16b arranged at symmetrical positions on both sides thereof.

As described above, the decoder 12 is divided into upper bit and lower bit decoders 12a and 12b.
Further, by dividing the current cell block 14 into the upper bit and lower bit current cell blocks 14a and 14b, the circuit configuration of the decoder 12 can be reduced. For example, instead of a circuit for decoding an 8-bit digital signal and generating 255 (= 2 ⁸ -1) decoded signals, a 3-bit digital signal is decoded and 7 (= 2 ³ -1) lines are decoded. Since it is sufficient to prepare two circuits for generating the decode signal, it is possible to configure the decoder 12 with an extremely small circuit.

The current cell type DA converter 10 of the present invention
Is configured by connecting all the current cells 16a and 16b in parallel to the output signal line 28. It should be noted that the current cell type DA converter 10 of the present invention is provided as one relatively small functional block formed in a relatively large semiconductor chip. Peripheral part). Therefore, when the output current characteristic varies between the current cells 16 arranged in a line, the variation necessarily becomes an inclined variation. The configuration of the current cells 16a and 16b used in the present invention is not particularly limited.
The current cells shown in (a), (b), (c) and (d) and all other types of conventionally known current cells can be used. Here, the current cell 16
The following description will be continued assuming that the configuration of a and 16b is the same as the configuration of the current cell 32a shown in FIG.

Next, the current cell type D
The operation of the A converter 10 will be described.

When an n-bit digital signal is input to the current cell type DA converter 10, the upper na bits are input to the upper bit decoder 12a, where they are decoded and subjected to (2 ^na -1) upper decode signals. Is output to the upper bit current cell block 14a. Similarly, the lower nb bits are input to the lower bit decoder 12b, decoded, and (2 ^nb -1) lower decoded signals are output to the lower bit current cell block 14b.

In these upper and lower decoding signals, the same number of decoding signals as the values (digital codes) of the upper and lower bits of the digital signal are activated. For example, if a 4-bit digital signal whose digital code is 0100 (binary number) is input, 15 (=
2 ⁴ -1) decoded signals are output, and among the 15 decoded signals, 4 decoded signals are activated. That is, the four current cells 16 are turned on.

Here, the current cell 16 (see FIG. 10A) is in an active state, that is, a high level (for example, 5
When the decode signal V) is input, the PMOS 20 is completely turned off and the PMOS 22 is completely turned on. Further, since a constant voltage is applied to the gate terminal of the PMOS 18, the constant current I of the PMOS 18 is equivalent to 16 LSB in the case of the upper bit current cell 16a or 1 LSB in the case of the lower bit current cell 16b. Is PMO
It flows to the output signal line 28 side through S22.

On the other hand, the inactive state of the current cell 16
That is, when a low-level (for example, 0 V) decode signal is input, the PMOS 20 is completely turned on and the PMOS 20 is turned on.
22 is completely turned off. Therefore, the PMOS 18
Flows through the PMOS 20 to the ground side.

As described above, in the current cell block 14, only the current cells 16 (16a, 16b) corresponding to the decode signal in the active state are turned on, and the total output from all the current cells 16 turned on is set. The current is output to the output signal line 28. Although not shown, this current is converted to a predetermined voltage level by a terminating resistor and output as an analog signal having a voltage level corresponding to the input digital code.

Next, the control method of the current cell 16 which is a characteristic part of the current cell type DA converter 10 of the present invention will be described by taking as an example a case where a 3-bit digital signal is converted into an analog signal having a resolution of 8 LSB. . That is,
As shown in FIG. 12, seven current cells 1, 2, 3, 4,
5, 6 and 7 are arranged in a line, and the output current characteristic of the current cell 4 arranged at the center among them is ± 0, and there is an inclined variation between these current cells 1 to 7. It will be described as if it were.

FIG. 2 shows a current cell type DA according to the present invention.
FIG. 4 is an output current characteristic diagram of one embodiment of the converter. In addition,
In this output current characteristic diagram, the current cells in the ON state are marked with a circle. Digital code 0
At this time, all the current cells 1 to 7 are in the off state, and the sum of the output current characteristics is naturally ± 0.

As shown in the output current characteristic diagram, at the time of the digital code 1, the current cell 4 is turned on, that is, only the current cell 4 whose output current characteristic is ± 0 is turned on. The sum of the output current characteristics is ± 0.

In the case of the digital code 2, the current cell 4 is turned off and the current cells 3 and 5 are simultaneously turned on, that is, the output current characteristic is +1.
And the current cell 5 having the output current characteristic of -1 are simultaneously turned on, and similarly, the sum of the output current characteristics becomes ± 0.

Similarly, in the case of the digital code 3,
Because the current cells 4 are further turned on while the current cells 3 and 5 remain on, that is, the current cells 4, 3 and 5 whose output current characteristics are ± 0, +1, and −1 are on. Therefore, the sum of the output current characteristics is ± 0.

Next, at the time of the digital code 4, the current cell 4 is turned off, the current cells 3 and 5 are kept on, and the current cells 2 and 6 are simultaneously turned on. , Output current characteristics are +
Since the current cells 3, 5, 2, and 6 of 1, -1, +2, and -2 are in the ON state, the total of the output current characteristics is ± 0.

Next, at the time of the digital code 5, the current cells 3, 5, 2 and 6 are kept on and the current cell 4 is further on, that is, the output current characteristics are ± 0, +1, -1, +2, -2 current cells 4,
Since 3, 5, 2, and 6 are in the ON state, the sum of the output current characteristics is ± 0.

Next, in the case of the digital code 6, the current cell 4 is turned off, the current cells 3, 5, 2 and 6 are kept on, and the current cells 1 and 7 are further turned off.
Are simultaneously turned on, that is, since the current cells 3, 5, 2, 6, 1 and 7 whose output current characteristics are +1, -1, +2, -2, +3 and -3, respectively, are on, The sum of the output current characteristics is ± 0.

Finally, at the time of the digital code 7, while the current cells 3, 5, 2, 6, 1 and 7 remain in the ON state,
Further, the current cell 4 is turned on, that is, the output current characteristics are ± 0, +1, −1, +2, −2, +3, respectively.
And -3 current cells 4, 3, 5, 2, 6, 1 and 7
Are in the ON state, the sum of the output current characteristics is ± 0.

As described above, in the current cell type DA converter 10 of the present invention, when the digital code is an odd number, the current cell 4 disposed at the center of the current cell block 14 is turned on, and the digital code is an even number. At times, the current cell 4 arranged at the center of the current cell block 14 is turned off. One set of current cell pairs 3 and 5, current cell pairs 2 and 6, and current cell pairs 1 and 7 having the same output current characteristics on the plus side and the minus side
Are simultaneously turned on or off according to the value of the digital code. Thus, in the current cell type DA converter 10 of the present invention, the variation in output current characteristics can always be completely eliminated irrespective of the digital code, so that the linearity thereof can be improved. In addition, even if a constant current transistor having a small L length is used, the circuit can be compensated for the same accuracy as that of the conventional method.

When the current cell block 14 is divided into upper bit and lower bit current cell blocks 14a and 14b as in the current cell type DA converter 10 shown in FIG. The control method of the current cell 16 used in the DA converter 10 is such that the current output from one upper-bit current cell 16a is large, that is, the output current characteristics vary widely,
It is particularly effective to apply it to the upper bit current cell block 14a. Needless to say, it is most preferable to apply to both the upper bit and lower bit current cell blocks 14a and 14b.

In the current cell type DA converter 10 of the present invention, the current cells 1 to 7 described above
The on / off state of the current cell 16 arranged at the center of the current cell block 14 can be controlled directly by a 1-bit signal in the digital signal. it can. Also,
One set of current cell pairs having the same output current characteristics on the plus side and the minus side can be simultaneously turned on and off, that is, these current cell pairs are controlled by one decode signal. Because you can
The decoding signal controlling these can be halved,
This has the advantage that the structure of the decoder 12 can be further simplified.

FIG. 3 shows a current cell type DA of the present invention.
1 shows an overall conceptual diagram of an embodiment of a converter. The illustrated current cell type DA converter 50 converts an 8-bit digital signal into a 256 LSB analog signal. The DA converter 50 includes flip-flops FFL7 to FFL0, FFS7 to FFS0, and timing adjustment delay circuits BFL7 to BFL0 in addition to the upper and lower bit decoders 52 and 54, the upper and lower bit current cell blocks 56 and 58. , BFS7-BFS
0, a constant potential generating circuit 60 and the like.

The current cell L0 in the figure is a higher-order bit current cell (CS × 16) for driving a current of 16 LSB.
The current cells L7 to L1 are an upper bit current cell pair (CS × 32) that drives a 32 LSB current by combining two upper bit current cells that drive a 16 LSB current. The current cell L0 is directly controlled by the digital signal D4, and each of the current cell pairs L7 to L1 is controlled by a common decode signal. Further, the current cell S7
The same applies to 〜S0.

The current cell L0 and the current cell S0
Are directly controlled by digital signals D4 and D0, respectively, but the present invention is not limited to this. For example, digital signals D4 and D0
And 54, which are output directly from the decoders 52 and 54 as decode signals, and may be configured to be directly controlled by these decode signals (ie, the digital signals D4 and D0).

The timing adjustment delay circuit BFL7
BFL0, BFS7 to BFS0 adjust the delay time of the output of the flip-flops FFL7 to FFL0, FFS7 to FFS0, and are composed of, for example, a plurality of serially connected buffers.

The constant potential generating circuit 60 has an output terminal IOUT
Is used together with a resistance element 64 externally connected to the output terminal to adjust an output voltage at an output terminal IOUT,
In the illustrated example, it is configured by a PMOS 62 and a resistance element 64. The source terminal of the PMOS 62 is connected to the power supply, the gate terminal and the drain terminal thereof are short-circuited, and the gate of the PMOS 18 (see FIG. 10A) serving as a constant current source in each of the current cells L7 to L0 and S7 to S0. Connected to the end. One terminal of the resistance element 64 is connected to the drain end of the PMOS 62, and the other terminal is connected to the ground.

As shown in FIG. 4, instead of constant potential generating circuit 60, adjusting current cell F, which is an adjusting current cell for determining a current value for one current cell, is used.
S can also be used. Resistance element 6 as an external circuit
6, the amount of current output from the adjustment current cell FS is determined. At this time, a value obtained by dividing the amount of current output from the adjustment current cell FS by the number is the amount of current per current cell. Thus, the amount of current of the current cell is determined. It is preferable to use at least two or more adjustment current cells FS in consideration of the symmetry of the arrangement.

In this DA converter 50, of the digital signals D7 to D0, the digital signals D7 to D5 are input to the upper bit decoder 52, and similarly, the digital signals D3 to D1 are input to the lower bit decoder 54. .

The upper decode signal and digital signal D4 output from upper bit decoder 52 are latched by flip-flops FFL7 to FFL0, respectively.
It is input to the upper-order bit current cell block 56 via the timing adjustment delay circuits BFL7 to BFL0. Similarly, the lower decode signal and the digital signal D0 output from the lower bit decoder 54 are latched by flip-flops FFS7 to FFS0, respectively, and input to the lower bit current cell block 58 via the timing adjustment delay circuits BFS7 to BFS0. Is done.

FIG. 5 shows an example of the arrangement of the current cells for the upper and lower bits. As shown in the figure, in the upper bit current cells L7 to L0, the current cell L0 is arranged at the center position, and current cell pairs L1 to L7 are arranged at symmetrical positions on both sides thereof. Further, the lower bit current cells S7 to S0 are arranged vertically at the center of the upper bit current cell in the horizontal direction in the drawing. The current cell S0 is arranged at the center position, and current cell pairs S1 to S7 are arranged at symmetrical positions on both sides thereof.

As described above, the lower bit current cells S7 to
By arranging S0 at the center position of the upper bit current cells L7 to L0, there is an advantage that the shift when carrying (carrying) from the lower bit can be reduced.

Here, a calculation example of the full-scale voltage (output maximum voltage) will be described. For example, if the amount of current flowing through the resistance element 64 of the constant potential generation circuit 60 is IA and the resistance value of the resistance element 68 externally connected to the output terminal IOUT is RΩ, the full scale current at the output terminal IOUT is I × 255 [A ]. Due to the resistance RΩ of the output terminal IOUT, the full scale voltage becomes 255 × IR [V].

By the way, the current cell 16 arranged at the center of the current cell block 14 is turned off,
When one pair of current cells having the same output current characteristics on the plus side and the minus side are simultaneously turned on, glitches may occur on the output signal line 28.
However, the current cell type DA converter 1 shown in FIG.
In the case of 0, the carry-over of the lower bit current cell block 14b causes the upper bit current cell block 14a
Is turned on. For example, latching the output signal of the decoder, that is, inserting a latch before the decode signal line 24 or inserting a delay circuit for timing adjustment causes glitch generation. Can be completely prevented.

The current cell type DA converter 10 of the present invention
Is basically configured as described above, but is not limited to only the above-described embodiment, and can be appropriately changed. For example, as shown in FIG. 1, the current cell block 14 can be applied to a case where the current cell block 14 is divided into upper bits and lower bits, or as shown in FIG. As the circuit configuration of the current cell 16, any conventionally known circuit configuration can be used.
Current cells 32 shown in (a), (b), (c) and (d)
When using a, 32b, 32c or 32d, P
It is preferable that the fixed voltage applied to the gate terminal of the MOS 18 or the NMOS 19 is appropriately selected.

In FIG. 2, the digital code 2
At the same time, the current cell pairs 3 and 5 are simultaneously turned on,
At the time of the digital code 4, the current cell pairs 2 and 6 are simultaneously turned on.
Further, the current cell pairs 1 and 7 are simultaneously turned on, but the order in which these current cell pairs are turned on is not limited. For example, at the time of the digital codes 2, 4, and 6, the current cell pairs 2 and 6, the current cell pairs 1 and 7, and the current cell pairs 3 and 5 can be simultaneously turned on.

Next, for a DA converter having a plurality of channels and formed into a macrocell, to which the current cell type DA converter of the present invention is applied, a 3-bit digital signal is similarly converted into an 8LSB analog signal. For example, a 3ch-DA converter used for image signal processing and the like will be described as an example.

FIG. 6 is a conceptual diagram of one embodiment showing the arrangement of a 3ch-DA converter to which the present invention is applied and its output current characteristics. In the figure, D of each channel
The variation of the output current characteristic between the A converters is displayed for each current cell, and similarly, the variation of the output current characteristic between the current cells in the individual channel DA converter is displayed in parentheses for each current cell. It is.

The 3ch-DA converter shown in FIG.
Current cells R1 to R of the color, G and B color DA converters
7, a layout structure in which current cells G1 to G7 and current cells B1 to B7 are mixed and arranged in a line.
A current cell B4 is disposed at the center position, and current cells G4a and G4b are disposed at symmetrical positions on both sides of the current cell B4.
Current cells R4a and R4b are arranged at symmetrical positions on both sides of 4a and G4b, respectively.

The current cells G4a and G4b are halved in size, for example, by reducing the size of the transistors constituting the current cell G4 before division into two. It is divided into two blocks, and has a driving capability of 1/2 of the current cell G4. The current cells G4a and G4b are simultaneously turned on or off by the same decode signal. When the current cells G4a and G4b are turned on, the current cells G4 before being divided by totaling both are turned on.
4 can flow the same current. The same applies to the current cells R4a and R4b.

Similarly, the current cell B4 is located symmetrically on both sides of the current cell R4a and R4b with respect to the current cell B4.
5 and B3, respectively, and similarly in the current cell B
4, the current cells G5, G3, current cells R5, R3, current cells B6, B
2, current cells G6, G2, current cells R6, R2, current cells B7, B1, current cells G7, G1, and current cell R
7, R1 are arranged.

That is, in a DA converter having a plurality of channels to which the present invention is applied, a DA converter of a plurality of channels is used.
Among the converters, the current cell at the center of the D / A converter of any one channel (as shown in FIG. 15, when the current cells are arranged in a line for each D / A converter of each channel, they are arranged at the center position thereof Current cell) at the center position. On the other hand, the current cell at the center of the DA converter of the remaining channel is divided into two current cell pairs, respectively, and symmetrical positions on both sides of the current cell arranged at the center position
In the case of this embodiment, more precisely, they are sequentially arranged at line-symmetrical positions around the current cell B4. Further, a pair of current cells are sequentially arranged around the center current cell of the D / A converter of each channel at symmetrical positions on both sides thereof.

Therefore, in the illustrated 3ch-DA converter, all the current cell pairs of the individual DA converters are arranged symmetrically with respect to the current cell B4 arranged at the central position. As shown, by controlling the individual DA converters,
The sum of the output current characteristics of the converters can always be ± 0, and the variation in the output current characteristics of each D / A converter can be completely eliminated regardless of the number of channels of the D / A converter and the digital code. Variations in output current characteristics between channels can be eliminated.

In the illustrated example, the current cell pairs are sequentially arranged in the order of B color, G color, and R color by taking a 3ch-DA converter as an example, but the present invention is not limited to this. is not.

For example, in the above-described embodiment, the B color D
The current cell B4 of the A converter is arranged at the center position.
The current cell R4 of the 4 or R color DA converter may be arranged at the center position. In the illustrated example, R,
The current cells of G and B colors are arranged symmetrically with respect to the current cells arranged one by one adjacently and sequentially and at the center. However, the present invention is not limited to this, and the symmetry is maintained. If so, current cells of the same color may be arranged adjacent to each other.

Further, the present invention is not limited to the 3ch-DA converter, but is applicable to any type of DA converter having a plurality of channels. Here, as one embodiment, FIG. 7 shows a conceptual diagram of an arrangement of each current cell of a DA converter of each channel when the present invention is applied to a 4ch-DA converter.

The 4ch-DA converter shown in FIG.
, The current cells X1 to X7 of the X DA converter serving as the fourth channel.
And the current cell pair R4a, R4b; R5, R3; R
6, R2; R7, R1 at the symmetrical positions on both sides, respectively, current cell pair X4a, X4b; X5, X3; X6, X2; X
7, X1 are sequentially arranged. The current cell X
4 is similarly divided into two current cells X4a and X4b.

Further, a pair of current cells arranged at a line symmetric position with respect to the current cell arranged at the center may be constituted by a plurality of current cell pieces having further smaller driving ability. Thus, the DA converter of the present invention is not limited to the number of channels of the DA
Applicable to A converter.

In the above embodiment, among the current cells at the center of the D / A converter of each channel, the current cells G4 and R4 other than the current cell B4 arranged at the center position when arranged according to the present invention. Each of the current cell pairs G4a and G4b is divided into two.
The current cell pair R4a and R4b are arranged at symmetrical positions on both sides of the current cell B4 arranged at the center, but the present invention is not limited to this.

For example, FIG. 8 shows a conceptual diagram of another embodiment of the arrangement of each current cell of the DA converter of each channel when the present invention is applied to a 3ch-DA converter.
The 3ch-DA converter of the illustrated example is a 3ch-DA converter shown in FIG.
As compared with the ch-DA converter, the current cells G4a, G4
4b and the height of the current cells other than the current cells R4a and R4b in the vertical direction in the figure are reduced to 1/2 times, and the width in the horizontal direction in the figure is doubled, for example, R3 is divided into R3a and R3b. The current cells G4a, G4b and the current cells R4a, R4b are respectively arranged at point symmetric positions with the center position of the current cells B4a and B4b as a center point CP. , B
4a, R4a, B5a, G5a, R5a,..., And current cells..., R3b, G3b, B3b, R4b, B
4b, G4b, B5b, G5b, R5b,... Can be considered as two rows.

Note that the DA converter shown in FIG.
From another viewpoint, the width is not changed, that is, the shapes of the current cells other than the current cells G4a and G4b and the current cells R4a and R4b are not changed at all (that is, D is not changed).
The external shape of the A converter remains unchanged), and the current cells G4a and G4b
It can also be considered that the width of the current cells R4a and R4b is reduced by half (that is, the height is doubled), and only the arrangement is changed.

In this DA converter, the current cells G4a and G4b are arranged at point symmetric positions with respect to the center point CP, so that their output currents are not limited to any of the horizontal and vertical directions in the figure. Variations in characteristics can be completely eliminated, and the accuracy can be improved. Further, as shown in this example, the DA of the present invention
In the converter, the width can be increased and the height can be reduced, that is, the outer shape of the DA converter can be appropriately changed.

In the illustrated example, the cells are apparently arranged in two rows. However, the present invention is not limited to this. If a pair of current cells of the same color arranged in the center are arranged point-symmetrically, It may be apparently arranged in a plurality of rows.
Further, the current cells arranged symmetrically in the center at the center may be divided into pieces of current cells having smaller current driving capability, provided that they are arranged in both rows adjacent to the current cell arranged in the center.

[0113]

As described in detail above, the current cell type DA converter according to the present invention can be used as a part of a semiconductor chip.
The semiconductor chip is arranged at an end of the semiconductor chip, and as a result, the semiconductor chip has an inclined output current characteristic variation. In the current cell type DA converter according to the present invention, when the digital signal is an odd number, the current cell arranged at the center among the current cells arranged in a row is turned on, and conversely, when the digital signal is an even number, the off state is turned off. At the same time, in response to the digital signal, the current cell pair disposed at symmetrical positions on both sides of the current cell disposed at the center is simultaneously turned on or off according to the digital signal.

The current cell type DA converter of the present invention is also applicable to a DA converter having a plurality of channels. At this time, each current cell of each DA converter is a current cell arranged at a central position. Are arranged at symmetrical positions on both sides thereof.

Therefore, according to the current cell type DA converter of the present invention, the output current characteristic of the current cell arranged at the center is ± 0, regardless of whether it is a single channel or a multi-channel, and Since the output current characteristics of the current cell pairs arranged at the same time are canceled by turning them on at the same time, not only the output current characteristics within the channels but also the dispersion of the output current characteristics between the individual channels is eliminated. Therefore, it is possible to completely eliminate the inclination-like variation of the entire output current characteristic and always keep ± 0. Therefore, according to the current cell type DA converter of the present invention, the linearity of the output current characteristic is improved, and the accuracy can be improved. Further, the current cell type DA of the present invention
According to the converter, for the same accuracy of the conventional method,
Even if a constant current transistor having a small L length is used, it is possible to compensate for the circuit, and there is an effect of preventing a decrease in yield due to process variation.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a current cell type DA converter of the present invention.

FIG. 2 is an output current characteristic diagram of one embodiment of the current cell type DA converter of the present invention.

FIG. 3 is an overall conceptual diagram of one embodiment of a current cell type DA converter of the present invention.

FIG. 4 is an overall conceptual diagram of another embodiment of the current cell type DA converter of the present invention.

FIG. 5 is a conceptual diagram of one embodiment showing an arrangement of each current cell in the current cell type DA converter shown in FIG. 3;

FIG. 6 is a conceptual diagram of an embodiment showing an arrangement of a current cell type DA converter of the present invention and output current characteristics thereof.

FIG. 7 is a conceptual diagram of another embodiment showing an arrangement of the current cell type DA converter of the present invention.

FIG. 8 is a conceptual diagram of another embodiment showing an arrangement of a current cell type DA converter of the present invention.

FIG. 9 is a block diagram of an example of a conventional current cell type DA converter.

FIGS. 10 (a), (b), (c) and (d) are circuit diagrams each showing an example of a conventional current cell.

FIG. 11 is a conceptual diagram of an example of a semiconductor chip on which an analog section and a digital section are mixedly mounted.

FIG. 12 is a schematic diagram of an example of a current cell type DA converter having an inclined output current characteristic variation.

FIGS. 13 (a), (b) and (c) are schematic views showing the order in which the current cells are sequentially turned on from one end to the other end, and the current cells are alternately arranged from the center to both ends; 3A and 3B are a schematic diagram showing an order in which the current cells are turned on and a schematic diagram showing the order in which the current cells are turned on at random.

FIGS. 14 (a), (b) and (c) are output current characteristic diagrams when the current cells are turned on in the order shown in FIGS. 13 (a), (b) and (c), respectively. .

FIG. 15 is a conceptual diagram showing an example of an arrangement of a 3ch-DA converter and output current characteristics thereof.

[Explanation of symbols]

10, 30, 50 Current cell type DA converter 12 Decoder 12a, 52 Upper bit decoder 12b, 54 Lower bit decoder 14 Current cell block 14a, 56 Upper bit current cell block 14b, 58 Lower bit current cell block 1, 2, 3, 4, 5, 6, 7, 16 (16a, 16
b), 32 (32a, 32b, 32c, 32d) Current cell 16a, L7 to L0 Upper bit current cell 16b, S7 to L0 Lower bit current cell 18, 20, 22, 62 P-type MOS transistor (P
MOS) 19,21,23 N-type MOS transistor (NMO
S) 24 decode signal line 26 inverted decode signal line 28 output signal line 40 semiconductor chip 42 analog unit 44 digital unit 46 output pad 60 constant potential generation circuit 64, 66, 68 resistance element 70 noise FFL7 to FFL0, FFS7 to FFS0 flip-flop BFL7-BFL0, BFS7-BFS0 Timing adjustment delay circuit FS adjustment current cell

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-253719 (JP, A) JP-A-4-162830 (JP, A) JP-A-2-306723 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (4)

(57) [Claims] 1. A multi-channel current cell type DA converter arranged at an end of a semiconductor chip and outputting an analog signal having a resolution corresponding to the number of bits of an input digital signal for each channel. A decoder for decoding the digital signal and outputting a decoded signal for each channel; and a current cell having a required driving capacity and the required number of cells arranged in a row for the plurality of channels according to the resolution of the analog signal of each channel. And a current cell block which is arranged symmetrically with respect to a current cell arranged at the center thereof, and wherein each current cell of each channel is controlled by the decode signal of each channel, and For one channel, the one current cell is one of the current cells arranged in the row. A centrally disposed, the remaining current cell is disposed symmetrically with respect to the centrally disposed current cell; for each of the remaining channels, for each channel, the And two current cells having half the driving capability are symmetrically arranged as a pair, and the remaining current cells have the same driving capability as the current cell arranged at the center, and the current cells arranged at the center are arranged. A cell and a pair of current cells located in the center of each channel, symmetrically disposed with respect to each of the plurality of all channels,
Among the current cells arranged in the column, the centrally arranged current cell or the pair of centrally arranged current cells is turned on when the digital signal is an odd number, and the digital signal is an even number. With the current cell disposed at the center and the pair of current cells disposed at the center as a center, the current cell disposed at the center or the pair of current cells disposed at the center is turned off. A current cell pair arranged at symmetrical positions on both outer sides is simultaneously turned on or off for each current cell pair arranged at the symmetrical position according to the digital signal. Type DA converter. 2. A pair of centrally located current cells,
For each channel, the current cell type DA converter according to claim 1 which is arranged in line symmetrical positions with respect to arranged current cells to said central. 3. A pair of current cells disposed at the center,
For each channel, the current cell type DA converter according to claim 1 arranged in point symmetry with respect to the center of the deployed current cells in the central. 4. The current cell disposed in the center and the pair of current cells disposed in the center of each channel are directly controlled by one bit of the digital signal of a corresponding channel as the decode signal, The current cell arranged at the center or the current cell pair arranged at symmetrical positions on both outer sides of the pair of current cells arranged at the center are arranged at respective symmetrical positions by a decode signal output from the decoder. 4. The current cell type DA converter according to claim 1 , wherein the current cell type DA converter is controlled simultaneously for each of the current cell pairs.