JP3181873B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, mainly a dynamic random access memory (hereinafter referred to as "D").
RAM).

[0002]

2. Description of the Related Art FIG. 5A is a diagram showing the configuration of a main part of a conventional DRAM. In the figure, 1 is a storage element (memory cell) for storing information, 2 and 2 'are bit lines for transferring signal charges read from the storage element 1, 3 is a word line for selecting a specific storage element 1, and 4 is A row decoder circuit for driving a specific word line 3, a sense amplifier (sense amplifier) 6 for amplifying a small signal transmitted through the bit lines 2, 2 ', and a reference numeral 5 for selecting a designated sense amplifier 6 A column decoder circuit 7 is an N-channel sense amplifier drive line for pulling out and driving the N-channel side of the sense amplifier 6, 8
Is a P-channel side sense amplifier drive line for driving the P-channel side of the sense amplifier 6 up, and 9 is an N-channel type sense amplifier drive line M for driving the N-channel side sense amplifier drive line 7.
The OS transistors 10 are P-channel type sense amplifier driving MOS transistors that drive the P-channel side sense amplifier drive line 8. 11 is a ground line, 12 is a power line, V _SS
Is a ground line potential, and V _DD is a power supply line potential. 13 and 1
Reference numeral 4 denotes a data line for outputting data from the sense amplifier 6. 16 is a main amplifier.

FIG. 5B shows a specific circuit diagram of the storage element 1. In FIG. 5B, 1A is a storage capacitor, and 1B is a MOS.
It is a transistor. FIG. 6 shows a C-MOS type sense amplifier which is a typical internal configuration of the sense amplifier 6. In FIG. 6, reference numerals 17 and 18 denote N-channel MOS transistors,
19 and 20 are P-channel type MOS transistors;
A and 15B are data output MOS transistors, respectively.

Next, referring to FIGS. 5 and 6, a conventional D
The operation of the RAM will be described. One word line 3 is selected by the row decoder circuit 4. Thus, data of the storage element 1 connected to the word line 3 is output to, for example, the bit line 2. As a result, a small potential difference is generated between the bit lines 2 and 2 ', and this is amplified by the sense amplifier 6. The amplified data is supplied to data lines 13 and 14 via data output transistors 15A and 15B in FIG.
, And further amplified by the main amplifier 16 and output outside the chip.

FIG. 7 shows operation waveforms at this time. This FIG.
, The period A is a precharge period, in which the bit lines 2, 2 'are all charged to a certain potential. The period B indicates a time when the word line 3 is driven and the signal charge stored in the storage element 1 is read out to the bit line 2 and a minute potential difference V is read out to the bit line 2. The period C is a period in which a minute potential difference is amplified by the sense amplifier 6 and rewritten in the storage element 1. The period D is a precharge period in which all the bit lines 2, 2 'are again charged to a certain potential in preparation for the next read cycle.

In FIG. 7, solid lines A ₁ and A ₂ represent potential waveforms of bit lines 2 and 2 ′, and the wiring resistance of N-channel sense amplifier drive line 7 and P-channel sense amplifier drive line 8 can be neglected. Is shown. However, in the actual case, their wiring resistances cannot be ignored, and the bit lines 2 and 2 forming a pair located far from the N-channel type sense amplifier driving MOS transistor 9 and the P-channel type sense amplifier driving MOS transistor 10. In the case of ′, the potential waveform is as shown by the dashed lines B ₁ and B ₂ . This is because, for example, the N-channel side sense amplifier drive line 7 is connected via the sense amplifier 6 to a number of bit lines 2,
The potential of bit line 2 or 2 'is lowered as a result of pulling out the potential of bit line 2'. However, since this N channel side sense amplifier drive line 7 is common to all bit lines 2 and 2 ', the N channel type The farther away from the sense amplifier driving MOS transistor 9, the lower the actual potential drop of the N-channel side sense amplifier drive line 7, and as a result, the sense amplification is delayed.

[0007] This delay in the sense amplification results in a decrease in the access tom of the entire semiconductor memory device. Less than,
This will be described. The signal amplified by the sense amplifier 6 is transferred to the main amplifier 16 through the data lines 13 and 14 (see FIG. 5). At this time, the characteristic that the main amplifier 16 does not amplify properly unless it has a certain potential difference or more. Therefore, the time at which data is output differs depending on the time gradient of the voltage generated on the data lines 13 and 14.

For example, as shown in FIG.
Is higher than V _H and the lower is V
Assuming that it amplifies correctly when it is less than _L ,
In the pair of bit lines 2 and 2 'near the N-channel type sense amplifier driving MOS transistor 9 and the P-channel type sense amplifier driving MOS transistor 10, the N-channel side sense amplifier drive line 7 and the P-channel side sense amplifier drive line 8
Since the influence of the wiring resistance is small and the state is close to the ideal state, it is close to the bit line potential change waveform of the solid lines A ₁ and A ₂ in FIG. 7, and the main amplifier 16 can operate correctly already at the time T ₁ . On the other hand, the pair of N-channel type sense amplifier driving MOS transistor 9 and P-channel furthest from the sense amplifier driving MOS transistor 10 bit lines 2 and 2 ', as previously described, one-dot chain line in FIG. 7 B _1, A potential change waveform as shown by B ₂ is obtained, and the main amplifier 16 cannot operate properly unless it reaches time T ₂ .

In the entire semiconductor memory device, the access time is specified by the worst value. Therefore, due to the wiring resistance of the N-channel sense amplifier drive line 7 and the P-channel sense amplifier drive line 8, the entire access time of the semiconductor memory device is reduced. The time gets longer. Conventional example, 64 Mbit equivalent DRAM
Simulation is performed using a circuit simulator (SPICE), assuming that the line width W _AL of the N-channel power supply line V _SN ( _VSS side) of the sense amplifier and the P-channel power supply line V _SP (V _DD side) the line width W _AL × 0.2 and the sense amplifier delay time) of the obtained relation between T _D. The result is shown by curve Z ₁ in FIG. At this time, the material of the N-channel side power supply line V _SN and the P-channel side power supply line V _SP is aluminum (Al), and the thickness thereof is 0.8 μm.

Referring to FIG. 8, the sense amplification delay time T _D is 8
ns or more, and when the line widths of the N-channel side power supply line V _SN and the P-channel side power supply line V _SP become thinner, it can be seen that the number increases rapidly. That is, in the conventional example, if the sensing amplification delay time T _D is originally long and the line width of the N-channel side power supply line V _SN and the P channel side power supply line V _SP is reduced in order to increase the integration degree, the sense amplification delay time is reduced. T _D becomes extremely long, and it is extremely difficult to achieve both high integration and high speed.

[0011]

In the configuration of the prior art as described above, the wiring resistance of the N-channel power supply line _VSN and the P-channel power supply line _VSP of the sense amplifier may cause a large value depending on the location of the sense amplifier. There is a problem that a sense amplification delay occurs and the access time of the entire semiconductor memory device becomes longer. The sense amplification delay time increases rapidly when the line widths of the N-channel power supply line V _SN and the P-channel power supply line V _SP of the sense amplifier are reduced for high integration. Was an obstacle.

Therefore, an object of the present invention is to shorten the sense amplification delay time caused by the wiring resistance of the power supply wiring for supplying power to the sense amplifier to shorten the access time,
An object of the present invention is to provide a semiconductor memory device that enables high integration.

[0013]

In the semiconductor memory device according to the present invention, a plurality of sense amplifier driving circuits for driving the sense amplifiers are dispersedly arranged for each sense amplifier row, and the plurality of sense amplifier driving circuits are arranged. The region where the means for accelerating the potential change of the word line in the storage element region is arranged is extended in the bit line direction and arranged in a region intersecting the sense amplifier row.

According to a second aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein a wiring group for supplying power to the plurality of sense amplifier driving circuits is formed in the same direction as the direction of the sense amplifier row. Power is supplied to the sense amplifier drive circuit from a position closest to the wiring group.

[0015]

According to the first aspect of the present invention, a plurality of sense amplifier driving circuits for driving the sense amplifiers are dispersedly arranged for each sense amplifier array. As a result, a layout that shortens the wiring distance between the sense amplifier and the sense amplifier driving circuit can be realized, and this layout can shorten the sense amplification delay time of the sense amplifier, thereby shortening the access time as a whole. it can. Also, since the area in the storage element area where the means for speeding up the potential change of the word line is arranged is extended in the bit line direction and arranged in the area intersecting the sense amplifier row, the cell array (storage element area ) Can be increased, and high integration can be achieved.

According to the configuration of the second aspect, in addition to having the same operation as the semiconductor memory device of the first aspect, the wiring distance between the first wiring group and the plurality of sense amplifier driving circuits is equalized. As a result, the variation of the sensing amplification delay can be reduced, and the access time determined by the longest sensing amplification delay can be shortened.

[0017]

【Example】

[First Embodiment] FIG. 1 (a) is a schematic view of a main part of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 1 (b) is surrounded by a solid line X in FIG. 1 (a). It is an enlarged view of an area.
1 (a) and 1 (b), reference numeral 44 denotes a word line lining area,
Reference numeral 101 denotes an arrangement region of a sense amplifier array, and 102 denotes an arrangement region of a storage element (memory cell) group. Reference numeral 103 denotes an intersecting region that intersects with the arrangement region 101 of the sense amplifier array when the word line lining region 44 extends in the bit line direction.
This is an arrangement area of the sense amplifier driving circuit. In the arrangement area 101 of the sense amplifier array, two adjacent intersection areas 10
Normally, about 64 sense amplifiers are arranged between the three. 1
1 is a ground line for supplying a ground line potential V _SS , and 12 is a power supply line for supplying a power supply line potential V _DD . Reference numerals 31 and 32 denote through-hole portions, respectively.
At 32, the power supply wiring group in the first direction (horizontal direction in the drawing) and the power supply wiring group in the second direction (vertical direction in the drawing) are electrically connected. The through-hole portion 31 connects the ground lines 11 in the first and second directions to each other to form a mesh, and the through-hole portion 32 connects the power supply lines 12 to each other in the first and second directions. To form a mesh.

The word line backing region 44 is used for backing a word line. A word line formed of polysilicon and an aluminum wiring running in parallel with the word line are mutually connected in this region. It is connected. By using the word line lining region 44, the effective resistance value of the word line is reduced, and the fall and rise of the potential of the word line (change in the potential of the word line) are accelerated.

The feature of this semiconductor memory device is that the power supply wiring (power supply line 12 and ground line 11) including the arrangement region 101 of the sense amplifier array and the word line lining region 44 on the arrangement region 102 of the storage element group are meshed. And a sense amplifier driving circuit for driving the sense amplifier is arranged in a distributed manner, and the arrangement position is extended in the bit line direction in the area where the means for speeding up the potential change of the word line in the memory element area is arranged. This is a layout that intersects with the sense amplifier row and supplies power to the sense amplifier drive circuit from the nearest point of the mesh-like power supply wiring, thereby shortening the wiring distance between the sense amplifier drive circuit and the sense amplifier. From this point, various effects that have not been obtained in the conventional DRAM occur.

Next, description will be made with emphasis on those effects. In FIG. 1, all wirings and circuits are not shown in FIG. 1 because the drawing becomes too complicated. Therefore, referring to FIG.
Sense amplifiers 6 constituting a sense amplifier array in placement area 101
Internal structure, their wiring and word line lining area 4
4 will be described below. First, the relationship between FIG. 1 and FIG. 2 will be described. In FIG. 2, reference numeral 6 denotes a sense amplifier. In FIG. 1, a large number of sense amplifiers 6 are arranged in a row in the vertical direction in the figure in a region 101, and a word line lining region 44 used for lining a word line is located between them. FIG.
FIG. 1 is a vertically enlarged view of one of the many sense amplifiers 6 in FIG. 1 and the word line lining area 44 used for lining.

In FIG. 2, 41 is a precharge control line, 42 is a sense amplifier column select line, and 43 is a sense amplifier activation line. 51 is a sense amplifier control line precharge circuit, 53 is a bit line precharge circuit, 54 is a CMOS flip-flop circuit for amplification, 55 is a data transfer circuit, 57 is a sense amplifier drive circuit for data output, and 58 is data rewrite. Of the sense amplifier driving circuit. 6
Reference numerals 1 and 62 denote N-channel type sense amplifier driving MOS transistors, 63 denotes an N-channel type sense amplifier driving MOS transistor, and 64 denotes a P-channel type sense amplifier driving MOS.
It is an S transistor.

Sense amplifier drive circuit 5 for data output
Numerals 7 are distributed and arranged in a row of the sense amplifiers 6 and are supplied with power from the nearest portions of the power supply line 12 and the ground line 11 connected in a mesh. The configuration and operation of this embodiment will be described by taking data reading from the storage element 1 as an example.

First, when reading out the signal charges stored in the storage element 1, the bit lines 2, 2 'are set to the precharge voltage V
_PR needs to be charged. Therefore, the shared switch gate control lines 21 and 22 are set to a high level, and the right storage element region and the left storage element region are connected to the central sense amplifier 6. Next, the precharge control line 41 is set to the high level, and the bit line precharge circuit 53 causes the bit lines 2 and 2 in the sense amplifier 6 and the storage element regions on the left and right sides of the sense amplifier 6.
2 'is charged to the precharge voltage _VPR . At the same time, the N-channel sense amplifier drive line 7 and the P-channel sense amplifier drive line 8 are similarly charged to the precharge voltage V _PR by the sense amplifier drive line precharge circuit 51 provided at the upper end of the column of the sense amplifiers 6. .

Next, the system on the side of the storage element area that is not read out is
A low switch control line, for example, 22 to a low level;
Only the left storage element area is connected to the sense amplifier 6
make. Next, one word is processed by the row decoder circuit 4.
The word line 3 is selected, and the potential of the word line 3 is at a high level.
Stand up. As a result, the signal charge of the storage element 1 becomes
Appears on bit line 2 'and is slightly between bit line 2 and bit line 2'.
A small potential difference occurs. This small potential difference sense amplifier
Amplify at 6. This causes the sense amplifier activation line 43 to go low.
Start by leveling. This allows you to use
Of the word line lining region 44 used and the sense amplifier 6
Sensing amplification for data output located in the area of intersection with the columns
MO for driving the N-channel type sense amplifier in the driver driving circuit 57
The S transistors 61 and 62 become conductive, and the N channel
The potential of the sense amplifier drive line 7 is set to the ground line potential V._SSApproaching
And the potential of the P channel side sense amplifier drive line 8 is
Rank V _DDIt works to get closer to. This allows
CMOS flip-flop for amplification in the sense amplifier 6
The trip circuit 54 operates to amplify a small potential difference.

Next, the sense amplifier column select line 42 goes high, the column select line 35 goes high, and the signal data in the sense amplifier 6 is transferred to the data lines 13 and 14 via the transfer circuit 55. Is output. This is further amplified and output outside the semiconductor memory device. On the other hand, a rewrite operation to the storage element 1 is performed in parallel with these data output operations. The sense amplifier driving circuit 58 for data rewriting arranged at the lower end of the column of the sense amplifier 6 contributes to this. When the sense amplifier activation line 43 is set to low level, the N-channel type sense amplifier drive MOS transistor 63 and the P-channel type sense amplifier drive MOS transistor 64 in the sense amplifier drive circuit 58 become conductive, and the N-channel side The potential of the sense amplifier drive line 7 is brought closer to the ground line potential V _SS , and the P-channel side sense amplifier drive line 8
At the power line potential V _DD .

As a result, the amplification operation of the sense amplifier 6 is completed, and rewriting to the storage element 1 is ensured. In particular, in the first embodiment, the N-channel type sense amplifier driving MOS transistor 62 is used as the P-channel side sense amplifier driving transistor in the sense amplifier driving circuit 57. Since the potential of the drive line 8 does not rise to the power supply line potential V _DD and rises only to a point where the power supply line potential V _DD drops by the threshold voltage of the MOS transistor 62 for driving the N-channel type sense amplifier, rewriting is completely completed. Can't do it. In the first embodiment, only the N-channel type driving transistor is used in the sense amplifier driving circuit 57 because the circuit in the sense amplifier driving circuit 58 is used when the P-channel type driving transistor is used. This is because two more inverting circuits are required as in the configuration, and if the inversion circuit is accommodated in the width of the word line lining region 44 used for lining, a stricter design tool is required and the yield is reduced. This is because an N-channel MOS transistor generally has a higher current driving capability than a P-channel MOS transistor and is suitable for space saving. As can be seen from the above description, the sense amplifier drive circuit 57 mainly outputs signals to the sense amplifier 6.
This is because it is provided to amplify to an extent necessary for outputting to the outside, and an N-type driving transistor is sufficient for this purpose. On the other hand, the sense amplifier drive circuit 58 arranged at the lower end of the column of the sense amplifiers 6 is mainly for rewriting signals to the storage element 1.

According to the above configuration, the following effects can be obtained. First, the sense amplifier delay caused by the wiring resistance of the sense amplifier drive lines 7 and 8 can be minimized. The reason is that the sense amplifier drive circuits 57 for data output can be dispersedly arranged on the sense amplifier drive lines 7 and 8, so that the sense amplifier drive lines 7, 8 from the sense amplifier 6 to the sense amplifier drive circuit 57 are provided. Can be reduced from 1/8 to 1/32 of the conventional distance, and
Wiring resistance can be reduced and sense amplification delay can be minimized. This is made possible only by forming the power supply line 12 and the ground line 11 in a mesh shape including the storage element region, the sense amplifier 6, and the word line lining region 44. That is, since the power supply line 12 and the ground line 11 in a mesh form are configured to supply power to a plurality of sense amplifier driving circuits 57 distributed and arranged,
Thus, a current sufficient for the operation can be supplied to the plurality of sense amplifier drive circuits 57.

Also in this embodiment, similarly to the conventional example,
Assuming a DRAM equivalent to 64 Mbits, a simulation is performed using a circuit simulator (SPICE), and the line width W _AL of the N-channel power line V _SN ( _VSS side) of the sense amplifier and the P-channel power line V the line width of the _SP (V _DD side) W _AL × 0.2 and the sense amplifier delay time of the obtained relation between T _D. The result is shown by curve Z ₂ in FIG. At this time, the material of the N-channel side power supply line V _SN and the P-channel side power supply line V _SP is aluminum (Al) as in the conventional example, and the thickness thereof is 0.8 μm.

Referring to FIG. 8, the sense amplification delay time T _D is approximately 4 ns, which can be shortened by 4 ns or more as compared with the conventional example. In addition, the N-channel power supply line V _SN and the P-channel power supply line V _SP It can be seen that there is almost no change even if the line width becomes narrow. That is, in the embodiment, on the shorter sense amplifier delay time T _D Unlike conventional e.g., N in order to increase the degree of integration
Be thinner line width of the channel side power supply line V _SN and P-channel side power supply line V _SP, not sense amplifier delay time T _D is longer, it become possible to achieve both high integration and high speed.

Second Embodiment A second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that the power line potential V _DD is provided between the power line 12 and the ground line 11 formed in a mesh shape, in addition to the stray capacitance formed naturally.
In order to stabilize the potential and the ground line potential V _SS , a stabilizing capacitor 71 is formed in the sense amplifier 6 and a stabilizing capacitor 72 is formed in the word line lining region 44 used for word line lining. is there. Other configurations are the same as those of the first embodiment.

According to such a configuration, there is an advantage that the potentials of the power supply line 12 and the ground line 11 formed in a mesh shape can be further stabilized. Conversely, if the degree of stability is the same, it is possible to make the thickness of each of the power supply line 12 and the ground line 11 in a mesh shape smaller, and to reduce the wiring area. Furthermore, the sum of the capacitances of the stabilizing capacitors 72 formed in this manner is extremely large in the entire chip, and as a result, the power supply line potential V _DD and the ground line potential V _{DD of the} peripheral circuits are reduced.
There is also an effect of stabilizing _SS , and the operation of the entire semiconductor memory device can be stabilized.

In the second embodiment, the stabilizing capacitors 71 and 72 are formed both in the sense amplifier 6 and in the word line lining region 44 used for lining.
It is effective to form only one of them. In the first embodiment and the second embodiment, the P-channel driving transistor of the sense amplifier driving MOS transistor of the data output sensing amplifier driving circuit 57 is the same as that shown in FIG.
And FIG. 3 shows a MOS for driving an N-channel type sense amplifier.
The transistor 62 is used. Of course, as shown in the sense amplifier driving circuit 57 of FIGS.
The effect does not change even if the S transistor 162 is used.

[0033]

According to the semiconductor memory device of the present invention, since a plurality of sense amplifier drive circuits for driving the sense amplifiers are dispersedly arranged for each sense amplifier row, the wiring distance between the sense amplifier and the sense amplifier drive circuit is provided. Can be shortened, and this layout can shorten the sense amplification delay time of the sense amplifier, thereby shortening the access time as a whole. Also, since the area in the storage element area where the means for speeding up the potential change of the word line is arranged is extended in the bit line direction and arranged in the area intersecting the sense amplifier row, the cell array (storage element area ) Can be increased, and high integration can be achieved.

According to the semiconductor memory device of the second aspect,
In addition to the same effects as the semiconductor memory device of the first aspect, the wiring distance between the wiring group and the plurality of sense amplifier driving circuits is equalized, so that the variation in the sense amplification delay can be reduced and the maximum. It is possible to shorten the access time determined by the longest sense amplification delay.

[Brief description of the drawings]

FIG. 1A is a configuration diagram of a main part of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 1B is an enlarged view of a region surrounded by a solid line X in FIG.

FIG. 2 is a more detailed configuration diagram of a sense amplifier and the like in a first embodiment.

FIG. 3 is a more detailed configuration diagram of a sense amplifier and the like in a second embodiment of the present invention.

FIGS. 4 (a) and 4 (b) are circuit diagrams showing another embodiment of the sense amplifier driving circuit of FIGS. 2 and 3. FIG.

FIG. 5 is a circuit diagram showing a main configuration of a conventional semiconductor memory device.

FIG. 6 is a circuit diagram showing a configuration of a conventional sense amplifier.

FIG. 7 is an operation waveform diagram of a conventional sense amplifier.

8 is a characteristic diagram showing the relationship between the examples and the line width of the power line and the sense amplifier delay time of the positive side of the sense amplifier in the conventional example (V _DD side) and negative (V _SS side).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Storage element 2, 2 'bit line 3 Word line 4 Row decoder circuit 5 Column decoder circuit 6 Sense amplifier 7 N channel side sense amplifier drive line 8 P channel side sense amplifier drive line 11 Ground line 12 Power supply line 31, 32 Through hole Unit 35 column selection line 41 precharge control line 42 sense amplifier column selection line 43 sense amplifier activation line 44 word line lining area 51 sense amplifier control line precharge circuit 53 bit line precharge circuit 54 CMOS flip-flop circuit for amplification 55 data Transfer circuit 57 Sense amplifier drive circuit 58 Sense amplifier drive circuit 61 N channel type sense amplifier drive MOS transistor 62 N channel type sense amplifier drive MOS transistor 63 N channel type sense amplifier drive MOS transistor 64 P channel type sense amplifier Arrangement region 103 intersection area of the arrangement region 102 storage elements of the driving MOS transistor 71 stabilizing capacitors 72 stabilizing capacitors 101 sense amplifier column

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-191397 (JP, A) JP-A-62-183140 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 G11C 11/401 H01L 21/8242

Claims (2)

(57) [Claims] 1. A plurality of sense amplifier driving circuits for driving a sense amplifier are separately arranged for each sense amplifier row, and the plurality of sense amplifier driving circuits speed up a change in potential of a word line in a storage element region. A semiconductor memory device wherein the region where the means is arranged is extended in the bit line direction and is arranged in a region intersecting the sense amplifier row. 2. A wiring group for supplying power to a plurality of sense amplifier driving circuits is formed in the same direction as the direction of the sense amplifier row, and power is supplied to the plurality of sense amplifier driving circuits from a position closest to the wiring group. 2. The semiconductor memory device according to claim 1, wherein: