JP3180404B2 - Method of forming capacitive element - Google Patents
Method of forming capacitive elementInfo
- Publication number
- JP3180404B2 JP3180404B2 JP00313592A JP313592A JP3180404B2 JP 3180404 B2 JP3180404 B2 JP 3180404B2 JP 00313592 A JP00313592 A JP 00313592A JP 313592 A JP313592 A JP 313592A JP 3180404 B2 JP3180404 B2 JP 3180404B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- electrode
- forming
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000003990 capacitor Substances 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 15
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置における容
量素子の形成方法に係り、とりわけ容量素子の絶縁膜を
形成する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor in a semiconductor device, and more particularly to a method for forming an insulating film of the capacitor.
【０００２】[0002]
【従来の技術】図３は、従来の方法により形成されたＤ
ＲＡＭ（Ｄynamic Ｒamdom ＡccessＭemory）の容量素
子であるスタックトキャパシタの断面図である。2. Description of the Prior Art FIG.
FIG. 2 is a cross-sectional view of a stacked capacitor that is a capacitive element of a RAM (Dynamic Ramdom Access Memory).
【０００３】図３に示した容量素子では、Ｐ型シリコン
基板１に、素子分離のためのフィールド酸化膜２が形成
され、Ｎ+拡散層３、ポリシリコンからなるワード線
４、アルミニウムからなるビット線５、ＳｉＯ2膜６、
層間絶縁膜７、ポリシリコンからなるキャパシタの下部
電極８、キャパシタの絶縁層として第１の酸化膜（Ｓｉ
Ｏ2）９およびＳｉ3Ｎ4膜１０、ポリシリコンからなる
キャパシタの上部電極１３がそれぞれ形成されている。In the capacitor shown in FIG. 3, a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1, an N + diffusion layer 3, a word line 4 made of polysilicon, and a bit made of aluminum. Line 5, SiO 2 film 6,
An interlayer insulating film 7, a lower electrode 8 of a capacitor made of polysilicon, and a first oxide film (Si
An upper electrode 13 of a capacitor made of O 2 ) 9, Si 3 N 4 film 10 and polysilicon is formed.
【０００４】図４は、図３における下部電極８／第１の
酸化膜（ＳｉＯ2）９、Ｓｉ3Ｎ4膜１０／上部電極１３
から構成されるＤＲＡＭのキャパシタのうち、下部電極
８／第１の酸化膜９、Ｓｉ3Ｎ4膜１０を形成する工程に
おける下部電極８、第１の酸化膜９、Ｓｉ3Ｎ4膜１０の
断面図である。FIG. 4 shows a lower electrode 8 / first oxide film (SiO 2 ) 9, an Si 3 N 4 film 10 / an upper electrode 13 in FIG.
Of the lower electrode 8, the first oxide film 9, and the Si 3 N 4 film 10 in the step of forming the lower electrode 8 / the first oxide film 9 and the Si 3 N 4 film 10 It is sectional drawing.
【０００５】図４（ａ）に示すポリシリコンで形成され
た下部電極８の表面上に形成された第１の酸化膜（Ｓｉ
Ｏ2）９は、いくら除去しようとフッ酸処理を施しても
洗浄の純水中あるいは乾燥中などにより成長してしまっ
た自然酸化膜である。A first oxide film (Si) formed on the surface of lower electrode 8 made of polysilicon shown in FIG.
O 2 ) 9 is a natural oxide film that has grown in pure water for cleaning or during drying, even if a hydrofluoric acid treatment is performed to remove it.
【０００６】図４（ｂ）に示すように、容量素子の容量
を増加させるためにＳｉＯ2よりも誘電率の高いＳｉ3Ｎ
4膜１０を第１の酸化膜（ＳｉＯ2）９の上面に減圧ＣＶ
Ｄ法により形成する。As shown in FIG. 4B, in order to increase the capacitance of the capacitive element, Si 3 N having a higher dielectric constant than SiO 2 is used.
4 A film 10 is formed on the upper surface of the first oxide film (SiO 2 ) 9
Formed by Method D.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上記方
法では減圧ＣＶＤ法によりＳｉ3Ｎ4膜１０を形成する工
程において、炉中へのローディング等時に酸素の巻き込
みがあり、図４（ｂ）に示すように、第１の酸化膜９が
図４（ａ）で示した厚さをより厚くさせ、１〜２ｎｍの
厚さにまで成長してしまう。これでは、Ｓｉ3Ｎ4をいく
ら薄膜化しようとしても、誘電率の低いＳｉＯ2の占め
る割合が大きくなり、容量の増大は図れない。However, in the above method, in the step of forming the Si 3 N 4 film 10 by the low pressure CVD method, oxygen is involved during loading into a furnace or the like, and as shown in FIG. As described above, the first oxide film 9 increases the thickness shown in FIG. 4A and grows to a thickness of 1 to 2 nm. In this case, no matter how much the thickness of Si 3 N 4 is reduced, the proportion of SiO 2 having a low dielectric constant increases, and the capacity cannot be increased.
【０００８】そこで、本発明は、キャパシタ絶縁膜の薄
膜化による容量増大においてネックとなる自然酸化膜等
の第１の酸化膜を除去し、その代わりに第１の酸化膜よ
りも誘電率が高く、しかも禁止帯幅の大きい酸化膜を形
成することにより容量の増大およびリーク電流の低下を
もたらすことにより、信頼性を向上させた容量素子の形
成方法を提供することを目的とする。Therefore, the present invention removes the first oxide film such as a natural oxide film which becomes a bottleneck in increasing the capacitance by reducing the thickness of the capacitor insulating film, and instead has a higher dielectric constant than the first oxide film. In addition, an object of the present invention is to provide a method for forming a capacitance element with improved reliability by forming an oxide film having a large forbidden band width to increase capacitance and reduce leakage current.
【０００９】[0009]
【課題を解決するための手段】上記課題は、片方の電極
／キャパシタ絶縁膜／他方の電極から構成される容量素
子の片方の電極表面上に誘電率の低い自然酸化膜から成
る第１の酸化膜が生じた半導体基板における容量素子の
形成方法であって、前記片方の電極を形成する材料膜よ
りも酸化物生成自由エネルギーの小さい材料膜を当該片
方の電極上の第１の酸化膜表面に形成する工程と、酸素
を供給しながら当該半導体基板を熱処理を行うことによ
り、誘電率の低い前記第１の酸化膜を改質して第１の酸
化膜よりも誘電率の高い第２の酸化膜を形成する工程
と、その後、前記第２の酸化膜表面に窒化シリコン膜を
形成する工程とを含むことを特徴とする容量素子の形成
方法によって解決される。An object of the present invention is to form a natural oxide film having a low dielectric constant on one electrode surface of a capacitor composed of one electrode / a capacitor insulating film / the other electrode.
The first method of forming a capacitive element in a semiconductor substrate having an oxide film occurs, the pieces small material film of oxide formation free energy than the material film for forming the one electrode that
Forming a first oxide film surface on the square of the electrode, the oxygen
Heat treatment is performed on the semiconductor substrate while supplying the first oxide film, thereby modifying the first oxide film having a low dielectric constant to form the first acid film.
Forming a second oxide film having a higher dielectric constant than the oxide film, and thereafter , forming a silicon nitride film on the surface of the second oxide film.
And a forming step .
【００１０】[0010]
【００１１】更に、上記課題は本発明によれば、片方の
電極を形成する材料膜を多結晶シリコンとし、片方の電
極を形成する材料膜よりも酸化物生成自由エネルギーの
小さい材料膜をアルミニウムとすることを特徴とする容
量素子の形成方法によって好適に解決される。Further, according to the present invention, according to the present invention, a material film forming one electrode is made of polycrystalline silicon, and a material film having a lower free energy of oxide generation than aluminum is used as a material film forming one electrode. It is preferably solved by a method for forming a capacitor, which is characterized in that
【００１２】[0012]
【作用】本発明によれば、図２（ａ）に示すように、容
量素子の片方の電極（下部電極）８の表面上に第１の酸
化膜９が形成された容量素子において、図２（ｂ）に示
すように、片方の電極８の材料膜よりも酸化物生成自由
エネルギーの小さい材料膜１１を、第１の酸化膜９の表
面上に形成した後に、図２（ｃ）に示すように熱処理を
行なうことにより、第１の酸化膜９と材料膜１１を反応
させて第２の酸化膜１２を形成する。材料膜１１の酸化
物生成自由エネルギーが片方の電極８の材料膜よりも小
さいので、片方の電極８の材料膜の酸化物である第１の
酸化膜９の酸素が材料膜１１と化合させて第２の酸化膜
１２を形成することができる。これにより、第１の酸化
膜を改質させて第１の酸化膜よりも誘電率の大きく、禁
止帯幅の広い第２の酸化膜１２を容量素子の絶縁膜とし
て形成することができ、容量の増大および信頼性を向上
させることができる。According to the present invention, as shown in FIG. 2A, in a capacitor in which a first oxide film 9 is formed on the surface of one electrode (lower electrode) 8 of the capacitor, FIG. As shown in FIG. 2B, after forming a material film 11 having a smaller free energy of oxide generation than the material film of one electrode 8 on the surface of the first oxide film 9, FIG. By performing the heat treatment as described above, the first oxide film 9 reacts with the material film 11 to form the second oxide film 12. Since the free energy of oxide formation of the material film 11 is smaller than that of the material film of the one electrode 8, oxygen of the first oxide film 9 which is an oxide of the material film of the one electrode 8 is combined with the material film 11. The second oxide film 12 can be formed. Thus, the first oxide film is modified to form the second oxide film 12 having a larger dielectric constant than the first oxide film and a wide band gap as an insulating film of the capacitor, and And the reliability can be improved.
【００１３】また、本発明によれば、酸素を供給しなが
ら熱処理を行なうことにより、材料膜１１が完全に酸化
され、第２の酸化膜１２のみにより片方の電極８の表面
を好適に被うことができる。Further, according to the present invention, by performing the heat treatment while supplying oxygen, the material film 11 is completely oxidized, and the surface of one electrode 8 is suitably covered only by the second oxide film 12. be able to.
【００１４】更に、本発明によれば、片方の電極８を形
成する材料膜を多結晶シリコンとし、片方の電極８を形
成する材料膜よりも酸化物生成自由エネルギーの小さい
材料膜１１をアルミニウムとすることにより、第１の酸
化膜であるＳｉＯ2よりも第２の酸化膜である酸化アル
ミニウム１２の方が誘電率が大きく、禁止帯幅の広い絶
縁膜を好適に形成することができる。Further, according to the present invention, the material film forming one electrode 8 is made of polycrystalline silicon, and the material film 11 having a smaller free energy of oxide generation than the material film forming one electrode 8 is made of aluminum. By doing so, an insulating film having a higher dielectric constant and a wider band gap can be suitably formed in the aluminum oxide 12 as the second oxide film than in the SiO 2 as the first oxide film.
【００１５】[0015]
【実施例】図１は、本発明による１つの実施例によって
形成されたＤＲＡＭのスタックトキャパシタの断面図で
ある。図１によれば、Ｐ型シリコン基板１に、フィール
ド酸化膜２、Ｎ+拡散層３、ポリシリコンからなるワー
ド線４、アルミニウムからなるビット線５、ＳｉＯ2膜
６、層間絶縁膜７、ポリシリコンからなるキャパシタの
下部電極８、キャパシタの絶縁層として第２の酸化膜
（酸化アルミニウム）１２およびＳｉ3Ｎ4膜１０、ポリ
シリコンからなるキャパシタの上部電極１３がそれぞれ
形成されている。FIG. 1 is a cross-sectional view of a stacked capacitor of a DRAM formed according to one embodiment of the present invention. According to FIG. 1, a field oxide film 2, an N + diffusion layer 3, a word line 4 made of polysilicon, a bit line 5 made of aluminum, an SiO 2 film 6, an interlayer insulating film 7, A lower electrode 8 of a capacitor made of silicon, a second oxide film (aluminum oxide) 12 and an Si 3 N 4 film 10 as an insulating layer of the capacitor, and an upper electrode 13 of a capacitor made of polysilicon are formed, respectively.
【００１６】以下、本発明による実施例を図面に基づい
て説明する。An embodiment according to the present invention will be described below with reference to the drawings.
【００１７】図２は、本発明による１つの実施例を示
し、図１における下部電極８／第２の酸化膜（酸化アル
ミニウム）１２、Ｓｉ3Ｎ4膜１０／上部電極１３から構
成されるＤＲＡＭのキャパシタにおいて、キャパシタの
絶縁膜である第２の酸化膜（酸化アルミニウム）１２お
よびＳｉ3Ｎ4膜１０を形成する工程における下部電極８
／第２の酸化膜（酸化アルミニウム）１２、Ｓｉ3Ｎ4膜
１０の断面図である。FIG. 2 shows an embodiment according to the present invention, and comprises a DRAM composed of a lower electrode 8 / second oxide film (aluminum oxide) 12, a Si 3 N 4 film 10 / an upper electrode 13 in FIG. The lower electrode 8 in the step of forming the second oxide film (aluminum oxide) 12 and the Si 3 N 4 film 10 which are the insulating films of the capacitor.
FIG. 2 is a sectional view of a second oxide film (aluminum oxide) 12 and a Si 3 N 4 film 10.
【００１８】図２（ａ）は、ポリシリコンで形成された
下部電極８の表面上に第１の酸化膜（ＳｉＯ2）９が形
成された状態を示している。この第１の酸化膜９は下部
電極８の表面洗浄処理後に生じた自然酸化膜である。図
２（ｂ）に示すように、シリコンよりも酸化生成自由エ
ネルギーの小さい物質であるアルミニウム金属１１をＣ
ＶＤ法により第１の酸化膜（ＳｉＯ2）９の表面上に１
〜２ｎｍの厚さに形成する。FIG. 2A shows a state in which a first oxide film (SiO 2 ) 9 is formed on the surface of a lower electrode 8 made of polysilicon. This first oxide film 9 is
This is a natural oxide film formed after the surface cleaning treatment of the electrode 8. As shown in FIG. 2 (b), aluminum metal 11, which is a substance having a lower free energy of oxidation generation than silicon, is replaced with C.
The first oxide film (SiO 2 ) 9 is formed on the surface of the first oxide film 9 by the VD method.
It is formed to a thickness of about 2 nm.
【００１９】次に、酸素を加え熱処理を行なうと、図２
（ｃ）に示すように第１の酸化膜（ＳｉＯ2）９の酸素
とアルミニウム１１が反応し、第２の酸化膜１２として
酸化アルミニウムを形成し、未反応のアルミニウムも供
給した酸素と反応し酸化アルミニウムとなる。更に、第
１の酸化膜（ＳｉＯ2）９のシリコンは下部電極８の上
に堆積し、第１の酸化膜（ＳｉＯ2）９は改質される。Next, when heat treatment is performed by adding oxygen, FIG.
As shown in (c), oxygen in the first oxide film (SiO 2 ) 9 reacts with aluminum 11 to form aluminum oxide as the second oxide film 12, and unreacted aluminum also reacts with the supplied oxygen. It becomes aluminum oxide. Furthermore, the first oxide film silicon (SiO 2) 9 is deposited on the lower electrode 8, the first oxide film (SiO 2) 9 is modified.
【００２０】次に、図２（ｄ）に示すように、減圧ＣＶ
Ｄ法によりＳｉ3Ｎ4膜１０を第２の酸化膜（酸化アルミ
ニウム）１２の表面上に形成する。Next, as shown in FIG.
By the method D, a Si 3 N 4 film 10 is formed on the surface of the second oxide film (aluminum oxide) 12.
【００２１】本実施例では、シリコンよりも酸化物生成
自由エネルギーの小さい物質としてアルミニウムを用い
たが、酸化アルミニウムは比誘電率が約８とＳｉ3Ｎ4の
７よりも大きく、容量を増加させることができる。In this embodiment, aluminum is used as a substance having a lower free energy of oxide formation than silicon. However, aluminum oxide has a relative dielectric constant of about 8 which is larger than 7 of Si 3 N 4 and increases the capacity. be able to.
【００２２】更に、禁止帯幅約１０ｅＶとＳｉＯ2より
も大きく、リーク電流を防ぎ信頼性向上にも寄与する。Further, the forbidden band width is about 10 eV, which is larger than that of SiO 2 , thereby preventing a leak current and contributing to an improvement in reliability.
【００２３】また、シリコンよりも酸化物生成自由エネ
ルギーの小さい物質にはＴｉ、Ｃｅ、Ｍｇ、Ｃａなどが
あり、これらの酸化物の誘電率および禁止帯幅の性質よ
り適用可能となり、更にシリコン以外の電極形成材料に
も、その酸化物の性質により適用可能となる。Materials having a lower free energy of oxide formation than silicon include Ti, Ce, Mg, Ca, etc., which are applicable due to the dielectric constant and bandgap properties of these oxides. It can be applied to the electrode forming material described above due to the nature of the oxide.
【００２４】また、片方の電極／絶縁膜／他方の電極が
横に並んだ構造をもつ容量素子においても適用可能とな
る。The present invention is also applicable to a capacitor having a structure in which one electrode / insulating film / the other electrode is arranged side by side.
【００２５】[0025]
【発明の効果】以上説明したように、本発明によれば、
容量素子の片方の電極を形成する材料膜よりも酸化物生
成自由エネルギーの小さい材料膜を自然酸化膜から成る
第１の酸化膜の表面上に形成した後に、酸素を供給しな
がら半導体基板を熱処理を行うことにより、この第１の
酸化膜を改質して第１の酸化膜よりも誘電率の高い第２
の酸化膜を形成し、更に、第２の酸化膜表面に窒化シリ
コン膜を形成するようになされる。この構成によって、
誘電率の低い自然酸化膜から成る第１の酸化膜を、より
誘電率の高い第２の酸化膜に改質することができ、この
第２の第２の酸化膜上に窒化シリコン膜を積層して成る
キャパシタ絶縁膜を有する容量素子を再現性良く製造す
ることができる。しかも、キャパシタ絶縁膜の高誘電体
化により蓄積容量の増加および、第２の酸化膜のＮａ +
バリヤ効果等によって容量素子の信頼性を向上させるこ
とができる。 As described above, according to the present invention,
Oxide is produced more than the material film that forms one electrode of the capacitor.
A material film with low free energy of formation consists of a natural oxide film
After forming on the surface of the first oxide film, do not supply oxygen.
By subjecting the semiconductor substrate to heat treatment,
The second oxide film is modified to have a higher dielectric constant than the first oxide film.
Oxide film is formed on the surface of the second oxide film.
A cone film is formed . With this configuration,
A first oxide film made of a natural oxide film having a low dielectric constant
It can be modified into a second oxide film having a high dielectric constant.
A silicon nitride film is laminated on a second second oxide film.
Manufacture capacitors with capacitor insulation film with good reproducibility
Can be Moreover, the high dielectric of the capacitor insulating film
Increases the storage capacity and increases the Na + of the second oxide film.
Improve the reliability of the capacitive element by barrier effect, etc.
Can be.
【図１】本発明による一実施例によって形成されたＤＲ
ＡＭスタックトキャパシタの断面図である。FIG. 1 shows a DR formed according to one embodiment of the present invention.
It is sectional drawing of an AM stacked capacitor.
【図２】本発明による一実施例を示し、図１に示すＤＲ
ＡＭスタックトキャパシタの絶縁膜形成工程における断
面図である。FIG. 2 shows an embodiment according to the present invention, wherein the DR shown in FIG.
It is sectional drawing in the insulating film formation process of AM stacked capacitor.
【図３】従来の方法によるＤＲＡＭスタックトキャパシ
タの断面図である。FIG. 3 is a cross-sectional view of a DRAM stacked capacitor according to a conventional method.
【図４】図３に示すＤＲＡＭスタックトキャパシタの絶
縁膜形成工程における断面図である。FIG. 4 is a cross-sectional view illustrating a step of forming an insulating film of the DRAM stacked capacitor shown in FIG. 3;
１ Ｐ型シリコン基板 ２ フィールド酸化膜 ３ Ｎ+拡散層 ４ ワード線（ポリシリコン） ５ ビット線（アルミニウム） ６ ＳｉＯ2膜 ７ 層間絶縁膜 ８ 片方の電極（下部電極） ９ 第１の酸化膜（ＳｉＯ2） １０ Ｓｉ3Ｎ4膜 １１ 材料膜（アルミニウム） １２ 第２の酸化膜（酸化アルミニウム） １３ 他方の電極（上部電極）Reference Signs List 1 P-type silicon substrate 2 Field oxide film 3 N + diffusion layer 4 Word line (polysilicon) 5 Bit line (aluminum) 6 SiO 2 film 7 Interlayer insulating film 8 One electrode (lower electrode) 9 First oxide film ( SiO 2 ) 10 Si 3 N 4 film 11 Material film (aluminum) 12 Second oxide film (aluminum oxide) 13 The other electrode (upper electrode)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 27/04 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/108 H01L 21/316 H01L 21/318 H01L 21/822 H01L 21/8242 H01L 27/04 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 identification code FI H01L 27/04 (58) Investigated field (Int.Cl. 7 , DB name) H01L 27/108 H01L 21/316 H01L 21/318 H01L 21/822 H01L 21/8242 H01L 27/04
Claims (2)
電極から構成される容量素子の片方の電極表面上に誘電
率の低い自然酸化膜から成る第１の酸化膜が生じた半導
体基板における容量素子の形成方法であって、 前記片方の電極を形成する材料膜よりも酸化物生成自由
エネルギーの小さい材料膜を当該片方の電極上の第１の
酸化膜表面に形成する工程と、酸素を供給しながら当該半導体基板を 熱処理を行うこと
により、誘電率の低い前記第１の酸化膜を改質して第１
の酸化膜よりも誘電率の高い第２の酸化膜を形成する工
程と、その後、 前記第２の酸化膜表面に窒化シリコン膜を形成する工程
とを含むことを特徴とする容量素子の形成方法。A dielectric is formed on the surface of one electrode of a capacitor composed of one electrode / capacitor insulating film / the other electrode.
A semiconductor in which a first oxide film made of a natural oxide film having a low rate is formed
A method of forming a capacitive element in the body substrate, forming a low material film of oxide formation free energy than the material film for forming the one electrode on the first surface of the oxide film on the one electrode Heat-treating the semiconductor substrate while supplying oxygen to modify the first oxide film having a low dielectric constant to form the first oxide film .
Forming a second oxide film having a dielectric constant higher than that of the second oxide film, and thereafter forming a silicon nitride film on the surface of the second oxide film. Element formation method.
晶シリコンとし、前記 酸化物生成自由エネルギーの小さい材質膜をアルミ
ニウム金属とすることを特徴とする請求項１記載の容量
素子の形成方法。Wherein the material film for forming the one electrode and the polycrystalline silicon, the method of forming the capacitor element of claim 1, wherein the small material film with the oxide formation free energy, characterized in that the aluminum metal .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00313592A JP3180404B2 (en) | 1992-01-10 | 1992-01-10 | Method of forming capacitive element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00313592A JP3180404B2 (en) | 1992-01-10 | 1992-01-10 | Method of forming capacitive element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05190792A JPH05190792A (en) | 1993-07-30 |
| JP3180404B2 true JP3180404B2 (en) | 2001-06-25 |
Family
ID=11548912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00313592A Expired - Fee Related JP3180404B2 (en) | 1992-01-10 | 1992-01-10 | Method of forming capacitive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3180404B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465297B1 (en) * | 2000-10-05 | 2002-10-15 | Motorola, Inc. | Method of manufacturing a semiconductor component having a capacitor |
| WO2004053997A1 (en) * | 2002-12-09 | 2004-06-24 | Interuniversitair Microelektronica Centrum (Imec) | Method for forming a dielectric stack |
-
1992
- 1992-01-10 JP JP00313592A patent/JP3180404B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05190792A (en) | 1993-07-30 |
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