JP3179792B2 - Multi-port random access memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-port random access memory, and more particularly, to a dual-port memory used for graphic display.

[0002]

2. Description of the Related Art In the field of information processing, image information (graphic information) to be processed or processed is stored on a CRT.
Display on a (cathode ray tube) display is performed. At this time, a memory called a frame buffer for storing one frame of image information is used. Such a frame buffer is typically a video RAM (VRAM)
Called. The configuration and operation of the image processing system using the video RAM will be briefly described with reference to FIG.

In FIG. 8, a video signal processing system includes a CP
U (central processing unit) 100, a CRT display controller 102, a video RAM 104, and a CRT display 106.

The CPU 100 writes desired data to the video RAM 104 or reads desired data. The CRT display controller 102 is a CRT
A horizontal / vertical synchronization signal for the display 106 is generated, and an address for reading data from the video RAM 104 is generated and applied to the video RAM 104.

[0005] The video RAM 104 stores image information to be processed or processed, and the stored image information is read out under the control of the CRT display controller 102 and provided to the CRT display 106.

[0006] The CRT display 106 has a video RA.
The data from M104 is displayed on the display screen.

For the video RAM 104, the CPU 1
No. 00 can be randomly accessed to perform read (read) / write (write). Thus, after performing a desired operation on the information stored in the video RAM 104, the data can be written into the video RAM 104 again. On the other hand, the video R
Data read serially from the AM 104 is provided, and an image according to the provided data is displayed on the screen of the CRT display 106.

When a normal dynamic random access memory (DRAM) is used as a frame buffer, in order to generate a video signal to be displayed on the screen of the CRT display 106, the DRAM always generates a video signal during a display period. Data must be read.

In a normal DRAM, one memory cycle is defined as either a read cycle or a write cycle. Therefore, during this display period, CPU 100 cannot access the DRAM, and the access period of CPU 100 to video RAM 104 is limited to outside the display period during the horizontal or vertical blanking period. As a result, C
The waiting time of the PU increases, and the execution speed of the program decreases.

In order to overcome the drawbacks of using a normal DRAM as a frame buffer, a multi-port RAM (dual-port RAM) has been widely used as an image memory. The multi-port RAM has an input / output port (RAM port) that the CPU 100 can access at random, and a serial port for serially reading display data under the control of the CRT display controller 102 and supplying the display data to the CRT display 106. And an input / output port (SAM port).

In this multi-port RAM, R
If data for one row (corresponding to data for one horizontal scanning line) is transferred from the AM port to the SAM port, display data is read from the SAM port during the display period, and during that time,
The CPU 100 can access the RAM port. Thereby, the waiting time of the CPU is reduced, and the execution speed of the program is increased.

FIG. 9 schematically shows an example of the entire configuration of a conventional multi-port RAM. The multi-port RAM shown in FIG. 9 has one RAM input / output port and one
And has two SAM input / output ports and is commonly referred to as a dual port RAM. Hereinafter, this dual port R
AM will be described.

Referring to FIG. 9, a conventional dual port R
AM is largely divided into a RAM port portion and a SAM port portion. The RAM port portion decodes a memory cell array 1 composed of a plurality of memory cells arranged in a two-dimensional array composed of rows and columns, and an internal address signal Add generated corresponding to an external address. A row decoder 2 for selecting a corresponding row, and an internal address signal Ad generated in response to an external address
d as a column address to select a corresponding column of the memory cell array 1 and a column decoder / IO control circuit 3 for controlling input / output of data to / from the selected column.

Row decoder 2 receives and decodes applied internal address signal Add as a row address in response to internal row address strobe signal RAS, and decodes the same.
The corresponding row of the memory cell array 1 is selected.

In response to internal column address strobe signal CAS, column decoder / IO control circuit 3 receives and decodes applied internal address signal Add as a column address and decodes the corresponding column of memory cell array 1. select.

The column decoder / IO control circuit 3
Controls data read and write in response to a read / write signal R / * W designating data read / write. That is, column decoder / IO control circuit 3 transfers the data to be written to the selected memory cell in response to the later falling of external control signal * CAS and signal R / * W. The column decoder / IO control circuit 3 is connected to an input / output buffer (not shown) via a data bus DQ. The operation of this RAM input / output buffer is controlled by the IO control portion of the column decoder / IO control circuit 3.

Here, an internal row address strobe signal RAS and an internal column address strobe signal CAS are respectively applied to an external row address strobe signal CAS supplied from outside.
Address strobe signal * RAS and external column
Internal control signal generated in response to address strobe * CAS.

The SAM port portion includes the memory cell array 1
SAM register 4 having a number of register elements capable of transferring data simultaneously with one row of memory cells, counter 6 for counting clock signal SC, and decoding the count value from counter 6 And a SAM decoder 5 for selecting the register element and connecting the selected register element to the internal serial data bus SO.

The SAM register 4 stores a transfer instruction signal * DT
And transfer gate means for simultaneously receiving data of a selected row of memory cell array 1 in response to the data. This SA
Data transmitted from M register 4 onto internal serial data bus SO is output via a SAM input / output buffer (not shown). Counter 6 responds to internal column address strobe signal CAS by using internal address signal A.
dd is fetched and set to the internal address signal Add fetching the initial count value. The initial setting function of the counter 6 is activated by the transfer instruction signal * DT. Next, the operation will be described.

Image data to be displayed is created by a CPU or the like and transmitted to the RAM port of the dual port RAM. In the RAM port portion, the control signal R
Under the control of AS and CAS, address signal Add is decoded by row decoder 2 and column decoder / IO control circuit 3, and a corresponding memory cell is selected from memory cell array 1.

Next, the image data to be displayed created and transmitted by the CPU or the like is transmitted to the selected memory cell via the data bus DQ and the column decoder / IO control circuit 3. Here, at the time of data writing, read / write signal R / * W is at “L” level indicating data writing.

In the address signal, a row address signal and a column address signal are given in time division, respectively.
The row address and column address signals are determined by the row address strobe signal RAS and the column address signal.
This is performed by the strobe signal CAS. Writing of data from the CPU or the like to the memory array 1 at the RAM port is the same as that of a normal DRAM.

The image data stored in the memory cell array 1 is read through a SAM port in order to transmit the image data to a CRT or the like which is a raster scan type display device at a high speed. The operation of reading data from the SAM port will be described with reference to an operation waveform diagram of FIG.

Reading of data from the SAM port section is as follows.
Address signal Add, signals * RAS, * CAS and *
This is performed by transferring data for one row from the memory cell array 1 to the SAM register 4 under the control of the DT. The data is transferred from the memory cell array 1 to the SAM register 4 when the external row address strobe signal * RAS is activated ("L" level).
It is instructed by setting the transfer instruction signal * DT to "L" and the signal R / * W to "H". At this time, a control signal * for specifying enable / disable of the SAM port *
SE is an arbitrary state.

In this state, address signal Add is decoded by row decoder 2 as a row address signal at the fall of external row address strobe signal RAS, and a row in memory cell array 1 is selected. After the data of the memory cell connected to the selected row in memory cell array 1 is transmitted on the bit line (column), the data is simultaneously sent to SAM register 4 in response to the rise of transfer instruction signal * DT. Will be transferred.

On the other hand, in response to the fall of external column address strobe signal * CAS, address signal Ad is output.
d is loaded into the counter 6. The column address signal loaded into the counter 6 specifies a register element selected first in the SAM register 4. That is,
The counter 6 is made loadable by the "L" state of the transfer instruction signal * DT, and loads a given column address signal in response to the signal CAS.

The counter 6 counts the control clock signal SC and supplies the count value to the SAM decoder 5 as a register element designation signal. The SAM decoder 5 decodes the given count value, selects a register element of the SAM register 4, and connects the selected register element to the internal serial data bus SO.

The data SO on the internal data bus SO is SA
Output via M input / output buffer. That is, SA
Register elements are sequentially selected from M register 4 in response to clock signal SC, and data of the selected register element is transmitted to internal data bus SO.

Since serial data SO read from this SAM port is read in response to clock signal SC, signals * RAS and * C are applied as in a normal DRAM.
There is no need to specify a memory cell by AS, and data can be read at high speed. The serial data SO read from this SAM port is transmitted to the display device.

[0030]

As described above, in the conventional dual port RAM, the address strobe signals * RAS and * CAS are used in synchronism with the address strobe signals * RAS and * CAS in the same manner as in a general-purpose memory. A memory cell is selected, and image data is written in the selected memory cell.

To output image data to the display device, the transfer mode is selected by setting the transfer instruction signal * DT to "L". Then, an address signal for selecting a transfer row in memory cell array 1 is input in synchronization with address strobe signal * RAS. An address signal (column address) Add input in synchronization with the column address strobe signal * CAS is applied to a counter 6 for specifying the address of the SAM port,
This is a start address to start reading M data.

Thereafter, every time the clock signal SC is input to the counter 6, the count value of the counter 6 is incremented and continuously synchronized with this clock signal to generate the SAM.
Data is output from the port.

FIG. 11 is a diagram showing the correspondence between the memory cell position of the memory cell array and the display position on the display screen of the display device. As shown in FIG. 11, the memory cell position of the memory cell array 1 and the display position on the display screen CRT have a one-to-one correspondence. That is, the memory cell array 1
1 row corresponds to one horizontal scanning line on the display screen CRT. Here, in FIG. 11, the memory cell array 1
A row includes 256-bit memory cells and a display screen CRT
The case where one horizontal scanning line is composed of 256 dots is shown as an example. In FIG. 11, the position of each memory cell is shown in hexadecimal.

The SAM register 4 stores the memory cell array 1
The same number of register elements as the number of columns are provided, and each register element is provided corresponding to each bit line pair of the memory cell array 1. At the time of data transfer, data of one row of the memory cell array 1 is transferred to the SAM register 4 as it is. Therefore, the address (column address) in the column direction of the memory cell array 1 and the SAM read address (S
(The selected address of the AM register) has a one-to-one correspondence.

According to such a memory mapping, according to the scan order of the raster scan type display device,
Image data can be processed at high speed. That is,
When processing image data in accordance with the memory mapping shown in FIG. 11, the CPU or the like can access the RAM port at high speed using a high-speed access mode (page mode, static column mode, etc.) and process the data. it can.

However, if this high-speed access mode is used, the access in the column direction can be performed at a high speed, but the signal RAS must be toggled to change the row address in the access in the row direction. The change of the row address due to the toggle of the signal RAS is performed in a normal DR.
Like AM, control of signals RAS and CAS is required, and it is necessary to take in a row address and a column address. Therefore, the access speed in the row direction is lower than that in the column direction.

In the application of the image processing,
, Such as several lines of Table示画face CRT (display screen
(Vertical direction) Image data may be processed. When such image data processing is performed, in the memory mapping of FIG. 11, it is necessary to access each row of the memory cell array 1 for each row of the display screen CRT, and it is necessary to frequently access in the row direction. Therefore, in this case, there is a problem that the high-speed access mode generally provided in the RAM port as described above cannot be effectively used. Here, FIG. 12 shows an example of a memory mapping in which one row of the memory cell array 1 corresponds to four rows of the display screen CRT.

Further, even if the data processing of the memory cell array 1 is executed via the RAM port according to the memory mapping, the SAM port remains on the display screen C.
Since data corresponding to one row of RT is sequentially output, data cannot be read serially from the SAM port and displayed on the display screen CRT as it is. In this case, processing such as rearrangement of data is required in the display device, and an image processing system with a simple circuit configuration cannot be obtained.

Even if it is possible to rearrange the data read from the SAM port using an external device, if the CPU or the like accesses the RAM port, the data is read every line on the display screen. It is necessary to set a row address.
It is required for each row on the RT and cannot execute high-speed data processing.

It is an object of the present invention to provide the above-described conventional multi-multi
An object of the present invention is to provide a multi-port RAM capable of processing two-dimensional image data at high speed while eliminating the disadvantages of the port RAM.

It is another object of the present invention to provide a multi-port RAM capable of mapping one row of memory cells of a memory cell array over a plurality of rows on a display screen.

[0042]

[MEANS FOR SOLVING THE PROBLEMS] A multi-channel device according to the present invention is provided.
The port RAM includes a memory cell array including a plurality of memory cells arranged in a two-dimensional array, a data register including a number of register elements capable of transferring data simultaneously with one row of memory cells in the memory cell array, and a clock. A counter for counting signals; and a selection circuit for decoding a count value of the counter as a register element designation signal, selecting a corresponding register element from a data register, and connecting to the internal data bus.

This counter has a function of counting by skipping the count value by a predetermined value.
This counter counts the clock signal
Circuit and a count-up instruction signal from this count circuit.
And an offset counter for counting signals. these
Count circuit and offset counter output count
Is output as the count value of the counter means.
Preferably, the count circuit activates the load instruction signal.
Time, part of the externally applied address signal is
And the offset counter is loaded
Data input / output node of RAM port when instruction signal is activated
Has a function to store the data given to the
You. Preferably, the counting operation of the counting means is repeated until all the contents of the data register are read.
Will be returned.

[0044]

The count value from the counter is skipped by a predetermined value and output in response to a clock signal. The selector circuit selects a corresponding register element from the data register by using the skipped count value from the counter as an address signal. This allows
It is possible to make one row of data in the memory cell array correspond to a plurality of rows on the display screen.

[0045]

FIG. 1 is a diagram schematically showing an entire configuration of a dual port RAM according to an embodiment of the present invention. In FIG. 1, the conventional dual port R shown in FIG.
Parts corresponding to the AM parts are denoted by the same reference numerals. The dual port RAM shown in FIG. 1 includes a counter 6 'having an offset function and performing a count operation by skipping a predetermined count value, instead of the counter 6 which counts the clock signal SC.
Counter 6 'is activated in response to transfer instruction signal * DT, loads internal address signal Add provided in synchronization with signal CAS, and counts clock signal and counter circuit 60, and transfer instruction signal *. An offset register 70 is activated in response to DT and loads data DQ applied to a data input / output unit (RAM input / output circuit) of a RAM port in synchronization with a signal CAS. Carry signal C from counter circuit 60 is applied to offset register 70. Offset register 70
When carry signal C is supplied from counter circuit 60, the register contents are incremented by "1".

Outputs of the counter circuit 60 and the offset register 70 are supplied to the SAM decoder 5 as a register element designation signal of the SAM register 4. Counter circuit 60 gives the upper bits of the read address (register element designating signal), while offset register 70 gives the lower bits of the read address. Therefore, counter circuit 60 takes in address signal bits other than the address signal bits expressed by offset register 70 among the internal address signals Add applied to the address buffer as its start address.

Address buffer 40 receives externally applied address signals A0 to An, and responds to external row address strobe signal * RAS and external column address strobe signal * CAS to apply the applied address signal. The fetched internal row address signal and internal column address signal are derived.

Control unit 50 receives various control signals * RAS, * CAS, R / * W, SC, * SE and * DT provided from the outside, and receives internal control signals RAS, CAS, R /
Generates * W, SC and * DT. Next, the operation will be described with reference to FIG. 2 which is an operation waveform diagram.

First, in the same manner as in the prior art, the transfer instruction signal * DT is set to "L" and the read / write signal R / * W is set to "H" at the fall of the signal * RAS. As a result, the dual port RAM is set to the transfer mode. Address buffer 40 takes in external addresses A0-An in response to the fall of signal * RAS and generates internal address signal Add. Row decoder 2 fetches and decodes an address signal applied in response to the rise of internal signal RAS as a row address signal, and selects a corresponding row in memory cell array 1.

Then, when signal * CAS falls, external address signals A0-An applied at that time are fetched by address buffer 40, and counter 6 'and column decoder / IO control are provided as internal column address signal Add. Provided to circuit 3.

Offset register 70 of counter 6 '
Responds to the rise of signal CAS, takes in data DQ supplied to the RAM input / output circuit and stores it as an offset value. Further, counter circuit 60 takes in an address signal of a predetermined bit in applied internal address signal Add in response to signal CAS, and stores it as a start address.

Next, when the clock signal SC is toggled, the counter circuit 60 increments the count value. The SAM decoder 5 decodes a signal from the counter 6 'comprising the counter circuit 60 and the offset register 70 as a read address, selects a corresponding register element from the SAM register 4 and connects it to the internal data bus SO, and outputs the serial data. Outputs SO.

Now, the offset register 70 is a 2-bit register, the counter circuit 60 is a 6-bit counter, and one row of the memory cell array 1 has 256 bits (0 to 255 (decimal): 00 to FF (hexadecimal). )). In this case, the 6-bit count value from the counter circuit 60 is used as the upper address signal bit of the SAM port read address,
Bit data is used as a lower read address signal bit of the SAM port. It is assumed that data DQ taken into offset register 70 in response to the rise of internal signal CAS is "00".

If row decoder 2 selects the 0th row of memory cell array 1, "L" of transfer instruction signal * DT
In response to the rise from "H" to "H", the 256-bit data in the 0th row of the memory cell array 1 is collectively transferred to the SAM register. It is also assumed that the column address signal (internal address signal Add) also specifies the 0th column. In this case, since the offset value set in the offset register 70 is “00” and the initial setting value of the counter circuit 60 is the address “00... 00”, the offset value is selected by the SAM decoder 5 in response to the clock signal SC. SA
Ban areas of the M register 4, the "00H".

Next, when the clock signal SC is supplied, the count value of the counter circuit 60 is incremented by one. At this time, the content of the offset register 70 is “0”.
0 "because while the is in, turn locations SAM port specified by the SAM decoder 5 becomes 04H. Hereinafter, each time the clock signal SC is toggled, turn locations 08H from SAM register 4, 0CH, 10H, 14H, 18H, 1
Turn land with a CH, an offset value of 4 bits are sequentially selected, data of the corresponding register element is output through the sequential SAM output circuit (not shown).

When the count value of the counter circuit 60 reaches FCH, display of one line of image data on the display device is completed.

When the count value of counter circuit 60 returns to 00H from FCH, carry signal C is output from counter circuit 60 and applied to offset register 70. The offset register 70 includes a counter circuit 60
The content is incremented by one in response to carry signal C from. At this time, the content stored in the offset register 70 is 01H. Subsequently, each time the clock signal SC is applied, the counter circuit 60 sets the count value to 1
Because the value is incremented, S
The AM port read address is 01H, 05H, 09
H, ...

Thereafter, the contents of the offset register 70 are incremented by one every time the display of one line on the display screen of the display device is completed by repeating the above operation. When the stored content of the offset register 70 reaches 00H, the SAM
All data for one row of the memory cell array 1 stored in the register 4 is output. As a result, the SAM register 4 has output image data for four lines of the display screen.

Since the offset register 70 has a counter function, two-dimensional data (four rows in the above-described embodiment) is continuously transmitted from the memory cell data for one row of the memory cell array 1 to the display screen. Can be output.

At this time, since the read address of the SAM port can be made independent of the column address of the RAM port by the function of the offset register 70, the memory mapping shown in FIG. And can be easily realized.

Since the offset register 70 has a counting function as described above, data to be displayed two-dimensionally on the display screen is represented as one line of data on the RAM port. Image processing can be performed by accessing the RAM port using the access mode, display image data can be written to the RAM port at high speed, and image data processing can be performed efficiently.

Here, when loading the data DQ given to the RAM port into the offset register 70,
Although the number of data is described as 2 bits, this is because a dual-port RAM can normally be accessed in units of a plurality of bits, and a plurality of RAM data input / output pins are provided. In the case of access in units of a plurality of bits, the memory cell array is usually divided into blocks corresponding to each data bit, and a SAM register 4 is provided corresponding to each block. Also in this case, the same row is usually selected from each block, and one row of data selected from each block corresponds to one row on the display screen of the display device.

Therefore, in the case of the access configuration in units of a plurality of bits, it is sufficient to consider the memory cell array 1 shown in FIG. 1 as a memory cell array block and to provide four memory cell array blocks. In the case of access in units of a plurality of bits, a plurality of SAM registers are provided corresponding to each block. Normally, data from the plurality of SAM registers is read in parallel.

Next, specific configurations of the counter circuit 60 and the offset register 70 will be described.

FIG. 3 is a diagram showing an example of a specific configuration of the counter shown in FIG. 3, the offset register 70 includes flip-flops 71 and 72 and an AND gate 73. Flip-flop 71 has a D input terminal receiving offset data DQ0 and a clock input terminal C receiving carry signal C from counter circuit 60.
K, an L input terminal for receiving the load instruction signal DT1, and Q
An output terminal. Q of this flip flop 71
The lowermost read address signal bit A0 is output from the output terminal.

AND gate 73 receives carry signal C from counter circuit 60 and output signal A0 from the Q output terminal of flip-flop 71.

Flip-flop 72 has a D input terminal for receiving offset data DQ1, a CK input terminal for receiving the output of AND gate 73, an L input terminal for receiving load instruction signal DT1, and a Q output terminal. A read address signal bit A1 is output from the Q output terminal of flip-flop 72.

The load instruction signal DT1 is a transfer instruction signal *
DT is received at its false input and is generated by an AND gate 74 which receives the internal signal CAS at its true input. The flip-flops 71 and 72 invert the signal state of the Q output terminal in response to the fall of the signal applied to the clock signal input terminal CK. Also flip flop 7
Responding to the rise of data load instruction signal DT1 applied to its L input terminal, 1, 72 latches the data applied to its D input terminal and transmits it to its Q output terminal.

The counter circuit 60 includes flip-flops 61, 62,... 63 and AND gates 64, 65. The flip-flops 61 to 63 are flip-flops 71 and 7 included in the offset register 70, respectively.
2 has the same configuration. Flip flop 61
Has an internal address signal bit Add2 at its D input terminal.
And receives the clock signal SC at its clock signal input terminal CK. Q of flip flop 61
A read address signal bit A2 is output from the output terminal.

Flip flop 62 receives internal address signal bit Add3 at its D input terminal, and receives the output of AND gate 64 at its clock signal input terminal CK. A read address signal bit A3 is output from the Q output terminal of flip-flop 62. AND gate 64
Receives the output signal A2 from the Q output terminal of the flip-flop 61 and the clock signal SC.

Flip-flop 63 receives an internal address signal bit Addn at its D input terminal, and receives the output of AND gate 65 at its clock input terminal CK.
Carry signal C is output from the Q output terminal of flip flop 63 and transmitted to offset register 70, and the most significant read address signal bit An is output.

AND gate 65 receives outputs from Q output terminals of flip-flops of all stages, that is, read address signal bits A2 to An-1, and clock signal SC.

That is, an AND gate is provided for the flip-flops of the second and subsequent stages in the counter circuit 60, and the output of the AND gate is transmitted to the corresponding flip-flop clock signal input terminal CK. You. Each AND gate receives an output signal from the Q output terminal of all the flip-flops in the preceding stage and a clock signal SC.

Load instruction signal DT2 receives data transfer instruction signal * DT at its false input and internal signal CA at its true input.
S is generated by an AND gate 66 receiving S. This load instruction signal DT2 is supplied to flip-flops 61-63.
To the load input terminal L. Next, the operation of the counter shown in FIG.
This will be described with reference to FIG.

First, the operation of the offset register 70 will be described with reference to FIG. When data transfer instruction signal * DT falls to "L", AND gate 74 passes internal signal CAS applied to its true input. Therefore, when internal signal CAS rises to "H", flip-flops 71 and 72 latch data DQ0 and DQ1 applied to their D input terminals, respectively, and output from their Q outputs. At this time, the offset data is given to the RAM data input / output pin in synchronization with the external signal * CAS. Therefore, as shown in FIG. 2, the offset register 70 is synchronized with the fall of the control signal * CAS. Is set to the offset value.

In this state, read address signal bits A0 and A1 are equal to offset data DQ0 and DQ1 provided from the RAM port, respectively. Next, a clock signal SC is generated, a count operation of the counter circuit 60 is performed, and a carry signal C is generated when the count value of the counter circuit 60 returns from the maximum value to the initial value. Carry signal C is applied to clock input terminal CK of flip-flop 71. Flip-flop 71 responds to the fall of the signal applied to clock input terminal CK to output signal A0 from its Q output terminal.
Is inverted. Therefore, when the counter circuit 60 counts up to the maximum count value and returns to the initial value, the outputs A1 and A0 of the offset register 70 become 0 and 1, respectively. The AND gate 73 outputs an “H” signal only when an “H” signal is applied to both inputs thereof, so that the output of the AND gate 73 remains “L”. Therefore, the signal A1 from the Q output terminal of the flip-flop 72 holds 0 in the initial state.

The counter circuit 60 executes the counting operation again, and outputs the carry signal C when returning from the maximum count value to the initial value. The carry signal C is the same signal as the most significant read address signal bit An, and falls from "H" to "L" when returning from the maximum count value to the initial value. This state is a state where the carry signal C is generated. Immediately before the carry signal C is generated, the carry signal C and the signal A0 are both at "H", so that the AND gate 73 outputs a signal of "H". When carry signal C is generated and the output of AND gate 73 falls from "H" to "L", the flip-flop inverts the state of signal A1 from its Q output terminal. That is, the signal A1 changes from “L” to “H”.

In response to the falling of carry signal C, flip-flop 71 provides signal A from its Q output terminal.
The state of 0 is inverted to “L”. In this state, the contents A1, A0 stored in the offset register 70 are 1, 0.
Becomes Hereinafter, by repeating this operation, a set (A) of the output signals A1 and A0 from the offset register 70 is set.
(1, A0) is (0,0), (0,1), (1,0),
(1,1) and (0,0) are repeated. Here, the logical value “0” corresponds to the potential level “L”, and the logical value “1” corresponds to the potential level “H”.

Next, the operation of the counter circuit 60 will be described with reference to FIG.
This will be described with reference to FIG. In this counter circuit 60 as well, load signal DT2 from AND gate 60 rises to "H" when internal signal CAS rises, and flip-flops 61-63 receive address signal bits Add2-- applied to their D input terminals. Addn is fetched as an initial setting value, and is output from the Q output terminal as an initial value of a SAM read address.

Subsequently, each time the clock signal SC rises to "H", the read address A is read by the SAM decoder 5.
0 to An are decoded, and the contents of the SAM register 4 are sequentially read. Each time the clock signal SC falls, first, the signal A from the Q output terminal of the flip-flop 61
The state of 2 is reversed. Even if the signal A2 becomes "H" in response to the first falling of the clock signal SC, the output of the AND gate 64 becomes "L" since the clock signal SC has already fallen to "L" at that time. On the level. Therefore, the signals A3 to An of all the flip-flop Q output terminals higher than the flip-flop 62 maintain the previous state.

When the clock signal SC falls for the second time,
Signal A2 from flip flop 61 falls to "L". In the second rising period of clock signal SC, the output of AND gate 64 is at "H", and signal A
In response to the fall of 2, the output of AND gate 64 falls. As a result, the state of the signal A3 from the Q output terminal of the flip-flop 62 is inverted to “H”. An AND gate is provided for each of the flip-flops 62 to the upper flip-flop, and the output of the AND gate is supplied to the clock input terminal CK. The AND gate 64 receives the signal of the Q output terminal from all the flip-flops in the preceding stage. When clock signal SC falls ^2n-2 times, read address signal bit An rises to "H", and clock signal SC rises to ^2n-1.
When falling, the highest read address signal An becomes "H".
To "L", and the counter circuit 60 returns to the initial state. At this time, carry signal C is generated.

With the above structure, the offset consisting of the two least significant bits of the read address is incremented by one each time the counter circuit 60 reaches the maximum count value. Therefore, the initial value is offset every count cycle and the count operation is performed. A counter having an offset / skip function of skipping every four bits can be obtained.

That is, as shown in FIG. 3, internal address signal bits Add2 to Adddn are used as initial setting values, and data D supplied to RAM input / output data bus
Q0 and DQ1 are used as offset designation data, and the output of the offset register 70 is supplied to the SAM decoder 5 using the lower 2 bits as a read address signal and the output signal from the counter circuit 60 as upper read address signals A2 to An. A counter having an offset function in which a count value skipped by four bits is output for each clock signal and the initial value is incremented by one bit for each count cycle can be obtained.

The configuration of the counter circuit having the offset function is not limited to the configuration shown in FIG. 3, but a presettable binary counter is used, each of which is used independently of the offset register and the counter circuit 60. The same effect as in the above embodiment can be obtained with any circuit configuration as long as the offset register counts in response to a carry or borrow signal from the circuit 60.

The counter circuit shown in FIG. 3 increments the count value in response to clock signal SC, and offset register 70 performs a count operation using carry signal C from counter circuit 60 as a clock signal. I have. However, instead, the counter circuit 60 decrements its contents in response to the clock signal SC, derives a borrow signal when the minimum count value is reached, and supplies it to the offset register 70, and the offset register 70 Even with a counter configuration that counts down, the same effect as in the above embodiment can be obtained.

According to the above configuration, memory cells for one row of the memory cell array 1 are distributed over four rows on the display screen. Therefore, one row of data in one memory array corresponds to only 1/4 horizontal scanning line on the display screen. In this case, as shown in FIG. 6, four dual-port RAMs having the same configuration are used, each of which corresponds to a quarter area on the display screen. That is, as shown in FIG. 6, dual port memories M1, M2, M3 and M4 having the same configuration are provided in parallel, and the CPU 10 is connected to these four memories M1 to M4.
0 accesses sequentially or in parallel , and the memory M1
To M4 are sequentially read and transmitted to CRT 106. Although the number of dual port RAMs increases, each dual port RA
Since the storage capacity of M is only 1/4 that of the conventional one, the overall storage capacity is almost the same as that of the conventional one.

In the case of the memory configuration shown in FIG.
100 outputs data and addresses according to the memory mapping as shown in FIG. Therefore, whether the memories M1 to M4 are accessed sequentially or simultaneously depends on the configuration of the memory system. C
PU data bus width is equal to RA of each of memories M1 to M4.
If the input and output bits of the M data are four times as large, simultaneous access can be made in parallel. In either case,
In each of the dual-port RAMs M1 to M4, four rows of data are written for the same row, so that data can be written at high speed using the high-speed access mode of the RAM port.

The dual port RAMs M1 to M4 to C
The transfer of data to the RT 106 is performed at each dual port R
The configuration may be such that data is sequentially read from AM, or data is simultaneously read from dual port RAMs M1 to M4 and stored in a shift register, for example, and then sequentially read in a predetermined order.

The memory M of the memory system shown in FIG.
FIG. 7 shows the correspondence between 1 to M4 and the display screen. Thus, a dual port RAM (memory)
Each of M1 to M4 corresponds to each of the four divided areas # 1 to # 2 of the display screen CRT. FIG.
Has shown a configuration in which four dual-port RAMs are provided in parallel, but instead, four memory cell arrays and SAM registers are integrated on one semiconductor chip, and One SA
M registers may be provided and operated independently to process the data in each of the four divided areas, and the four divided data may be sequentially read out in parallel or serially. At this time, SA
If data is read out serially by sequentially activating the M register for each memory area, data can be read at high speed.

Even in the case of such a one-chip configuration, the CPU 100 can write four rows of data by accessing each row of each memory area. Can be performed.

In the above embodiment, the case where the offset register has 2 bits and the counter circuit has 6 bits has been specifically described as an example. However, the number of these bits can be set arbitrarily. According to the configuration of the present invention, the bit value of the read address skipped by the offset register is 2 ⁿ bits, where n is the number of bits in the offset register.

Further, in the operation waveform diagram shown in FIG.
Data DQ applied to the RAM port in response to the rise of internal signal CAS is loaded into the offset register. However, address signals Add0 and Add1 provided in synchronization with the rise of internal signal CAS may be used as offset data, and internal signal RAS may be used.
When data rises, data DQ applied to the data input / output terminal of the RAM port may be taken. In this case, in the circuit configuration shown in FIG. 3, internal signal RAS is applied to the true input of AND gate 74 instead of internal signal CAS.

Further, as the offset data applied to the offset register, data from the RAM data input / output terminal is used, thereby preventing the provision of extra pins. However, when there is an unused pin terminal at the time of package mounting in the dual port RAM, the pin terminal may be used as an offset data input pin.

In the above embodiment, the dual
Although port RAM has been described as an example, this generally means that R
Even in a multi-port RAM provided with a plurality of AM data input / output ports and a plurality of SAM data input / output ports, the same effect as in the above embodiment can be obtained.

[0095]

As in the above, according to the present invention, according to the present invention, so as to read the data and the read address of the SAM port of multi-port RAM to skip by a certain address
Therefore, the column address of the RAM port and the read address of the SAM port can be made independent, and RA
One row of the M port can correspond to a plurality of rows on the display screen of the display device, and two-dimensional processing of image data can be performed using the high-speed access mode in the RAM port. Further, by processing one row of data in the RAM port, it is possible to process a plurality of rows of data on the display screen of the display device, and it is possible to efficiently process two-dimensional image data at high speed. . Ma
Also, this SAM port read address skip function
And a counting circuit that counts clock signals,
Counts the count-up instruction signal of the count circuit
Because it is realized using an offset counter,
The SAM port read address can be easily scanned with a simple circuit configuration.
This configuration can realize a configuration that allows for

[Brief description of the drawings]

FIG. 1 shows a dual port R according to an embodiment of the present invention.
It is a figure showing an example of the whole composition of AM.

FIG. 2 is a signal waveform diagram showing an operation of the dual port RAM according to the present invention.

FIG. 3 is a diagram illustrating an example of a specific configuration of a counter illustrated in FIG. 1;

FIG. 4 is a signal waveform diagram representing an operation of the offset register shown in FIG.

FIG. 5 is a signal waveform diagram representing an operation of the counter circuit shown in FIG. 3;

FIG. 6 is a diagram showing a configuration example of a memory system using a dual port RAM according to the present invention.

FIG. 7 is a diagram showing a correspondence relationship between a memory area of a dual port RAM and a display screen of a display device according to the present invention.

FIG. 8 is a diagram showing a configuration example of a system used in a conventional video signal processing system.

FIG. 9 is a diagram schematically showing an entire configuration of a conventional dual port RAM.

FIG. 10 is a signal waveform diagram showing a data read operation of a SAM port of a conventional dual port RAM.

FIG. 11 is a diagram showing a correspondence relationship between a memory cell array in a conventional dual port RAM and a display screen of a display device.

FIG. 12 is a diagram for explaining a problem of a conventional dual port RAM.

[Explanation of symbols]

 1: memory cell array 2: row decoder 3: column decoder / IO control circuit 4: SAM register 5: SAM decoder 6, 6 ': counter 60: counter circuit 70: offset register

Claims (3)

(57) [Claims] 1. A multi-port random access memory having a randomly accessible RAM port and a serially accessible SAM port, wherein the SAM port inputs / outputs data serially with the outside of the memory. A memory cell array having a plurality of memory cells arranged in a two-dimensional array consisting of rows and columns; a memory cell array having a plurality of memory cells arranged in rows and columns; Data register means including a plurality of register elements, and a clock signal.
A counting circuit for counting, wherein the counting circuit
The count value is sequentially updated each time the clock signal is applied
And a count-up instruction from the counting circuit.
Offset counter, and the mosquito counts the signal
Count value from the counter circuit and the offset cowl.
Receiving a count value from the data register as a register element designation signal, sequentially selecting the register elements of the data register means and connecting to the internal data bus,
Multi-port random access memory. 2. The counting circuit according to claim 1 , wherein each of the counting circuits has a clock input, and the clock input is connected to the clock input.
The logic state of the output signal
A plurality of flip-flop circuits, and a first stage flip-flop of the plurality of flip-flop circuits.
Compatible with flip-flop circuits excluding flip-flop circuits
A clock signal and a preceding flip-flop
Circuit corresponding to all output signals and flip-flops
Output clocking signal to clock input of clock circuit
The first stage flip-flop, comprising:
The clock signal is clocked to the clock input of the
Flip-flop provided as a final signal
The output signal of the circuit is
2. The multi-port random access memory of claim 1, wherein said memory is provided to said offset counter . 3. The count circuit according to claim 1, wherein the count circuit includes an internal address signal.
Initial value is set by And the offset counter is
The initial value is set by the data from the RAM port.
The multi-port random according to claim 1 or 2,
Access memory.