JP3170764B2 - Selective growth method of silicon-based thin film, method of manufacturing top gate type and bottom gate type thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for selectively growing a silicon-based thin film and, more particularly, to depositing a silicon-based thin film only on a silicon-based material on a substrate having a silicon-based material and an oxide-based transparent conductor exposed on the surface. The present invention relates to a method for selectively growing a silicon-based thin film that can be made.

[0002]

2. Description of the Related Art In recent years, a vapor phase selective growth method capable of selectively exposing two or more types of substances to a substrate surface and depositing a desired substance only on a specific substance has been proposed. Generally, it is performed under a relatively high temperature process condition of about 600 ° C. by using a thermal vapor deposition method (hereinafter, referred to as a thermal CVD method).

For example, on a silicon substrate on which an insulating film such as silicon oxide is selectively formed, a method of depositing a silicon film only on a portion where silicon is exposed, or a method of forming a silicon oxide film and a silicon nitride film in a desired pattern. There is known a method of depositing a silicon film only on a silicon nitride film formed on a substrate.

[0004] GNPersons et al., Appl. Phys.
At t.59, 2546 (1991), under a relatively low temperature (about 300 ° C.) process condition using plasma CVD, a silicon thin film was formed only on a metal such as a silicon oxide film or molybdenum formed on a glass substrate. Shows a method for selectively growing.

This is based on the fact that silicon is more likely to grow on a metal having higher conductivity than an insulator such as silicon oxide, and the time required for forming nuclei required for growth is shorter. Specifically, by repeating the growth of silicon nuclei and the removal of silicon nuclei on the insulating film by hydrogen plasma, a silicon film can be grown only on metal.

Although GNPersons et al. Suggest the possibility of selective growth among other substances by this method,
The specific conditions are not shown. On the other hand, in a semiconductor element, a large step is generated because the patterned insulating film or conductive film overlaps many times in the formation process, and there is a problem such as division or inhomogeneity of the thin film at the step. .

FIG. 10 shows an example of a thin film transistor (TFT) used as a conventional active element for driving a liquid crystal display. An SiN film 52 is formed on a glass substrate 51. At predetermined positions on the SiN film 52, indium tin oxide films (ITO films) 53 are formed as source and drain electrodes at predetermined intervals. IT
On the upper surface of the O film 53, an n ⁺ -type hydrogenated amorphous silicon layer (n ⁺ a-S
i: H) 54 is formed.

A hydrogen-added amorphous silicon (a-Si: H) layer 55 serving as an operating semiconductor layer is formed from above the ITO source electrode to above the ITO drain electrode, covering the surface of the SiN film 52 between the source and drain electrodes. ing.
An SiN film 56 is formed so as to cover the source and drain electrodes 53, the a-Si: H layer 55, and the surrounding SiN film 52.

A gate electrode 57 of aluminum or the like is formed on the surface of the SiN film 56 on the channel region between the source electrode and the drain electrode. In the structure illustrated in FIG. 10A, the a-Si: H layer 55 absorbs backlight light emitted from the glass substrate 51 side. Thus, the off-state current of the TFT increases. In order to suppress an increase in off-state current, the thickness of the a-Si: H layer 55 may be reduced.

[0010]

FIG. 10B is a diagram showing a-
An example in which the thickness of the Si: H layer 55 is reduced is shown. a-
When the thickness of the Si: H layer 55 is reduced, the ITO film 53 and S
The a-Si: H layer is divided 58 at a step portion from the iN film 52. For this reason, conduction between the source and drain electrodes is not ensured, which causes a device failure.

In order to solve this problem, it is effective to fill a step between the source and drain electrodes with an insulating film to flatten the surface. However, in the method of flattening the surface by depositing a thin film over the entire surface of the substrate and then etching only the projections using photolithography, it is difficult to planarize the surface with good controllability, and the number of steps increases. There is also a problem.

In order to embed an insulating film in a step without increasing the number of steps, a selective growth method may be used. However, the selective growth method by the thermal CVD method generally requires a high-temperature process of about 600 ° C. for that reason,
It cannot be used when an oxide such as ITO, a low melting point metal such as aluminum, or a substrate having a low softening point such as soda glass is used.

Further, even in the selective growth method using the plasma CVD method, a film forming process at about 250 to 300 ° C. is required. In addition, it is possible to selectively grow an amorphous or crystalline silicon film having high conductivity by these techniques, and it is not possible to selectively grow an insulating film.

An object of the present invention is to provide a selective growth method capable of selectively growing a silicon-based thin film at a relatively low temperature. Another object of the present invention is to provide a selective growth method capable of selectively growing a silicon-based insulating film.

[0015]

According to the method for selectively growing a silicon-based thin film of the present invention, an undersubstrate having a surface of a semiconductor or insulator containing silicon and a surface of an oxide-based transparent conductor is provided.
A growth nucleus forming step of exposing the substrate to a plasma containing a silane-based gas at a substrate temperature of 200 ° C. or less to form a silicon growth nucleus on the surface; and subjecting the insulating substrate to a plasma of hydrogen or an inert gas at a substrate temperature of 200 ° C. or less. A growth nucleus removing step of exposing the silicon growth nuclei formed on the semiconductor or insulator surface, leaving at least a part of the silicon growth nuclei formed on the oxide-based transparent conductor surface, A growth nucleus forming step and a growth nucleus removing step are alternately repeated a predetermined number of times to form a silicon-based thin film forming step only on the surface of the semiconductor or insulator containing silicon.

In the silicon-based thin film forming step, after the growth nucleus removing step, the substrate is exposed to a plasma containing at least one element of oxygen, nitrogen, carbon, and germanium, and the silicon growth nucleus is removed. A reaction step of reacting at least one element of oxygen, nitrogen, carbon and germanium to form at least one silicon compound of silicon oxide, silicon nitride, silicon carbide and silicon germanium. .

The undersubstrate is formed by patterning an oxide-based transparent conductive film on the surface of an insulator containing silicon. In the step of forming a silicon-based thin film, the upper surface of the silicon-based thin film is formed of the oxide-based thin film. The silicon-based thin film may be formed until it is substantially flush with the upper surface of the transparent conductive film.

According to the method of manufacturing a top gate type thin film transistor of the present invention, a source electrode and a drain electrode are formed at predetermined intervals on an insulating substrate having a silicon-based insulator surface, and the source electrode and the drain electrode are formed on the source electrode and the drain electrode. In a method for manufacturing a top gate type thin film transistor in which an operating semiconductor layer continuously formed over a straddle and a gate insulating film and a gate electrode formed on the operating semiconductor layer in this order, a predetermined Forming a source electrode and a drain electrode each having an oxide-based transparent conductor surface on the upper surface thereof at an interval of;
Exposing the substrate to a plasma containing silane or disilane at a temperature of not more than 200 ° C. to form silicon growth nuclei on the surface, and exposing the substrate to a plasma of hydrogen or an inert gas at a substrate temperature of 200 ° C. or less; While removing all the silicon growth nuclei formed on the surface of the oxide-based transparent conductor of the source electrode and the drain electrode, on the region where the source electrode and the drain electrode are not formed on the insulating substrate, the silicon A growth nucleus removing step of leaving at least a part of the growth nucleus; and exposing the substrate to a plasma containing at least one element of oxygen, nitrogen, carbon, and germanium, wherein the silicon growth nucleus, oxygen, nitrogen, Reacting with at least one element of carbon and germanium to form silicon oxide, silicon nitride, silicon carbide Forming a silicon compound thin film by repeating a reaction step of forming at least one silicon compound of silicon and silicon germanium, the growth nucleus forming step, the growth nucleus removing step, and the reaction step a predetermined number of times in this order. Forming a silicon compound thin film on the silicon-based insulator surface until the upper surface of the silicon compound thin film is substantially flush with the upper surfaces of the source electrode and the drain electrode.

According to the method of manufacturing a bottom gate type thin film transistor of the present invention, a gate electrode formed by patterning on an insulating substrate having a silicon-based insulator surface, and a gate insulating film and an active semiconductor layer are formed on the gate electrode. In a method for manufacturing a bottom-gate thin film transistor including a source electrode and a drain electrode formed in this order and formed on the operating semiconductor layer so as to sandwich the gate electrode, an oxide-based thin film may be formed on the insulating substrate. A step of patterning and forming a gate electrode having a transparent conductor surface, and a step of exposing the substrate to a plasma containing silane or disilane at a substrate temperature of 200 ° C. or lower to form silicon growth nuclei on the surface And the substrate is heated to a substrate temperature of 20.
Exposure to a plasma of hydrogen or an inert gas at 0 ° C. or lower to remove all the silicon growth nuclei formed on the surface of the oxide-based transparent conductor of the gate electrode, and to form the gate electrode on the insulating substrate. A growth nucleus removing step of leaving at least a portion of the silicon growth nuclei on the region not subjected to the exposure, exposing the substrate to a plasma containing oxygen or nitrogen, and reacting the silicon growth nucleus with oxygen or nitrogen. Forming a silicon oxide film or a silicon nitride film by repeating a reaction step of forming silicon oxide or silicon nitride, the growth nucleus forming step, the growth nucleus removing step, and the reaction step a predetermined number of times in this order. , On the surface of the silicon-based insulator until the upper surface of the silicon oxide film or the silicon nitride film is substantially flush with the upper surface of the gate electrode. And forming a silicon film or a silicon nitride film.

[0020]

By exposing a base substrate having a semiconductor or insulator surface containing silicon and an oxide-based transparent conductor surface to a plasma containing a silane-based gas such as silane or disilane at a substrate temperature of 200 ° C. or lower, Many silicon growth nuclei can be formed on the surface of a semiconductor or insulator containing silicon without being formed on the surface of the oxide-based transparent conductor.

By exposing the substrate on which the silicon growth nuclei have been formed to plasma of hydrogen or an inert gas, the oxide-based nuclei formed on the surface of the semiconductor containing silicon or the insulator are left. All silicon growth nuclei formed on the surface of the transparent conductor can be removed.

By repeating this step, a silicon thin film can be selectively grown only on the surface of a semiconductor or insulator containing silicon. After removing all silicon growth nuclei formed on the surface of the oxide-based transparent conductor, the underlying substrate is exposed to a plasma containing at least one element of oxygen, nitrogen, carbon and germanium,
Reacting the silicon growth nucleus with at least one element of oxygen, nitrogen, carbon and germanium;
By forming at least one kind of silicon compound among silicon oxide, silicon nitride, silicon carbide, and silicon germanium, the silicon compound can be selectively formed only on the surface of a semiconductor or insulator containing silicon.

In this manner, a silicon-based thin film can be selectively grown only on the surface of a semiconductor or insulator containing silicon. According to this method, the surface of the insulating substrate can be planarized by filling the steps on the surface of the insulating substrate with a silicon-based thin film.

In the manufacturing process of the top gate type thin film transistor, the recess between the source electrode and the drain electrode formed below is filled with a silicon-based thin film to planarize the surface, and an operating semiconductor layer and the like are formed thereon. It is possible to prevent separation due to a step and obtain a uniform operating semiconductor layer. The same effect can be obtained by embedding the gate electrode in a bottom-gate thin film transistor in which the gate electrode is formed below.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. FIG. 1A shows a silicon layer deposition step by a plasma CVD method. An SiN film 2 is formed on an insulating substrate 1 such as quartz, and ITO is partially formed on the SiN film 2.
A base substrate on which the film 3 is formed is prepared. Although silicon nitride has a stoichiometric composition of Si ₃ N _{4, the} composition is changed depending on the film forming conditions, and thus is described as SiN.

A growth nucleus 4 necessary for growing silicon is formed on the surfaces of the SiN film 2 and the ITO film 3 by using a parallel plate type plasma CVD apparatus. The growth nuclei are formed by a flow rate of silane (SiH ₄ ) of 25 sccm and a flow rate of hydrogen of 550.
The silane plasma 5 was generated under the conditions of sccm, a pressure of 0.6 Torr, and an RF power of 200 W.

Under these conditions, the speed at which the growth nuclei 4 are formed on the surface of the SiN film 2 is faster than the speed at which the growth nuclei 4 are formed on the surface of the ITO film 3. This step is performed by forming a growth nucleus 4 on the surface of the ITO film 3.
Until it starts to form. Under the above conditions, about 5-1
It is about 0 seconds.

FIG. 1B shows a step of etching the growth nucleus by the hydrogen plasma 6. The etching conditions were a hydrogen flow rate of 550 sccm, a pressure of 0.6 Torr, and an RF power of 30.
0W.

This process is performed until the growth nuclei 4 formed on the surface of the ITO film 3 are completely removed. Under the above conditions, it is about 50 to 100 seconds. At this time, the SiN film 2
Although a part of the growth nuclei 4 formed on the surface is also removed at the same time, since more growth nuclei are formed than on the surface of the ITO film 3, even after removing all the growth nuclei on the surface of the ITO film 3, the Si is removed.
Growth nuclei 4 remain on the surface of the N film 2.

FIG. 2 shows the change in the thickness of the deposited silicon layer with respect to the substrate temperature when the above-mentioned silicon layer deposition step and etching step are alternately repeated 100 times. The horizontal axis indicates the substrate temperature, and the vertical axis indicates the thickness of the deposited silicon layer. Represents the thickness of the silicon layer on the surface of the SiN film 2;

On the surface of the SiN film, as the substrate temperature increases from 100 ° C. to 400 ° C., the film thickness slightly decreases from about 620 ° to about 570 °. On the ITO film, a silicon layer is scarcely formed at a substrate temperature of 200 ° C. or lower, and rapidly increases at a temperature of 200 ° C. or higher, and the silicon layer thickness becomes about 260 ° at a substrate temperature of about 380 ° C. .

Therefore, if the substrate temperature is 200 ° C. or lower, a silicon layer is selectively formed only on the SiN film 2. However, when the substrate temperature is 200 ° C. or higher, a silicon layer grows on the surface of the ITO film 3 and the selectivity is lost.

This is because when the substrate temperature is 200 ° C. or higher, I
It is considered that the TO film was reduced by the hydrogen plasma, and metal indium appeared on the surface. This is because silicon generally easily grows on metal, and a silicon layer is formed on the surface of the ITO film whose surface is made of metal indium.

From this embodiment, it is possible to form a silicon layer only on the surface of the SiN film by setting the substrate temperature to 200 ° C. or less on the surface of the substrate formed of the ITO film and the SiN film.

Next, a second embodiment of the present invention will be described. The second embodiment includes a nitridation step of nitriding a growth nucleus of silicon formed on the surface of the SiN film after the etching step (FIG. 1B) of the first embodiment.

FIG. 1C shows a nitriding step. FIG.
When the substrate after the etching step (B) is exposed to nitrogen plasma, the growth nucleus 4 of silicon is nitrided because its thickness is sufficiently small, and becomes a SiN film 8. This state is shown in FIG.
Is equivalent to the substrate state before the start of the step. That is, the silicon-based material can be grown under the same conditions.

The nitriding was performed at a substrate temperature of 100 ° C., a nitrogen gas flow rate of 60 sccm, a hydrogen gas flow rate of 100 sccm, a pressure of 0.6 Torr, and an RF power of 400 W. By repeating the silicon layer depositing step, the etching step, and the nitriding step of the first embodiment as many times as necessary, the SiN film 2 is formed.
It is possible to selectively grow a SiN film having a desired thickness only on the surface.

In the above embodiment, an example was described in which the SiN film was selectively grown by using nitrogen plasma. However, other silicon compounds can be formed by using other than nitrogen plasma. For example, an SiO ₂ film can be selectively grown by using oxygen plasma, a SiC film can be selectively grown by using carbide plasma such as methane, and a SiGe film can be selectively grown by using plasma containing germanium.

In the above embodiment, an example was described in which silane (SiH ₄ ) was used as a plasma source in the silicon layer deposition step, but disilane (Si ₂ H ₆ ) was used.
Other silane compounds may be used.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 3 (A) shows S by the conventional method.
The case where an aluminum (Al) wiring is formed so as to be orthogonal to the ITO wiring formed in a stripe shape on the iN film is shown. An SiN film 12 is formed on an insulating substrate 11, and on the SiN film 12, an ITO wiring 13 having a thickness of about 2000 ° in a direction perpendicular to the paper is formed at a predetermined interval.

On the SiN film 12 and the ITO wiring 13, an SiN film 14 having a thickness of about 1000 ° is formed as an interlayer insulating film, and is formed on the SiN film 14 in a direction parallel to the plane of FIG.
An Al wiring 15 having a thickness of 0 ° is formed.

In this case, since the step between the surface of the SiN film 12 and the upper surface of the ITO wiring 13 is large, the Si
In some cases, division 16 occurs at the step portion in the N film 14.
Similar division occurs in the Al wiring 15 formed thereon. Therefore, a conduction failure of the Al wiring 15 or an insulation failure between the Al wiring 15 and the ITO wiring 13 occurs.

FIG. 3B shows a third embodiment of the present invention for solving the above problem. I similar to that of FIG.
After the formation of the TO wiring 13, the selective growth method according to the second embodiment is used to form a SiN film on the exposed portion of the SiN film 12.
A film 17 is formed. The upper surface of the SiN film 17 is the ITO wiring 1
3 is formed until the same height as the upper surface of the SiN film 3.
Flatten the surface.

An interlayer insulating film 14 and an Al wiring 15 are formed on the flattened surface. By flattening the substrate surface before forming the interlayer insulating film and the wiring,
The occurrence of division can be prevented.

Next, a fourth embodiment of the present invention will be described with reference to FIG. This embodiment relates to a method of manufacturing a top gate thin film transistor (TFT) using an ITO film for source and drain electrodes.

FIG. 4A shows a step of forming source and drain electrodes. SiN film 22 on insulating substrate 21
Are formed. After forming an ITO film on the SiN film 22, patterning by photolithography
ITO source electrodes 23a and 23
The TO drain electrode 23b is formed.

FIG. 4B shows a step of selectively growing a SiN film. After the formation of the ITO source electrode 23a and the ITO drain electrode 23b, the selective growth method according to the second embodiment is used to remove SiN only in the portion where the SiN film 22 is exposed.
An N film 24 is formed. The upper surface of the SiN film 24 is formed to be several tens of degrees higher than the upper surfaces of the source and drain electrodes 23a and 23b.

FIG. 4C shows n ⁺ as a contact layer.
4 shows a step of forming a layer. On the ITO source electrode 23a and the ITO drain electrode 23b, n ⁺ a-S
i: H films 25a and 25b are formed such that the upper surfaces thereof are at the same height as the upper surface of SiN film 24. As a forming method, an n ⁺ a-Si film may be formed on the entire surface and patterned by photolithography, or may be formed by selective growth under appropriate film forming conditions.

As described above, the n ⁺ a-Si: H film 25a
By making the upper surface of the upper surface 25b and the upper surface of the SiN film 24 uniform, the surface can be flattened. FIG. 4 (D)
Shows a step of forming an active semiconductor layer, a gate insulating layer, and a gate electrode.

An a-Si: H layer is formed as a working semiconductor layer by CVD on the substrate whose surface is flattened as shown in FIG. It is selectively etched by photolithography, and from the upper surface of the source electrode contact layer 25a to the drain electrode contact layer 25b.
, The n ⁺ a-Si: H layer is continuously left so as to cover the upper surface of the SiN film 24 therebetween.
To form

Next, SiN is formed as a gate insulating layer so as to cover the contact layers 25a and 25b and the operating semiconductor layer 26.
A film 27 is formed. Further, a gate electrode 28 of Al or the like is formed on the surface of the SiN film 27 above the operation semiconductor layer 26.

As described above, before forming the operating semiconductor layer 26, the source electrode 23a, the drain electrode 23b and the SiN
By filling the step with the film 22 with the SiN film 24 and flattening the surface, the working semiconductor layer 26 can be formed uniformly without being divided.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIGS. 5A and 5B show steps similar to the steps shown in FIGS. 4A and 4B in the fourth embodiment, respectively. However, S in FIG.
In the step of selectively growing the iN film 24, the SiN film 2
4 is different in that the upper surface is formed so as to have the same height as the upper surfaces of the source electrode 23a and the drain electrode 23b.

FIG. 5C shows a step of attaching phosphorus (P) to the surfaces of the source electrode 23a and the drain electrode 23b. When the substrate shown in FIG. 5B is exposed to phosphine (PH ₃ ) plasma, the ITO source electrodes 23a and I
Phosphorus adheres only to the surface of the TO drain electrode 23b.
In this step, the substrate temperature is 120 ° C., and the PH ₃ flow rate is
m, hydrogen flow rate 200 sccm, pressure 0.2 Torr, R
The test was performed under the condition of F power of 100 w.

FIG. 5D is a view showing the state of FIG.
3D shows a step of forming an a-Si: H operation layer similar to that of FIG.
Since phosphorus is attached to the surfaces of the source electrode 23a and the drain electrode 23b, when the a-Si: H semiconductor layer 26 is formed thereon, the vicinity of the ITO source electrode 23a and the ITO drain electrode 23b of the active semiconductor layer 26 , N ⁺ type. Therefore, it is not necessary to form the contact layer 25a or 25b as shown in the fourth embodiment.

As in the fourth or fifth embodiment, the ITO
By selectively growing the SiN film to a desired thickness so as to fill the step between the film and the SiN film, it is possible to prevent the operating semiconductor layer formed thereon from being divided by the step.

Next, a sixth embodiment will be described with reference to FIG. This embodiment uses a metal electrode such as chromium (Cr) instead of the ITO electrode in the fourth embodiment shown in FIG.

FIG. 6A shows a step of forming source and drain electrodes. SiN film 2 on insulating substrate 21
2 are formed. A Cr film and an ITO film are continuously formed on the SiN film 22 by a sputtering method or the like. After that, patterning is performed by photolithography, and the ITO films 31a and 31b are left on the upper surface for about 2000 °.
Then, a Cr source electrode 30a and a Cr drain electrode 30b having a thickness of 10 nm are formed.

FIG. 6B shows a step of selectively growing a SiN film. S using the selective growth method according to the second embodiment
The SiN film 24 is formed only on the portion where the iN film 22 is exposed. At this time, since the ITO films 31a and 31b are formed on the Cr source electrode 30a and the Cr drain electrode 30b, no SiN film is formed thereon.

The upper surface of the SiN film 24 is
1b is formed so as to have the same height as the upper surface. FIG.
(C) shows a step of removing the ITO films 31a and 31b. By removing the ITO films 31a and 31b, the SiN film 24, the gate electrode 30a and the drain electrode 3 are removed.
A step corresponding to the thickness of the ITO films 31a and 31b occurs at the boundary with 0b.

FIG. 6D shows contact layers 25a and 25a.
b, a step of forming the operating semiconductor layer 26, the gate insulating film 27, and the gate electrode 28. Cr source electrode 30a,
N ⁺ a as a contact layer on the Cr drain electrode 30b;
-Si: H films 25a and 25b are formed. At this time, a
-Si: The upper surfaces of the H films 25a and 25b are formed so as to have the same height as the upper surface of the SiN film 24.

Then, FIG. 4D in the fourth embodiment.
The a-Si: H semiconductor layer 26, the SiN film 27 as a gate insulating film, and the gate electrode 28 are formed in the same manner as in the process shown in FIG. As described above, even when the metal electrode is used for the source and the drain, the fourth or fifth metal layer using the ITO electrode can be formed by forming the ITO film on the metal electrode.
The SiN film can be selectively grown in the same manner as in the embodiment, and the step can be eliminated.

Next, a seventh embodiment will be described with reference to FIG. FIG. 7A shows a case where the SiN film 24 of the fourth embodiment shown in FIG. 4D is replaced with an a-SiC film 32.

In the step of forming the SiN film 24 shown in FIG. 4B, the a-SiC film can be selectively grown by generating plasma of a carbide such as methane instead of nitrogen plasma.

Since a-SiC is not an insulator, it is necessary to electrically isolate adjacent TFTs. Therefore, it is necessary to remove the SiC film 32 formed outside the source electrode 23a and the drain electrode 23b.

FIG. 7B shows a structure of a TFT in which adjacent TFTs are electrically separated. Gate electrode 2 of Al or the like
8 as a mask, the SiN film 27, the SiC film 32, and S
By selectively etching the iN film 22, it is possible to separate adjacent TFTs.

As described above, by filling the recess between the source electrode 23a and the drain electrode 23b with a-SiC, there are the following merits. In order to suppress an increase in the off current of the TFT due to the influence of the backlight or the like, a-S
It is preferable to reduce the thickness of the i: H operating semiconductor layer 26. However, if the thickness is reduced, it becomes difficult to obtain a sufficient on-current. As shown in FIG. 7B, the source electrode 23a
By filling the space between the drain electrodes 23b with the a-SiC 32, a part of the on-current flows through the a-SiC 32, and the decrease of the on-current can be compensated.

Since a-SiC has a larger band gap than a-Si: H, increase in off-state current due to light absorption is small. Thus, it is possible to compensate for the decrease in the on-current while suppressing the increase in the off-current.

The case where the selective growth method of the present invention is applied to a top gate type TFT has been described above. Next, a case where the selective growth method is applied to a bottom gate type TFT will be described. An eighth embodiment of the present invention will be described with reference to FIG.

FIG. 8A shows a step of forming a gate electrode. The SiN film 42 is formed on the insulating substrate 41.
A ZnO film is formed on the SiN film 42 and is patterned by photolithography.
The gate electrode 43 is formed.

FIG. 8B shows a step of selectively growing a SiN film. After the formation of the ZnO gate electrode 43, the SiN film 44 is selectively grown on the exposed portion of the SiN film 42 by the selective growth method according to the second embodiment.

In the second embodiment, the case where the SiN film is selectively grown on the SiN film of the substrate in which the ITO film is partially formed on the SiN film has been described. Alternatively, selective growth can also be performed by using a ZnO film instead.

The upper surface of the SiN film 44 is a ZnO film 43
Is formed so as to have the same height as the upper surface of. in this way,
By selectively growing the SiN film, a flat surface including the upper surface of the ZnO gate electrode 43 can be obtained.

FIG. 8C shows a step of further forming a gate insulating film, an operating semiconductor layer, and source and drain electrodes. On the ZnO gate electrode 43 and the SiN film 44, a SiN film 45 having a thickness of about 1000 ° is formed. Further, on the surface of the SiN film 45 above the gate electrode 43, an a-Si: H film 46 having a thickness of about 200.degree.

N ⁺ a-Si: H layers 47a and 47b as contact layers are formed on both ends of the a-Si: H film 46, respectively.
To form a source electrode 48a and a drain electrode 48b. As described above, in order to form a flat surface including the upper surface of the ZnO gate electrode 43, the SiN film 45, a-S
The i: H film 46 can be formed uniformly without being divided.

Next, a ninth embodiment of the present invention will be described with reference to FIG. The structure of the TFT is the same as that of the eighth embodiment shown in FIG. 8C, except that a metal film such as Al is used instead of a ZnO film as a gate electrode.

FIG. 9A shows a step of forming a gate electrode.
Is shown. The SiN film 42 is formed on the insulating substrate 41.
Al and S are formed on the SiN film 42 by sputtering or the like.
nO _TwoAfter continuous film formation, photolithography
After patterning, SnO_TwoFilm 50 was formed
An Al gate electrode 49 having a thickness of about 2000 ° is formed.

FIG. 9B shows a step of selectively growing a SiN film. In the second embodiment, after the Al gate electrode 49 having the SnO ₂ film 50 formed on the upper surface is formed, the SiN film 44 is selectively grown on the portion where the SiN film 42 is exposed by the selective growth method according to the second embodiment. Although the case where the SiN film is selectively grown on the SiN film of the substrate in which the ITO film is partially formed on the SiN film has been described, the SnO ₂ film is used instead of the ITO film as in this embodiment. Can also be selectively grown.

The SiN film 44 is formed such that its upper surface is at the same height as the upper surface of the Al gate electrode 49. Subsequently, by removing the SnO ₂ film 50 on the Al gate electrode 49, a flat surface including the upper surface of the Al gate electrode 49 can be obtained.

FIG. 9C is a circuit diagram of the eighth embodiment.
Steps similar to those of FIG. As described above, by covering the upper surface of the gate electrode with the SnO ₂ film or the like, the same effect as in the eighth embodiment can be obtained even when a metal electrode is used as the gate electrode.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0082]

As described above, according to the present invention,
A silicon-based thin film can be selectively deposited only on a silicon-based semiconductor or insulator surface of a substrate in which an oxide-based transparent conductive film is formed on a silicon-based semiconductor or insulator surface. By applying this selective growth method when manufacturing a thin film transistor, the substrate surface can be flattened without going through complicated steps such as photolithography and etch back.

Thus, the productivity and device characteristics of the thin film transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate for explaining a silicon-based thin film selective growth method according to first and second embodiments of the present invention.

FIG. 2 is a graph showing a change in a silicon film thickness with respect to a substrate temperature grown according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a substrate for explaining the effect of a silicon-based thin film selective growth method according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of a substrate for explaining a method of manufacturing a top-gate thin film transistor according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view of a substrate for explaining a method of manufacturing a top-gate thin film transistor according to a fifth embodiment of the present invention.

FIG. 6 is a cross-sectional view of a substrate for explaining a method of manufacturing a top-gate thin film transistor according to a sixth embodiment of the present invention.

FIG. 7 is a cross-sectional view of a substrate for explaining a method of manufacturing a top-gate thin film transistor according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view of a substrate for explaining a method of manufacturing a bottom-gate thin film transistor according to an eighth embodiment of the present invention.

FIG. 9 is a cross-sectional view of a substrate for explaining a method of manufacturing a bottom-gate thin film transistor according to a ninth embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional top-gate thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 SiN film 3 ITO film 4 Si growth nucleus 5 Silane plasma 6 Hydrogen plasma 7 Nitrogen plasma 8 SiN film 11 Insulating substrate 12, 14 SiN film 13 ITO wiring 15 Aluminum wiring 16 Divided 17 SiN film 21 Insulating substrate Reference Signs List 22 SiN film 23 a ITO source electrode 23 b ITO drain electrode 24 SiN film 25 a, 25 b n ⁺ a-Si: H contact layer 26 a-Si: H semiconductor layer 27 SiN film 28 gate electrode 29 phosphorus 30 a Cr source electrode 30 b Cr drain electrode 31a, 31b ITO film 32 SiC film 41 Insulating substrate 42 SiN film 43 ZnO gate electrode 44, 45 SiN film 46 a-Si: H semiconductor layer 47a, 47bn ⁺ a-Si: H contact layer 48a Source electrode 48b Drain electrode 49 Alge Gate electrode 50 SnO ₂ film 51 Glass substrate 52, 56 SiN film 53 ITO film 54 n ⁺ a-Si: H layer 55 a-Si: H layer 57 Gate electrode 58 Divided

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Yanai 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Fumiyo Takeuchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-60-249334 (JP, A) JP-A-62-181711 (JP, A) JP-A-3-19218 (JP, A) JP-A-5-32485 (JP, A) Hei 5-275335 (JP, A) JP-A-7-235502 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/205 H01L 21/318 H01L 21/336

Claims (5)

(57) [Claims] 1. An undersubstrate having a semiconductor or insulator surface containing silicon and an oxide-based transparent conductor surface,
A growth nucleus forming step of exposing to a plasma containing a silane-based gas at a substrate temperature of 200 ° C. or less to form a silicon growth nucleus on the surface; and a plasma of hydrogen or an inert gas at a substrate temperature of 200 ° C. or less. A growth nucleus removal step of exposing the silicon growth nuclei formed on the semiconductor or insulator surface to at least partially leave the silicon growth nuclei formed on the oxide-based transparent conductor surface; A silicon-based thin film selective growth method comprising: a silicon-based thin film forming step of forming a silicon-based thin film only on the surface of a semiconductor or insulator containing silicon by repeating the growth nucleus forming step and the growth nucleus removing step alternately a predetermined number of times. . 2. The method according to claim 2, wherein, after the growth nucleus removing step, the substrate is exposed to a plasma containing at least one element of oxygen, nitrogen, carbon, and germanium. A reaction step of reacting the nucleus with at least one element of oxygen, nitrogen, carbon, and germanium to form at least one silicon compound of silicon oxide, silicon nitride, silicon carbide, and silicon germanium. The method for selectively growing a silicon-based thin film according to claim 1. 3. The undersubstrate is formed by patterning an oxide-based transparent conductive film on the surface of an insulator containing silicon. In the silicon-based thin film forming step, the upper surface of the silicon-based thin film is 3. The method according to claim 2, wherein the silicon-based thin film is formed until it is substantially flush with the upper surface of the oxide-based transparent conductive film. 4. A source electrode and a drain electrode formed at predetermined intervals on an insulating substrate having a silicon-based insulator surface, and are formed continuously over the source electrode and the drain electrode. In a method for manufacturing a top gate type thin film transistor in which a working semiconductor layer and a gate insulating film and a gate electrode are formed in this order on the working semiconductor layer, an oxide-based transparent film is formed on the upper surface at a predetermined interval on the insulating substrate. A step of forming a source electrode and a drain electrode having a conductor surface; and a step of exposing the substrate to a plasma containing silane or disilane at a substrate temperature of 200 ° C. or lower to form a silicon nucleus on the surface. Exposing the substrate to a plasma of hydrogen or an inert gas at a substrate temperature of 200 ° C. or less to oxidize the source electrode and the drain electrode; Removing all the silicon growth nuclei formed on the surface of the material-based transparent conductor, and at least a part of the silicon growth nuclei on a region where the source electrode and the drain electrode are not formed on the insulating substrate. Exposing the substrate to a plasma containing at least one element of oxygen, nitrogen, carbon and germanium, and removing the silicon growth nucleus and at least one of oxygen, nitrogen, carbon and germanium; A reaction step of reacting with at least one element to form at least one silicon compound of silicon oxide, silicon nitride, silicon carbide, and silicon germanium; the growth nucleus forming step; and the growth nucleus removing step; The reaction step is repeated a predetermined number of times in this order to form a silicon compound thin film. A top gate type thin film transistor manufacturing method the upper surface of the compound thin film and a step of forming a silicon compound thin film on the silicon-based insulator surface until approximately flush with the upper surface of the source electrode and the drain electrode. 5. A gate electrode formed by patterning on an insulating substrate having a silicon-based insulator surface, and a gate insulating film and an operating semiconductor layer are formed on the gate electrode in this order. In a method of manufacturing a bottom gate type thin film transistor including a source electrode and a drain electrode formed so as to sandwich the gate electrode, a gate electrode having an oxide-based transparent conductor surface on an upper surface is patterned on the insulating substrate. Forming the substrate; exposing the substrate to a plasma containing silane or disilane at a substrate temperature of 200 ° C. or less to form a silicon growth nucleus on the surface; and forming the substrate at a substrate temperature of 200 ° C. The silicon component formed on the surface of the oxide-based transparent conductor of the gate electrode is exposed to a plasma of hydrogen or an inert gas below. A growth nucleus removing step of removing all long nuclei and leaving at least a part of the silicon growth nuclei on a region where the gate electrode is not formed on the insulating substrate; and Exposing the silicon growth nucleus to oxygen or nitrogen to form silicon oxide or silicon nitride; exposing the silicon growth nucleus to silicon or silicon nitride; the growth nucleus forming step; the growth nucleus removing step; Is repeated a predetermined number of times in this order to form a silicon oxide film or a silicon nitride film, and the silicon oxide film or the silicon nitride film Forming a silicon oxide film or a silicon nitride film.