JP3160960B2 - Semiconductor device and method of forming contact hole - Google Patents
Semiconductor device and method of forming contact holeInfo
- Publication number
- JP3160960B2 JP3160960B2 JP27816791A JP27816791A JP3160960B2 JP 3160960 B2 JP3160960 B2 JP 3160960B2 JP 27816791 A JP27816791 A JP 27816791A JP 27816791 A JP27816791 A JP 27816791A JP 3160960 B2 JP3160960 B2 JP 3160960B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring film
- contact hole
- lower wiring
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の多層配線構
造におけるコンタクトホールの形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a multilayer wiring structure of a semiconductor device.
【０００２】近年，半導体装置の微細化，高速化にとも
ない，多層配線構造が重要視され，コンタクトホールの
高い信頼性が要求されている。このため，コンタクトホ
ール内の配線のくびれを抑え，コンタクトホール内の下
層配線膜と上層線線膜のコンタクト面積を増やす必要が
ある。In recent years, with miniaturization and speeding up of semiconductor devices, multilayer wiring structures have been regarded as important, and high reliability of contact holes is required. For this reason, it is necessary to suppress the constriction of the wiring in the contact hole and increase the contact area between the lower wiring film and the upper line film in the contact hole.
【０００３】[0003]
【従来の技術】図３は従来例の説明図である。図におい
て，19は下層絶縁膜, 20は下層配線膜, 21は上層絶縁
膜, 22はコンタクトホール, 23は上層配線膜である。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 19 is a lower insulating film, 20 is a lower wiring film, 21 is an upper insulating film, 22 is a contact hole, and 23 is an upper wiring film.
【０００４】従来の多層配線においては，図３に断面図
で示すように，上層配線膜21のカバレッジを向上させる
ため，コンタクトホール22の形成時に，先ず，上層絶縁
膜21の上半分に等方性エッチングを行ない，断面がテー
パー状のホールを形成し, 続いて，上層絶縁膜21の下半
分に異方性エッチングを行ない，断面が垂直のホールを
下層配線膜20が露出するまで行ない, いわゆる, コンタ
クトホール22がワイングラス形状になるエッチング方法
を行っていた。In the conventional multi-layer wiring, as shown in a sectional view of FIG. 3, in order to improve the coverage of the upper wiring film 21, when forming the contact hole 22, first, the upper half of the upper insulating film 21 is isotropically formed. Etching is performed to form a hole having a tapered cross section. Subsequently, anisotropic etching is performed on the lower half of the upper insulating film 21, and a hole having a vertical cross section is formed until the lower wiring film 20 is exposed. However, the etching method in which the contact hole 22 becomes a wine glass shape is performed.
【０００５】ところが，このワイングラス形状では，上
層配線膜23と下層配線膜20の接触面積が小さく，またコ
ンタクトホール22下部の異方性エッチング部分におい
て, 図にＢで示すくびれ部分で上層配線膜23の膜厚が，
表面Ａの部分の半分以下と，薄くなっていた。However, in this wine glass shape, the contact area between the upper wiring film 23 and the lower wiring film 20 is small, and in the anisotropically etched portion below the contact hole 22, the upper wiring film is formed by a narrow portion shown in FIG. 23 film thickness,
The thickness was less than half of the surface A portion.
【０００６】[0006]
【発明が解決しようとする課題】従って，コンタクトホ
ール22内の上層配線膜23のカバレッジが悪くなったり，
上層配線膜23と下層配線膜19のコンタクト面積が小さく
なったりして，配線膜のコンタクト抵抗の増加，甚だし
い時は断線障害を起こす原因となっていた。Therefore, the coverage of the upper wiring film 23 in the contact hole 22 is deteriorated,
For example, the contact area between the upper wiring film 23 and the lower wiring film 19 is reduced, which increases the contact resistance of the wiring film and, in extreme cases, causes a disconnection failure.
【０００７】本発明は，以上の点を鑑み，多層配線のコ
ンタクトホールの形成において，配線膜のカバレッジの
改善及び多層配線膜のコンタクト面積の拡大を行ない，
半導体装置の信頼性を向上させることを目的として提供
されるものである。In view of the above, the present invention improves the coverage of a wiring film and increases the contact area of a multilayer wiring film in forming a contact hole of a multilayer wiring.
It is provided for the purpose of improving the reliability of a semiconductor device.
【０００８】[0008]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は下層絶縁膜，２は下層配線
膜，３は上層絶縁膜，４はレジスト膜，５は開口部，６
は碗型上部ホール，７は筒型下部ホール，８は碗型下部
ホール，９はコンタクトホール，10はテーパー形状, 11
は上層配線膜である。FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a lower insulating film, 2 is a lower wiring film, 3 is an upper insulating film, 4 is a resist film, 5 is an opening, 6
Is a bowl-shaped upper hole, 7 is a cylindrical lower hole, 8 is a bowl-shaped lower hole, 9 is a contact hole, 10 is a tapered shape, 11
Is an upper wiring film.
【０００９】上記の問題点を解決する手段として，基本
的にはコンタクトホールの断面を下部まで傾斜させて上
層配線膜のカバレッジを向上させ，下層配線膜の表面を
凸型にしてコンタクト面積を大きくすれば良い。As means for solving the above problems, basically, the cross section of the contact hole is inclined to the lower part to improve the coverage of the upper wiring film, and the surface of the lower wiring film is made convex to increase the contact area. Just do it.
【００１０】即ち、本発明の目的は、基板表面あるいは
基板上に形成された下層絶縁膜上に、下層配線膜、上層
絶縁膜、レジスト膜を順次形成する工程と、前記レジス
ト膜にコンタクトホール形成のための開口部をパターニ
ングする工程と、前記レジスト膜をマスクとして前記下
層配線膜の周縁部の少なくとも一部が露出するように前
記上層絶縁膜をエッチングし、コンタクトホールを形成
する工程と、前記コンタクトホール内に露出した前記下
層配線膜をエッチングして、前記下層配線膜の周縁部を
テーパー形状とする工程と、前記上層絶縁膜、前記コン
タクトホール及び前記下層配線膜を覆うように上層配線
膜を形成することによって、前記上層配線膜と前記下層
配線膜をコンタクトする工程とを含むことを特徴とする
コンタクトホールの形成方法によって達成される。That is, an object of the present invention is to sequentially form a lower wiring film, an upper insulating film and a resist film on a substrate surface or a lower insulating film formed on the substrate, and to form a contact hole in the resist film. Patterning an opening for forming, etching the upper insulating film so as to expose at least a part of a peripheral portion of the lower wiring film using the resist film as a mask, and forming a contact hole; Etching the lower wiring film exposed in the contact hole to taper the peripheral portion of the lower wiring film; and forming an upper wiring film to cover the upper insulating film, the contact hole and the lower wiring film. Contacting the upper wiring film and the lower wiring film by forming a contact hole. It is achieved by the forming method.
【００１１】[0011]
【作用】本発明は、上記のように、下層配線膜の周縁部
の少なくとも一部が露出するようにコンタクトホールが
形成され、かつ下層配線膜の表面の周縁部を削って凸部
にすることにより、上層配線膜と下層配線膜のコンタク
ト面積が増大している。According to the present invention, as described above, a contact hole is formed so as to expose at least a part of the peripheral portion of the lower wiring film, and the peripheral portion of the surface of the lower wiring film is cut into a convex portion. As a result, the contact area between the upper wiring film and the lower wiring film is increased.
【００１２】[0012]
【実施例】図２は本発明の一実施例の工程順工程順模式
断面図である。図において，12は二酸化シリコン(SiO2)
膜, 13は下層アルミニウム(Al)配線膜, 14は下層燐珪酸
ガラス(PSG) 膜, 15はスピン・オン・グラス(SOG) 膜,
16は上層PSG 膜, 17はコンタクトホール, 18は上層Al配
線膜である。FIG. 2 is a schematic cross-sectional view showing the sequence of steps according to an embodiment of the present invention. In the figure, 12 is silicon dioxide (SiO 2 )
13 is a lower aluminum (Al) wiring film, 14 is a lower phosphosilicate glass (PSG) film, 15 is a spin-on-glass (SOG) film,
16 is an upper PSG film, 17 is a contact hole, and 18 is an upper Al wiring film.
【００１３】図２（ａ）に示すように，SiO2膜12が被覆
されたシリコン(Si)基板上に下層Al配線膜13を形成し，
その上に上層絶縁膜として，下層PSG 膜14を被覆し,SOG
膜15を塗布しエッチバックして平坦化し, 更に上層PSG
膜16を積層する。As shown in FIG. 2A, a lower Al wiring film 13 is formed on a silicon (Si) substrate covered with an SiO 2 film 12,
On top of this, a lower PSG film 14 is coated as an upper insulating film, and SOG
Apply film 15, etch back, flatten, and further upper layer PSG
The film 16 is laminated.
【００１４】この後, 本発明に関する工程は, 図１の工
程順模式断面図により説明する。図１（ａ）に示すよう
に，レジスト膜４にコンタクトホール形成用の開口部５
をパターニングする。Thereafter, the steps related to the present invention will be described with reference to the schematic sectional views of the steps shown in FIG. As shown in FIG. 1A, an opening 5 for forming a contact hole is formed in the resist film 4.
Is patterned.
【００１５】図１（ｂ）に示すように，レジスト膜４を
マスクとして, 上層絶縁膜３の厚さのほぼ半分まで, プ
ラズマエッチングにより, 四弗化炭素(CF4) と酸素(O2)
をそれぞれ50sccm導入し, 基板温度 200℃, マイクロ波
出力１ｋＷの条件で等方性エッチングを行なって, 断面
にテーパーのついた碗型上部ホール６を形成する。As shown in FIG. 1B, using the resist film 4 as a mask, carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) are etched by plasma etching to approximately half the thickness of the upper insulating film 3.
Is introduced under the conditions of a substrate temperature of 200 ° C. and a microwave output of 1 kW to form a bowl-shaped upper hole 6 having a tapered cross section.
【００１６】続いて, 図１（ｃ）に示すように，レジス
ト膜４をマスクとして, 上層絶縁膜３の下部をＲＩＥに
より，CF4 と三弗化メタン(CHF3)をそれぞれ50sccm導入
し,基板温度200 ℃， RF 出力450 Ｗの条件で下層配線
膜が露出するまで異方性エッチングを行なって, 断面が
垂直な筒型下部ホール７を形成する。Subsequently, as shown in FIG. 1C, using the resist film 4 as a mask, CF 4 and methane trifluoride (CHF 3 ) are introduced at a rate of 50 sccm under the upper insulating film 3 by RIE, respectively. Anisotropic etching is performed under the conditions of a substrate temperature of 200 ° C. and an RF output of 450 W until the lower wiring film is exposed to form a cylindrical lower hole 7 having a vertical cross section.
【００１７】図１（ｄ）に示すように，レジスト膜４を
除去し, 再び, 等方性エッチングを上記と同様の条件で
行って，碗型下部ホール８を形成する。その後，図１
（ｅ）に示すように，アルゴン(Ar)スパッタにより，Ar
100sccm,真空度0.2 〜0.7Torr , 出力 350〜400 Ｗで下
層配線膜２の表面をスパッタエッチングして，コンタク
トホール９に露出した下層配線膜２の上縁部をテーパー
形状にする。As shown in FIG. 1D, the resist film 4 is removed, and isotropic etching is performed again under the same conditions as above to form a bowl-shaped lower hole 8. Then, FIG.
As shown in (e), argon (Ar) sputtering
The surface of the lower wiring film 2 is sputter-etched at 100 sccm, a degree of vacuum of 0.2 to 0.7 Torr, and an output of 350 to 400 W, so that the upper edge of the lower wiring film 2 exposed to the contact hole 9 is tapered.
【００１８】そして，上層絶縁膜３及び下層配線膜を覆
って上層配線膜としてAl膜を被覆し, パターニングして
上層配線膜11とする。この結果, 図２（ｂ）に示すよう
な碗型のコンタクトホール17に上層Al配線膜18が埋めこ
まれた多層配線の接続部が得られる。Then, an Al film is covered as an upper wiring film covering the upper insulating film 3 and the lower wiring film, and is patterned to form an upper wiring film 11. As a result, a connection portion of the multilayer wiring in which the upper Al wiring film 18 is buried in the bowl-shaped contact hole 17 as shown in FIG. 2B is obtained.
【００１９】[0019]
【発明の効果】本発明によれば、以上説明したように、
下層配線膜の周縁部の少なくとも一部が露出するように
コンタクトホールが形成され、かつ下層配線膜の表面の
周縁部を削って凸部にすることにより、上層配線膜と下
層配線膜のコンタクト面積が増大する。According to the present invention, as described above,
A contact hole is formed such that at least a part of the peripheral portion of the lower wiring film is exposed, and the peripheral portion of the surface of the lower wiring film is shaved to form a convex portion, so that the contact area between the upper wiring film and the lower wiring film is reduced. Increase.
【００２０】これにより，障害のない安定した多層配線
膜が形成され，高集積，高速の半導体装置の開発に寄与
するところが大きい。As a result, a stable multilayer wiring film free from obstacles is formed, which greatly contributes to the development of a highly integrated and high-speed semiconductor device.
【００２１】[0021]
【図１】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】 本発明の一実施例の説明図FIG. 2 is an explanatory view of one embodiment of the present invention.
【図３】 従来例の説明図FIG. 3 is an explanatory view of a conventional example.
１ 下層絶縁膜 ２ 下層配線膜 ３ 上層絶縁膜 ４ レジスト膜 ５ 開口部 ６ 碗型上部ホール ７ 筒型下部ホール ８ 碗型下部ホール ９ コンタクトホール 10 テーパー形状 11 上層配線膜 12 SiO2膜 13 下層Al配線膜 14 下層 PSG膜 15 SOG膜 16 上層 PSG膜 17 コンタクトホール 18 上層Al配線膜Reference Signs List 1 lower insulating film 2 lower wiring film 3 upper insulating film 4 resist film 5 opening 6 bowl-shaped upper hole 7 cylindrical lower hole 8 bowl-shaped lower hole 9 contact hole 10 taper shape 11 upper wiring film 12 SiO 2 film 13 lower Al Wiring film 14 Lower PSG film 15 SOG film 16 Upper PSG film 17 Contact hole 18 Upper Al wiring film
フロントページの続き (56)参考文献 特開 昭59−159542（ＪＰ，Ａ) 特開 平２−22844（ＪＰ，Ａ) 特開 昭61−247054（ＪＰ，Ａ) 特開 平２−116129（ＪＰ，Ａ) 特開 昭63−258021（ＪＰ，Ａ) 特開 昭63−228736（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3065 H01L 21/3205 H01L 21/768 Continuation of the front page (56) References JP-A-59-159542 (JP, A) JP-A-2-22844 (JP, A) JP-A-61-247054 (JP, A) JP-A-2-116129 (JP) , A) JP-A-63-258021 (JP, A) JP-A-63-228736 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/3065 H01L 21/3205 H01L 21/768
Claims (1)
絶縁膜上に、下層配線膜、上層絶縁膜、レジスト膜を順
次形成する工程と、 前記レジスト膜にコンタクトホール形成のための開口部
をパターニングする工程と、 前記レジスト膜をマスクとして、少なくとも前記下層配
線膜の周縁部の一部が露出するように前記上層絶縁膜を
エッチングし、コンタクトホールを形成する工程と、 前記コンタクトホール内に露出した前記下層配線膜をエ
ッチングして、前記下層配線膜の周縁部をテーパー形状
する工程と、 前記上層絶縁膜、前記コンタクトホール及び前記下層配
線膜を覆うように上層配線膜を形成することによって、
前記上層配線膜と前記下層配線膜をコンタクトする工程
とを含むことを特徴とするコンタクトホールの形成方
法。A step of sequentially forming a lower wiring film, an upper insulating film, and a resist film on a substrate surface or a lower insulating film formed on the substrate; and forming an opening for forming a contact hole in the resist film. Patterning; using the resist film as a mask, etching the upper insulating film so as to expose at least a part of a peripheral portion of the lower wiring film to form a contact hole; Etching the lower wiring film thus formed to taper the periphery of the lower wiring film, and forming the upper wiring film so as to cover the upper insulating film, the contact hole and the lower wiring film,
Contacting the upper wiring film with the lower wiring film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27816791A JP3160960B2 (en) | 1991-10-25 | 1991-10-25 | Semiconductor device and method of forming contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27816791A JP3160960B2 (en) | 1991-10-25 | 1991-10-25 | Semiconductor device and method of forming contact hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05121380A JPH05121380A (en) | 1993-05-18 |
| JP3160960B2 true JP3160960B2 (en) | 2001-04-25 |
Family
ID=17593528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27816791A Expired - Fee Related JP3160960B2 (en) | 1991-10-25 | 1991-10-25 | Semiconductor device and method of forming contact hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3160960B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115360165A (en) * | 2022-08-30 | 2022-11-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor interconnection structure and manufacturing method thereof |
-
1991
- 1991-10-25 JP JP27816791A patent/JP3160960B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05121380A (en) | 1993-05-18 |
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