JP3152559B2 - Semiconductor mounting board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate and, more particularly, to a highly integrated chip-in-board type semiconductor mounting substrate having excellent connection reliability and manufacturability.

[0002]

2. Description of the Related Art Conventionally, when mounting electronic components such as ICs and LSIs on a printed circuit board, a lead wire is inserted into a conductive hole provided on the board, and soldered by flow soldering to fix the connection. The method was mainstream.
In such a method, DIP (Dual in-line packa)
It is common to insert and mount ge) type electronic components. However, in recent years, with the increasing functionality of electronic devices, the density of integrated circuits has been increasing, and the number of terminals has been increasing rapidly. . Therefore, surface mounting technology (SMT) has been developed to connect and fix the terminals of components directly to the wiring pattern on the surface of the printed circuit board without passing the lead wires through the holes. In this mounting technology, electronic components are mounted as a flat package, a leadless chip carrier package, or a tape carrier package.
A method of directly mounting a “bare chip” on a substrate has also been adopted.

[0003] Such mounting means have helped to increase the degree of integration as compared to previously known techniques. However, since the mounting area per electronic component is constant and mounted on the surface of the substrate, the number of mounted electronic components is limited to the size of the mounting area of the substrate, and the electronic components larger than this are limited. When mounting the electronic device, there is a problem in that the substrate must be made large, which hinders downsizing of the electronic device.

On the other hand, recently, attention has been paid to three-dimensional mounting of electronic components. For example, a chip-in-chip having an increased number of mounting units per unit area by apparently mounting bare chips inside a substrate. A board has been proposed (see JP-A-4-298100).

[0005]

However, in the above prior art, since the wiring patterns between the upper and lower substrates are connected using the through holes, the provision of the through holes is
There remains a problem to be solved that the wiring area is obstructed and the mounting density cannot be improved. In addition, connection using a through hole requires a long process from drilling to plating, and when plating is performed in the through hole, it damages electronic components. There was a problem.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to develop a technique that can advantageously solve the above-described problems of the prior art. It is an object of the present invention to provide a chip-in-board type semiconductor mounting substrate which is simple, therefore excellent in manufacturability and excellent in connection reliability.

[0007]

Means for Solving the Problems The inventors of the present invention have made intensive studies for realizing the above object, and as a result, have arrived at an invention having the following content as a gist configuration. That is, the present invention provides a semiconductor mounting substrate having electronic components mounted on a plurality of stacked substrates or inside the substrate, providing a concave portion on at least one inner surface of the substrates to be overlapped, and through the concave portion. The electronic components are mounted, and the laminated substrates are joined face-to-face by solder bumps. The solder bumps are composed of a Sn thin film layer and at least a part of Sn crystal grains formed of Pb.
And a Sn-Pb-coated crystal coated with, and after heating and melting, cooling to form an alloy layer.

[0008]

One of the features of the present invention is that a wiring pattern between a plurality of substrates in a semiconductor mounting substrate is connected by solder bumps. As a result, the area required for connection can be small, and even if the number of connection terminals increases,
High integration of electronic components can be realized without obstructing the mounting area and wiring area. The second feature of the present invention is that, by using the electroless single plating of Sn and Pb without using the substitution type electroless eutectic solder plating,
The point is that a metal layer that becomes a desired solder layer when melted is used as the solder bump. In particular, the point is that a Sn disproportionation reaction is used as the electroless plating of the Sn crystal. Thereby, it is possible to eliminate the shortage of the deposition film thickness, which is a disadvantage of the substitution type electroless eutectic solder plating,
Narrow pitch mounting, which has been considered difficult, can be easily and reliably performed. In addition, the electroless plating by the disproportionation reaction, from an alkaline solution containing no reducing agent,
Disproportionation Asuzusan ion, 2Sn (OH) ₃ ^- caused by _{→ Sn + Sn (OH) 6} 2-, is that the electroless plating of autocatalytic.

The substrate used in the present invention is preferably a so-called resin substrate made of glass epoxy, glass polyimide, glass bismaleimide triazine or the like. The recesses in the substrate as the base board are formed by a method of forming a counterbore by processing the substrate, a method of partially laminating portions other than the mounting portion by a build-up method using a photosensitive interlayer insulating material, or the like.

Here, the metal layer constituting the solder bump is formed of a Sn thin film layer and a Sn—Pb coated crystal in which at least a part of Sn crystal grains is coated with Pb, and is melted. Finally, the Sn / Pb ratio becomes 99.9 / 0.1 to 20.0.
It is desirable that the composition ratio be /80.0. The reason for this is that if the Sn content exceeds 99.9%, it is necessary to set the temperature to a very high temperature during melting, which may damage the substrate and the like. If the content exceeds 80.0%, the solder after melting is easily oxidized.

In the present invention, a concave portion is provided on the substrate,
The reason why the electronic component is mounted at that position is that a gap between the mounted bare chips cannot be obtained with only the solder bumps.

Incidentally, an external connection terminal such as a pin or a solder bump may be provided on the outermost layer of the semiconductor mounting substrate of the present invention, or a heat radiating plate or a heat radiating layer may be formed.

The semiconductor mounting substrate of the present invention can be manufactured by the method described below. (1) First, in manufacturing, a printed board, which is a base board, is manufactured by an ordinary method (such as a subtractive method), and a concave portion for mounting an electronic component is provided on the board by a counterbore method or the like. (2) Next, an electronic component such as a chip is housed and mounted in a recess provided on the substrate. Here, as a method for mounting electronic components, there is a surface mounting method (SMT) by soldering.
), Automatic adhesive mounting method using film as a support (TA
B: Tape automated bonding), wire bonding mounting method (COB: Chip On Board), and flip chip mounting method using solder bumps can be used. (3) The electronic component mounted via the concave portion provided on the surface of the substrate or inside thereof as described above may be sealed with a resin or the like. Then, solder bumps are formed between the inner surfaces of the printed circuit board to be joined, and those surfaces are turned inside, and the solder bumps are melted, thereby joining and integrating with the wiring pattern portion of the other substrate, and apparently, A chip-in-board type semiconductor mounting substrate in which electronic components are also mounted inside the substrate is obtained. Here, the solder bumps are mainly formed on the connection conductors of the printed circuit board.
Forming a Sn thin film layer, forming a Sn crystal on the Sn thin film layer by a disproportionation reaction of Sn based on selective deposition on Sn, at least a part of the Sn crystal, Forming a Sn—Pb coated crystal by substituting and coating with Pb by a Sn—Pb substitution reaction based on the Sn thin film layer formed in the above step, and a Sn— layer in which at least a part of Sn crystal particles is coated with Pb. The Pb-coated crystal is melted by heating, and then cooled to form an alloy layer.

[0014]

【Example】

(Example 1) (1) First, a multilayer printed wiring board was manufactured by a conventional method (see FIG. 1A). In the case of a substrate provided with a concave portion (counterbore portion) for mounting the electronic component 4, no pattern was formed at the mounting position. (2) Of the substrates prepared in the above (1), a mounting concave portion was provided on the substrate for mounting the electronic component 4 by machining (counterboring) to expose the inner layer. The counterbore depth was adjusted so that the height of the electronic component 4 after mounting the electronic component 4 was lower than the height of the non-processed surface of the substrate (FIG. 1).
(b)). (3) Solder was supplied to the printed wiring board obtained in the above (1) and (2) using the following disproportionation reaction to form a solder bump 3 (see FIG. 1 (c)). ). a. Printed wiring board is replaced with a replacement tin plating bath of the following composition
The catalyst was immersed for 30 seconds to perform a catalyst treatment (surface activation treatment). [Substitution tin plating bath] 42% tin borofluoride; 30 g / l thiourea; 80 g / l bath temperature; 80 ° C. b. Next, tin disproportionation reaction plating was performed using a tin disproportionation reaction plating bath having the following composition, and the film was converted to a film thickness by deposition weight of 60%.
A μm tin layer was obtained. [Tin disproportionation reaction plating bath] Potassium hydroxide; 370 g / l stannous chloride; 160 g / l sorbite; 12 g / l TTHA.6Na salt; 28 g / l (expressed as pure components) Bath temperature; . Next, the wiring board on which the tin layer has been formed is immersed in a lead replacement solution having the following composition at 80 ° C. for 3 minutes to form a lead replacement layer.
It was immersed in a glycol-based heat medium bath at 195 ° C. for 12 seconds, and the laminated metal was alloyed (soldered) to produce a wiring board for surface mounting. [Lead replacement liquid] 45% lead borofluoride; 45 cc / l 42% borofluoric acid; 100 cc / l The solder coating layer provided on the obtained wiring board for surface mounting was measured with a fluorescent X-ray micro-thickness meter. The measured film thickness is 50 μm,
Sn / Pb (weight ratio) ≒ 62/38, melting point measured at 188 ° C,
Excellent solder properties were exhibited. (4) The electronic component 4 was mounted on the counterbored portion of the surface mounting wiring board obtained in the above (3) using a reflow machine (FIG. 1).
(d)). (5) On the substrate that has been subjected to the processes (1) to (4),
Another substrate prepared in (1) was joined by reflow melting the solder bumps 3 applied to the non-counterbore portions on the counterbore portion forming surface side to prepare a chip-in-board type semiconductor mounting substrate (FIG. 1 (e)).

Embodiment 2 (1) As described below, a multi-layer method is employed in which a portion other than an electronic component mounting portion is partially laminated by a build-up method using a photosensitive resin material without performing counterboring. A chip-in-board type semiconductor mounting board was produced in the same manner as in Example 1 except that a concave portion (electronic component mounting portion) for mounting the electronic component 4 was formed on the printed wiring board (see FIG. 2). ). In FIG. 2, it is desirable that the photosensitive insulating layer 5 be formed after the via hole 8 or the through hole 7 is filled and flattened with a resin or the like. This is because the final bump formation surface is flattened and the connection reliability between the bumps is improved. a. Mix 1275 parts by weight of melamine resin, 1366 parts by weight of 37% formalin and 730 parts by weight of water, and adjust the pH with 10% sodium carbonate.
= 9.0 and maintained at 90 ° C. for 60 minutes, and then 109 parts by weight of methanol was added to obtain a resin solution. b. This resin liquid was dried by a spray drying method to obtain a powdery resin. c. The resin powder obtained in the step b, the release agent, and the curing catalyst were pulverized and mixed in a ball mill to obtain a mixed powder. d. Place the mixed powder in a mold heated to 150 ° C,
The molded product was held at a pressure of 0 kg / cm ² for 60 minutes. In this molding, the mold was opened and degassing was performed. e. The molded product obtained in the step d was pulverized and pulverized with a ball mill to obtain powders having particle diameters of 0.5 μm and 5.5 μm. f. 60 parts by weight of a phenol novolak type epoxy resin (manufactured by Yuka Shell), 40 parts by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell) and 5 parts by weight of an imidazole-based curing agent (manufactured by Shikoku Chemicals) were dissolved in butyl cellosolve acetate. With respect to 100 parts by weight of the solid content of the composition, 15 parts by weight of the fine powder prepared in step e above and 30 parts by weight of the fine powder having a particle size of 5.5 μm were mixed.
The mixture was kneaded with this roll, and butyl cellosolve acetate was further added to prepare an adhesive solution having a solid content of 75%.
The viscosity of this solution was measured at 20 ° C. for 60 seconds using a digital viscometer manufactured by Tokyo Keiki in accordance with JIS-K7117. The viscosity was 5.2 Pa · s at 6 rpm and 2.6 Pa · s at 60 rpm. The value (thixotropic property) was 2.0. g. The glass epoxy substrate is roughened by polishing, and JIS-B0
After forming a roughened layer of 601 R _max = 2 to 3 μm, the adhesive solution prepared in step f above was applied to the substrate using a roll coater. The coating method used at this time was a coating roll for resist for medium and high viscosity (made by Dainippon Screen) with a gap of 0.4 mm between the coating roller and the doctor bar, and a gap of 1.4 mm between the coating roller and the backup roller. Transfer speed 400m
m / s. Then, after standing for 20 minutes in a horizontal state,
By drying at 70 ° C., an adhesive layer 5 having a thickness of about 50 μm was formed. h. The substrate on which the adhesive layer 5 is formed is immersed in an oxidizing agent composed of a 500 g / l chromic acid (CrO ₃ ) aqueous solution at 70 ° C. for 15 minutes to roughen the surface of the adhesive layer 5 and then neutralized. (Made by Shipley Co.) and washed with water. The surface of the adhesive layer 5 was activated by applying a palladium catalyst (manufactured by Shipley) to the substrate having the adhesive layer 5 roughened. i. Next, the substrate subjected to the treatment h was subjected to a heat treatment for fixing the catalyst at 120 ° C. for 30 minutes in a nitrogen gas atmosphere (10 ppm). j. Next, a resin solution obtained by imparting photosensitivity to the adhesive solution prepared in the step f above was applied on the substrate treated in the step i.
Was applied using a roll coater in the same manner as described above. The obtained coating layer was subjected to a heat treatment at 80 ° C. for 30 minutes in order to remove the solvent, then exposed through a mask for pattern formation, developed with an Eterna IR (manufactured by Asahi Kasei), and then irradiated with ultraviolet rays (UV After curing, a heat treatment was performed to form a plating resist 6 (40 μm in thickness). k. After the plating resist 6 has been formed, the substrate obtained in j is immersed in an electroless copper plating solution having the composition and conditions shown in Table 1 for 11 hours to form a conductor portion 1. Electroless copper plating of 25 μm was applied. l. In the wiring pattern thus obtained, the surface of the resist 6 is further buff-polished, while the surface of the chemical copper plating is blackened, and then the above processes g to k (formation of the adhesive layer 5 to plating) By repeating formation of the resist 6 to electroless copper plating), a plurality of wiring patterns were laminated. m. Finally, a photoresist is formed as the solder resist 2 using the resin composition obtained by removing the filler from the adhesive layer composition of the above f, and a photoresist is formed in the same manner as in h. Was formed.

[0016]

[Table 1]

(Comparative Example 1) As shown in FIG. 3, a semiconductor mounting substrate in which surface mounting substrates were connected to each other using a connector was manufactured.

Comparative Example 2 As shown in FIG. 4, a semiconductor mounting substrate in which surface mounting substrates were pin-connected to each other was manufactured.

(Comparative Example 3) As shown in FIG. 5, a semiconductor mounting substrate in which surface mounting substrates were connected to each other using a flexible substrate was manufactured.

The degree of integration, connection reliability, and manufacturability of the semiconductor mounting substrate manufactured as described above were compared. Table 2 shows the results. As is clear from the results shown in this table, the semiconductor mounting board according to the present invention was excellent in all of the degree of integration, connection reliability and manufacturability, unlike other semiconductor mounting boards.

[0021]

[Table 2]

(Embodiment 3) A chip-in-board type semiconductor mounting substrate according to the present invention is a BGA (ball grid array) type (see FIG. 6), which is one of the integrated circuit package systems, and a QFP (quad flat). It can be used for packages having various structures such as a package) type (see FIG. 7) and a PGA (pin grid array) type (see FIG. 8).

[0023]

As described above, in the semiconductor mounting substrate of the present invention, the wiring pattern between a plurality of substrates is connected by solder bumps, and the solder bumps are connected to the Sn thin film layer and at least the Sn crystal particles. Partly covered with Pb
Since it was formed with Sn-Pb coated crystal and was heated and melted and then cooled to form an alloy layer, even if the number of connection terminals increased, the mounting area and wiring area were not hindered even if the number of connection terminals increased. In addition to realizing the integration, the shortage of the deposited film thickness, which is a drawback of the conventional substitution type electroless eutectic solder plating, can be eliminated, and the mounting at a narrow pitch can be easily performed with high reliability. Therefore, a highly integrated chip-in-board type semiconductor mounting substrate excellent in connection reliability and manufacturability can be provided.

[Brief description of the drawings]

FIG. 1 is a view showing one manufacturing process according to a semiconductor mounting substrate of the present invention.

FIG. 2 is a schematic view showing a cross section of a surface mounting substrate when an electronic component mounting concave portion is formed by another method.

FIG. 3 is a schematic diagram showing a semiconductor mounting substrate in which surface mounting substrates are connected to each other using a connector.

FIG. 4 is a schematic view showing a semiconductor mounting substrate in which surface mounting substrates are connected to each other using pins.

FIG. 5 is a schematic view showing a semiconductor mounting substrate in which surface mounting substrates are connected to each other using a flexible substrate.

FIG. 6 is a schematic view showing a package structure when the semiconductor mounting substrate according to the present invention is applied to a BGA type package.

FIG. 7 is a schematic view showing a package structure when the semiconductor mounting substrate according to the present invention is applied to a QFP type package.

FIG. 8 is a schematic diagram showing a package structure when the semiconductor mounting substrate according to the present invention is applied to a PGA type package.

[Explanation of symbols]

 Reference Signs List 1 conductor 2 solder resist 3 solder (solder bump) 4 electronic component 5 photosensitive insulating layer (photosensitive adhesive layer) 6 plating resist 7 through hole 8 via hole

Continuation of the front page (56) References JP-A-4-370957 (JP, A) JP-A-6-45517 (JP, A) JP-A-63-156395 (JP, A) JP-A-61-39551 (JP) JP-A-7-106509 (JP, A) JP-A-6-216492 (JP, A) WO 93/25060 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) H01L 25/00 H01L 23/12 H01L 21/60 H05K 1/14 H05K 1/18 H05K 3/46

Claims (2)

(57) [Claims] 1. A semiconductor mounting substrate having electronic components mounted on or inside a plurality of stacked substrates, wherein a concave portion is provided on at least one inner side surface of the substrates to be superimposed, and an electronic component is provided through the concave portion. While mounting the components, the Sn thin film layer and at least a part of the Sn crystal particles are covered with Pb.
Sn-Pb-coated crystals that are covered
A semiconductor mounting substrate wherein the laminated substrates are joined face-to-face by solder bumps that are cooled to form an alloy layer . 2. The solder bump is formed of a Sn thin film layer and a Sn—Pb coated crystal in which at least a part of Sn crystal particles is coated with Pb. The semiconductor mounting substrate according to claim 1.